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Fujitsu MB15F74UL Datasheet page 12

Dual serial input pll frequency synthesizer
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MB15F74UL
4. Serial Data Data Input Timing
Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
Data
Clock
LE
Parameter
Min
t
20
1
t
20
2
t
30
3
t
30
4
Note : LE should be "L" when the data is transferred into the shift register.
12
1st data
MSB
t
t
1
2
t
7
Typ
Max
Unit
ns
ns
ns
ns
Invalid data
Control bit
LSB
t
3
t
t
4
5
Parameter
Min
Typ
t
100
5
t
20
6
t
100
7
2nd data
t
6
Max
Unit
ns
ns
ns

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