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Block Diagram - Fujitsu MB15F74UL Datasheet

Dual serial input pll frequency synthesizer
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MB15F74UL

BLOCK DIAGRAM

Intermittent
PS
(5)
IF
mode control
(IF-PLL)
(1)
fin
IF
Prescaler
(IF-PLL)
(32/33, 64/65)
(2)
Xfin
IF
(19)
OSC
IN
OR
Prescaler
fin
(15)
RF
(RF-PLL)
Xfin
(
)
14
RF
(64/65, 128/129)
Intermittent
mode control
PS
(11)
RF
(RF-PLL)
Schmitt
LE
(16)
circuit
Schmitt
Data
(17)
circuit
Schmitt
Clock
(18)
circuit
4
3 bit latch
7 bit latch
Binary 7-bit
swallow counter
(IF-PLL)
2 bit latch
14 bit latch
Binary 14-bit pro-
grammable ref.
T1
T2
counter(IF-PLL)
Binary 14-bit pro-
T1
T2
grammable ref.
counter (RF-PLL))
2 bit latch
14 bit latch
Binary 7-bit
swallow counter
(RF-PLL)
3 bit latch
7 bit latch
Latch selector
C
C
N
N
23-bit shift register
1
2
V
GND
CCIF
(4)
11 bit latch
Phase
Binary 11-bit
programmable
comp.
(IF-PLL)
counter (IF-PLL)
fp
IF
1 bit latch
C/P setting
counter
fr
IF
fr
RF
C/P setting
counter
1 bit latch
fp
RF
Phase
Binary 11-bit
comp.
programmable
(RF-PLL)
counter (RF-PLL)
fp
RF
11 bit latch
(20)
(12)
GND
V
GND
CCRF
Vp
IF
IF
(3)
(6)
Charge
(7)
Current
pump
Switch
(IF-PLL)
Lock Det.
(IF-PLL)
LD
IF
Fast
lock
Tuning
Selector
AND
LD
fr
IF
(8)
fr
RF
fp
IF
fp
RF
LD
RF
Lock Det.
(RF-PLL)
Charge
Current
(9)
pump
Switch
(RF-PLL)
(13)
(10)
Vp
RF
RF
Do
IF
LD
fout
Do
RF

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