AGB Programming Manual
3.3.1 Access Timing
The following timing charts illustrate Game Pak ROM access with 3 wait
cycles on the first access and 1 wait cycle on the second.
1) Sequential Access
System Clock
16.78 MHz
Wait Cycles
AD Bus
2) Random Access
System Clock
16.78 MHz
Wait Cycles
AD Bus
©1999 - 2001 Nintendo of America Inc.
wait
wait
wait
Address
1st Access
(3 wait cycles)
wait
wait
wait
Address
1st Access
(3 wait cycles)
23
wait
wait
Data
Data
2nd Access
3rd Access
(1 wait cycle)
(1 wait cycle)
wait
wait
wait
Data
Address
1st Access
(3 wait cycles)
AGB Memory
Data
Data
D.C.N. AGB-06-0001-002B4