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Nintendo 1504166 - Game Boy Advance SP Edition Console Programming Manual

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April 2, 2001
AGB Programming Manual
Version 1.1
1999 - 2001 Nintendo of America Inc.

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Summary of Contents for Nintendo 1504166 - Game Boy Advance SP Edition Console

  • Page 1 April 2, 2001 AGB Programming Manual Version 1.1 1999 - 2001 Nintendo of America Inc.
  • Page 2 AGB Programming Manual “Confidential” This document contains confidential and proprietary information of Nintendo and is also protected under the copyright laws of the United States and other countries. No part of this document may be released, distributed, transmitted or reproduced in any...
  • Page 3 AGB is an innovation born from experience. While providing backwards compatibility with the enormous software resources available for the 100 million Game Boy units in use worldwide, it also breaks new ground for portable game devices. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 4 03/10/2000 -Improved the description of interrupt and multiple interrupt process. 03/10/2000 -Improved the description of system call and multiple system call process. 0.4.1.2 04/06/2000 -Added the description of UART system communication. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 5 -Revised the connection diagram of 16 bit multi-play communication. -Added a description to all sound operation modes of the sound control register. -Revised the itemized description of Chapter 10 "Sound". D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 6 *Added the restrictions to the description of the repeat flag in DMA3. *Updated the timing chart and the cable connection diagram for the multi- play communication. *Revised the description of the normal serial communication cautions. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 7 084h SGCNT1 SOUNDCNT_X à à 088h SG_BIAS SOUNDBIAS à à 060h~ SG10_(L H) SOUND1CNT_(L H) ** à à 064h SG11 SOUND1CNT_X à à 068h SG20 SOUND2CNT_L à à 06Ch SG21 SOUND2CNT_H D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 8 à JOYSTAT 158h JOYRE_(L H) à à JOY_RECV_(L H) ** 150h~ JOYTR_(L H) à à JOYTRANS_(L H) ** 154h~ --Key Related-- P1 à à KEYINPUT 130h P1CNT à à KEYCNT 132h D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 9: Table Of Contents

    6.1.4 Character Data Format ....................42 6.1.5 BG Screen Data Format .....................43 6.1.6 BG Screen Data Address Mapping for the LCD Screen..........45 6.1.7 BG Rotation and Scaling Features ................49 6.1.8 BG Scrolling ......................52 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 10 1 ........................87 OUND 10.4 S 2 ........................91 OUND 10.5 S 3 ........................93 OUND 10.6 S 4 ........................97 OUND 10.7 S ....................100 OUND ONTROL 10.8 S PWM C ..................104 OUND ONTROL 11 TIMER....................106 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 11 16.1 S ......................163 UNCTION 16.2 H ......................164 UNCTION 17 AGB SYSTEM CALLS ..............165 17.1 S ..................165 YSTEM PERATION 17.1.1 Normal Calls ......................165 17.1.2 Multiple Calls ......................167 18 ROM REGISTRATION DATA ............170 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 12 Can be set to either 0 or 1. Must be set to a specified fixed value. 3. Abbreviations Nintendo's game hardware is abbreviated as follows: Ø DMG (Game Boy) Ø CGB (Game Boy Color) Ø AGB (Game Boy Advance) Ø DOL (Nintendo GameCube) D.C.N.

  • Page 13: Agb System

    AGB is a portable game device that maintains downward compatibility with Game Boy Color (CGB) and provides higher performance. AGB’s 2.9-inch-wide reflective TFT color LCD and 32-bit RISC CPU enable production of games that match or surpass the Super Nintendo Entertainment System (Super NES) in performance. AGB CPU 32-bit RISC CPU (ARM7TDMI)/16.78 MHz...
  • Page 14 The following Game Paks operate on the AGB system. DMG Game Paks, DMG/CGB dual mode Game Paks, and CGB dedicated Game Paks AGB dedicated Game Paks(Game Paks that only function with AGB) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 15: System Configuration

    + PWM) Special Color Processing Circuit R:8/16/32 W:8/16/32 Control RGB(5:5:5) * "R:8/16/32" and "W:8/16/32" mean that you can access an area of 8bits/16bits/32bits when reading LCD Unit and writing, respectively. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 16: Complete Block Diagram

    General Purpose Bus Memory Space 64KByte Max. AD Bus Memory General Purpose Bus Space Memory Space 32MByte Max. 32KByte Max. Power 3.3V AGB Game Pak(AGB Only) Power 5V DMG/CGB Game Pak D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 17: Memory Configuration And Access Width

    In the AGB CPU, memory addresses are allocated in 8-bit increments, and little- endian format is used in implementing the 8-, 16-, and 32-bit access widths. Memory Register d24 d23 d16 d15 d08 d07 0003h 0002h 0001h 0000h D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 18: Agb Memory

    (1 Kbyte) 05000000h I/O, Registers 04000000h 03007FFFh CPU Internal Working RAM (32 Kbytes) 03000000h 0203FFFFh CPU External Working RAM (256 Kbytes) 02000000h 00003FFFh Unused Area System ROM (16 Kbytes) 00000000h Image Area D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 19: Memory Configuration

    The 96 Kbytes from 06000000h is the VRAM area. This area is for BG and OBJ data. 7) OAM The 1 Kbyte from 07000000h is Object Attribute Memory (OAM). It holds the objects to be displayed and their attributes. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 20: Game Pak Memory

    512 Kbits of SRAM or Flash Memory can be stored here. However, it is an 8 bit data bus. Due to the specifications, any Game Pak device other than ROM must be accessed using Nintendo's library. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 21: Game Pak Memory Wait Control

    Prefetch Buffer, the fetch is completed with no wait in respect to the CPU. If there is no hit, the fetch is done from the Game Pak ROM and there is a wait based on the set wait state. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 22 Wait cycles for the Game Pak RAM can be set. The relation between the wait control settings and wait cycles is as follows. Use the appropriate settings for the device you are using. Wait Control Value Wait Cycles D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 23: Access Timing

    2) Random Access System Clock 16.78 MHz Wait Cycles wait wait wait wait wait wait AD Bus Address Data Address Data 1st Access 1st Access (3 wait cycles) (3 wait cycles) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 24: Game Pak Bus

    AD10 AD11 AD12 AD13 AD14 AD15 Address(upper) Data /CS2 /CS2 RAM Chip Selection IREQ and Terminal used for IREQ IREQ and Terminal used for IREQ DREQ and DREQ DREQ and DREQ D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 25: Lcd

    16.212 s horizontal blank Number of 68 lines 4.994 ms horizontal lines per vertical blank Scanning H interval frequency 13.618 KHz 73.433 s cycle V interval frequency 59.727 Hz 16.743 ms D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 26: Lcd Status

    VCOUNT 0000h V counter value 0-227 A value of 0-227 is read. A value of 0-159 indicates that rendering is in progress; a value of 160-227 indicates a vertical blanking interval. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 27: General Lcd Status

    DISPSTAT [d04] H-Blank Interrupt Request Enable Flag Allows an interrupt request to be generated during horizontal blanking. DISPSTAT [d03] V-Blank Interrupt Request Enable Flag Allows an interrupt request to be generated during vertical blanking. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 28 DISPSTAT [d01] H-Blank Status Can check whether a horizontal blanking interval is currently in effect. DISPSTAT [d00] V-Blank Status Can check whether a vertical blanking interval is currently in effect. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 29: Image System

    Master flag that controls whether windows 0 and 1 are displayed. For information on windows, see “Chapter 8, Window Feature”. DISPCNT [d12-08] Individual Screens Display Flag Allows individual control of whether BG0, BG1, BG2, BG3, and OBJ, respectively, are displayed. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 30 DISPCNT [d02-00] BG Mode Selects the BG mode from a range of 0-5. For more information on BG modes, see the following section. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 31: Bg Modes

    The method of controlling text BG scrolling is different from that of BG rotation/scaling and bitmap BG scrolling. (See “6.1.8 BG Scrolling” and “6.1.7 BG Rotation and Scaling Features”.) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 32: Vram Memory Map

    BG modes 0, 1, and 2. For more information, see section 6.1.3, VRAM Address Mapping of BG Data. In addition, see the descriptions below for more information on the memory areas and the data formats for each area. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 33: Rendering Functions

    BG2CNT and BG3CNT also support BG rotation and scaling control. The registers used by the BG modes are as follows. BG Mode BG Control Register BG0CNT BG1CNT BG2CNT BG3CNT (text) (text) (text) (text) (text) (text) (rotation/scaling) (rotation/scaling) (rotation/scaling) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 34 10: 3rd priority 1: Enable 11: 4th priority Character Base Block Color Mode 0: 16 colors x 16 palettes 1: 256 colors x 1 palette Screen Base Block 0-31 Screen Size D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 35 Screen Size Screen Data Screen Size Screen Data 256×256 2 Kbytes 128×128 256 Bytes 512×256 4 Kbytes 256×256 1 Kbyte 256×512 4 Kbytes 512×512 4 Kbytes 512×512 8 Kbytes 1024×1024 16 Kbytes D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 36 Virtual screen size: 512 x 512 (256 x 256) (256 x 256) (256 x 256) Display Screen Display Screen (240 x 160) (240 x 160) (256 x 256) (256 x 256) (256 x 256) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 37 Virtual screen size: 512 x 512 Virtual screen size: 1024 x1024 (1024 x (512 x 512) 1024) Transparent Display Screen (240 x 160) Transparent Display Screen (240 x 160) Transparent Transparent Transparent Transparent D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 38 Values of 0 (highest priority) to 3 can be specified. When the BG priority has been changed, care should be taken in specifying the pixels used for color special effects. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 39: Mosaic Size

    45 46 47 48 49 00 00 00 00 51 52 53 54 55 56 00 00 00 00 60 61 62 63 64 68 69 70 71 72 73 74 77 78 79 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 40: Vram Address Mapping Of Bg Data

    BG control register. The amount of data depends on the type of BG screen (text or rotation/scaling) and the screen size. These can be set by the BG control register. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 41 Base Block 8 Base Block 7 Base Block 6 Base Block 5 Base Block 4 Base Block 0 Base Block 3 Base Block 2 Base Block 1 0000h Base Block 0 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 42: Character Data Format

    8 dots D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 43: Bg Screen Data Format

    Enables the BG character to be flipped vertically. A setting of 1 produces the vertical-flip display. [d10] Horizontal Flip Flag Enables the BG character to be flipped horizontally. A setting of 1 produces the horizontal-flip display. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 44 16 colors x 16 palettes) and rotation/scaling BG screens (which can handle only 256 colors x 1 palette) may be used together. Therefore, the VRAM mapping status should be sufficiently understood when programming. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 45: Bg Screen Data Address Mapping For The Lcd Screen

    LCD Display Area 1-2) Virtual Screen Size of 512 x 256 Dots 512 dots (64 blocks) 256 dots 256 dots (32 blocks) (32 blocks) 256 dots (32 blocks) LCD Display Area D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 46 256 dots (64 blocks) 256 dots (32 blocks) (32 blocks) 256 dots (32 blocks) 512 dots (64 blocks) 1000 103E 1800 183E 256 dots (32 blocks) 17C0 17FE 1FFE LCD display area D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 47 LCD display area 2-2) Virtual Screen Size of 256 x 256 Dots 256 dots (32 blocks) 240 dots (30 blocks) 160 dots (20 blocks) 256 dots (32 blocks) LCD display area D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 48 (30 blocks) 160 dots (20 blocks) 1024 dots (128 blocks) 3F00 3F01 3F02 3F03 3F04 3F1D 3F1E 3F7E 3F7F 3F80 3F81 3F82 3F83 3F84 3F9D 3F9E 3FFE 3FFF LCD display area D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 49: Bg Rotation And Scaling Features

    (distance moved in direction y, next line) = ( 1 / ) cos y-axis : Magnification along x-axis : Magnification along y-axis BG rotation and scaling are implemented in AGB using the following arithmetic expressions. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 50 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Address Register 026h BG2PD dmy: distance of movement in y direction along next line 0100h 036h BG3PD D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 51 BG control register can be used to select whether the area of the screen into which the overflow occurs is transparent or wraps around the display screen. For information on BG control, see “6.1.1 BG Control”. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 52: Bg Scrolling

    15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 012h BG0VOFS 0000h 016h BG1VOFS 01Ah BG2VOFS 01Eh BG3VOFS V offset Offset Illustration V Offset H Offset Display Screen Screen D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 53: Bitmap Mode Bgs (Bg Modes 3-5)

    Due to the fact that in Bitmap Mode there is only one BG plane(other than the backdrop plane), there is no priority relationship among BGs, but you can set up priorities with OBJ. For information on this, see “6.4 Display Priority of OBJ and BG”. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 54: Bg Rotation/Scaling

    2. 256-Color (of 32,768) Display Format (BG Mode 4) Palette RAM color data (256 of the 32,768 colors storable) are referenced. Each pixel uses 1 byte. 07 06 05 04 03 02 01 00 Color No. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 55: Pixel Data Address Mapping For The Lcd Screen

    1265Eh 12660h 12662h 12664h 12666h 12668h 12838h 1283Ah 1283Ch 1283Eh 12840h 12842h 12844h 12846h 12848h 12A18h 12A1Ah 12A1Ch 12A1Eh 12A20h 12A22h 12A24h 12A26h 12A28h 12BF8h 12BFAh 12BFCh 12BFEh VRAM address (+06000000h) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 56 1332Fh 13330h 13331h 13332h 13333h 13334h 1341Ch 1341Dh 1341Eh 1341Fh 13420h 13421h 13422h 13423h 13424h 1350Ch 1350Dh 1350Eh 1350Fh 13510h 13511h 13512h 13513h 13514h 135FCh 135FDh 135FEh 135FFh VRAM address (+06000000h) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 57 13C3Eh 13C40h 13C42h 13C44h 13C46h 13C48h 13D78h 13D7Ah 13D7Ch 13D7Eh 13D80h 13D82h 13D84h 13D86h 13D88h 13EB8h 13EBAh 13EBCh 13EBEh 13EC0h 13EC2h 13EC4h 13EC6h 13EC8h 13FF8h 13FFAh 13FFCh 13FFEh VRAM address (+06000000h) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 58: Obj (Object)

    “×4” expresses the number of cycles that the OBJ Rendering Circuit can use per one dot. “-6” represents the number of cycles needed for processing before OBJ rendering at the start of the H Line. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 59 If the number for non-displayed (outside of the screen) OBJ in the OAM is lower than that for displayed OBJ, the bigger the non-displayed OBJ's size is, the less efficient the rendering will be. Please be aware of this problem. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 60: Character Data Mapping

    (16 colors/16 palettes) 32x32 dots (16 colors/16 palettes) 8x16 dots (16 colors/16 palettes) 64x64 dots 16x16 dots (16 colors/16 palettes) (256 colors/1 palette) Character mapping area (character no.in hexadecimal notation) Character name D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 61 1 basic character n+56 n+57 n+58 n+59 n+60 n+61 n+62 n+63 100h 3 2 b y t e s 0FFh 16 x 16-dot character (256 colors x 1 palette format) 000h Character name D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 62: Oam

    Rotation/Scaling Parameter PD-31 Attribute 2 Attribute 1 OBJ127 Attribute 0 Rotation/Scaling Parameter PB-0 Attribute 2 OBJ1 Attribute 1 Attribute 0 Rotation/Scaling Parameter PA-0 Attribute 2 OBJ0 Attribute 1 Attribute 0 07000000h 16 Bits D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 63 Specifies whether the OBJ data format is 16 colors x 16 palette mode or 256 colors x 1 palette mode. [d12] OBJ Mosaic Flag Turns mosaic for OBJs on and off. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 64 OBJ field, by setting the double-size flag to 1. With this setting, the OBJ does not surpass the boundaries of the OBJ field even if the OBJ display is magnified by up to two-fold. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 65 With the OBJ rotation/scaling feature enabled by setting this bit to 1, the maximum number of OBJs displayed per line is decreased. Please refer to the description in Section 6.3.1 on OBJ Display Capability on a Single Line. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 66 OBJ Attribute 1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x-coordinate Rotation/scaling parameter selection 0-31 Horizontal flip flag Vertical flip flag OBJ Size D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 67 [d13-09] Rotation/Scaling Parameter Selection The parameters used in OBJ rotation/scaling processing are selected from the 32 parameters registered in OAM. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 68 16 colors x 16 palettes (color mode=1) Allows selection of 1,024 characters. 256 colors x 1 palette (color mode=0) Allows selection of 512 characters. Bit 0 fixed at 0 in 2-dimensional mapping mode. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 69 Rendering Functions BG Mode is 3~5 (Bitmap Mode) OBJ character data RAM is halved to 16 KB, so character name numbers 0-511 are disabled and numbers 512 and greater are used. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 70: Obj Rotation/Scaling Feature

    The center of rotation is fixed at the center of the OBJ field. If a reference point surpasses the specified OBJ size, it becomes transparent. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 71 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 dmy: distance moved in y direction along next line D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 72: Display Priority Of Obj And Bg

    BG is between the OBJs. Please be cautious not to let this situation occur. Examples of when display is not right: OBJ-No.0 (OBJ priority 2) BG (BG priority 1) OBJ-No.1 (OBJ priority 0) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 73: Color Palettes

    Color 0 transparency is used to render the pixels of low-priority OBJs or BGs as transparent. The color specified for color 0 of BG palette 0 is applied to the backdrop, which has the lowest priority. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 74: Color Palette Ram

    (of 32,768) that can be specified. The memory map of the OBJ and BG palettes is shown in the follow figure. Palette RAM 050003FFh Palette RAM 512 bytes 05000200h 050001FFh Palette RAM 512 bytes 05000000h D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 75 Color 13 Palette 0 Palette 8 Color 14 Palette 9 Color 15 Palette 10 Palette 11 Palette 12 Color 252 Palette 13 Color 253 Palette 14 Color 254 Palette 15 Color 255 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 76: Color Data Format

    15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 B4 B3 B2 B1 B0 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0 Blue Green D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 77: Window Feature

    WIN0V Left-upper y-coordinate of window Right-lower y-coordinate of window 0000h 046h WIN1V Window Display Example Window 0 has a higher display priority than Window 1. Window 0 Window 1 Display Screen D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 78: Window Control

    1: Display 1: Display Color Special Effects Flag Color Special Effects Flag 0: Disable color special effects 0: Disable color special effects 1: Enable color special effects 1: Enable color special effects D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 79 A setting of 0 turns display off, and 1 turns display on. WININ [d13][d05], WINOUT[d13][d05] Color Special Effects Flags A setting of 0 disables color special effects; 1 enables them. For information on color special effects, see “9 Color Special Effects”. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 80: Color Special Effects

    Color Special Effects Setting 2nd Target Pixel Although color special effects are specified by the BLDCNT register, for blending, which involves processing between surfaces, the 2 target surfaces must have suitable priorities. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 81 When OBJ=1 for the 1st target screen, processing for decreased brightness is performed only for normal objects. If a semi-transparent OBJ is the 1st target screen, blending processing is always executed. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 82: Color Special Effects Processing

    The values of EVA, EVB, and EVY are numbers less than 1 and are obtained by multiplying 1/16 by an integer. EVA, EVB, EVY Coeff. EVA, EVB, EVY Coeff. 8/16 1/16 9/16 2/16 10/16 3/16 11/16 4/16 12/16 5/16 13/16 6/16 14/16 7/16 15/16 16/16 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 83 Display color (R) = 1st pixel (R) - 1st pixel (R) ×EVY Display color (G) = 1st pixel (G) - 1st pixel (G) ×EVY Display color (B) = 1st pixel (B) - 1st pixel (B) ×EVY D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 84: Sound

    Sound 3 9bit Addition 4-Fold Sound 4 9bit Selection Direct Sound A & FIFO A Addition DMA1 9bit 1-Fold/2-Fold (8 Words) Direct Sound B FIFO B DMA2 9bit 1-Fold/2-Fold (8 Words) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 85: Direct Sounds Aandb

    8 bits of linear audio data to the FIFO with a CPU write. Specify the transfer mode for DMA 1 or 2 (see 12.2 “DMA 1 and 2”). Specify the direct sound outputs settings in the sound control register. Start the timer. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 86 3. If the DMA channel receiving the request is in sound FIFO transfer mode, 4 words of data are provided to the sound FIFO (the DMA WORD COUNT is ignored). The preceding is repeated starting from 1. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 87: Sound1

    6/f128 (46.9 ms) 7/f128 (54.7 ms) (f128=128Hz) SOUND1CNT_L [d03] Sweep Increase/Decrease Specifies whether the frequency increases or decreases. When the sweep function is not used, the increase/decrease flag should be set to 1. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 88 Envelope initial value SOUND1CNT_H [d15 - 12] Envelope Initial-Value Allows specification of any of 16 levels ranging from maximum to mute. SOUND1CNT_H [d11] Envelope Increase/Decrease Specifies whether to increase or decrease the volume. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 89 Waveform 12.5% 25.0% 50.0% 75.0% SOUND1CNT_H [d05 - 00] Sound Length With st signifying the sound length, the length of the output sound is determined by the following formula. time (sec) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 90 8 clocks or more. Unless the initialization flag is set twice with an interval of 8 clocks or more, the sound may not be heard. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 91: Sound2

    With n signifying the value specified, the length of 1 step (step time) is determined by the following formula. steptime (sec) When n=0, the envelope function is turned off. SOUND2CNT_L [d07 - 06] Waveform Duty Cycle Specifies the proportion of waveform amplitude peaks. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 92 (Reset sound length flag of NR24), always set 0 for data of sound length (lower 6 bits of NR21) after setting frequency data. If 0 is not set, sound may stop prematurely. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 93: Sound3

    RAM bank specification) is played, followed immediately by the data in the back bank. The front bank 32 steps and the back bank 32 steps combine to form a waveform pattern with a total of 64 steps. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 94 Sound Length Flag Frequency Data 0: Continuous 1: Counter Initializaton Flag SOUND3CNT_X [d15] Initialization Flag When SOUND3CNT_L [d07] is 1, a setting of 1 in this bit causes Sound 3 to restart. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 95 (Reset the sound length flag of NR34), always set 0 for the data of sound length (NR31) after setting the frequency data. If 0 is not set, sound may stop prematurely. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 96 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Attributes Initial Value Address Register WAVE_ Step 30 Step 31 Step 28 Step 29 09Eh RAM3_H D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 97: Sound4

    When n = 0, the envelope function is turned off. SOUND4CNT_L [d05 - 00] Sound Length With st signifying the sound length, the length of the output sound is determined by the following formula. time (sec) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 98 However, %1110 and %1111 are prohibited codes. SOUND4CNT_H [d03] Polynomial Counter Step Number Selection A value of 0 selects 15 steps; 1 selects 7 steps. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 99 When a value is written to the envelope register, sound output becomes unstable before the initialization flag is set. Therefore, set initialization flag immediately after writing a value to the envelope register. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 100: Sound Control

    However, there is no effect on direct sound. SOUNDCNT_L [d02 - 00] R Output Level R output level can be set to any of 8 levels. However, there is no effect on direct sound. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 101 Each sound circuit’s status can be referenced. Each sound is set during output, and when in counter mode it is reset after the time passes which was set up with the length data. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 102 L Output of Direct Sound B 0: No output to L 1: Output to L Timer Selection for Direct Sound B 0: Timer 0 1: Timer 1 Direct Sound FIFO B Clear and Sequencer Reset D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 103 A setting of 00 results in output that is 1/4 of full range. A setting of 01 results in output that is 1/2 of full range. A setting of 10 results in full-range output. A setting of 11 is a prohibited code. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 104: Sound Pwm Control

    Amplitude Sampling Resolution Frequency 9bit 32.768KHz 8bit 65.536KHz 7bit 131.072KHz 6bit 262.144KHz PWM Conversion Image Input Waveform(Waveform PWM Modulation CPU Output Waveform Composition for All Sounds) Time Base Resolution (Sampling Frequency) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 105 AGB Programming Manual Sound SOUNDBIAS[d09-00] Bias Level This is used by system ROM. Please do not change this value, as it may cause errors. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 106: Timer

    Controls whether an interrupt request flag is generated by an overflow. No interrupt is generated with a setting of 0. An overflow does generate an interrupt if the setting is 1. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 107 Allows selection of a prescalar based on the system clock (16.78MHz). Setting Prescalar (Count-Up Interval) System clock (59.595 ns) 64 cycles of system clock ( 3.814 s) 256 cycles of system clock (15.256 s) 1024 cycles of system clock (61.025 s) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 108: Dma Transfer

    When transferring data to OAM or OBJ VRAM by DMA during H-blanking, the H-blank must first be freed from OBJ display hardware processing periods using the DISPCNT register. (See “5 Image System”.) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 109: Dma 0

    32-bit data transfer mode, up to 4000h x 4=10000h bytes can be transferred. Address Register 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Attributes Initial Value DMA0 0B8h 0000h CNT_L D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 110 [Note] Delay of 2 waits will occur before DMA is activated after this flag is set. Accessing DMA related registers during this time may cause a DMA malfunction. Do another process or insert a dummy load command instead. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 111 DMA enable flag is not set to 0. When the DMA repeat function is set to OFF, DMA halts as soon as the amount of data specified by the value in the word-count register has been transferred. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 112 A setting of 10 causes it to be fixed. A setting of 11 causes an increment and after all transfers end, a reload(The setting is returned to what it was when the transfer started) is done. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 113: Dma 1 And 2

    0000h 0D0h DMA2CNT_L The word-count register setting is disabled in direct-sound FIFO transfer mode. With each request received from sound FIFO, 32 bits x 4 words of sound data are transferred. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 114 [Note] Delay of 2 waits will occur before DMA is activated after this flag is set. Accessing DMA related registers during this time may cause a DMA malfunction. Do another process or insert a dummy load command instead. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 115 With a setting of 0, the data are transferred by DMA in 16-bit (half-word) units. With a setting of 1, the data are transferred by DMA in 32-bit (word) units. In direct-sound FIFO transfer mode, the data are transferred in 32-bit units. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 116 However, when in direct sound FIFO transfer mode, the destination address is fixed and unrelated to the setting. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 117: Dma 3

    32-bit data transfer mode, up to 10000h x 4=40000h bytes can be transferred. Address Register Initial 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Attributes Value 0DCh DMA3CNT_L 0000h D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 118 [Note] Delay of 2 waits will occur before DMA is activated after this flag is set. Accessing DMA related registers during this time may cause a DMA malfunction. Do another process or insert a dummy load command instead.. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 119 Sets the bit length of the transfer data. With a setting of 0, the data are transferred by DMA in 16-bit (half-word) units. With a setting of 1, the data are transferred by DMA in 32-bit (word) units. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 120 A setting of 10 causes it to be fixed. A setting of 11 causes an increment to be carried out and then a reload (returned to setting at start of transfer) is done after every transfer is completed. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 121 Although the DMA repeat flag is ON, this DMA will be disabled after the transfer of 1 frame's worth of data. Therefore, it is necessary to re-enable the DMA enable flag for every frame to be transferred. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 122 (Three NOP commands or one LDR command) + the 1st clock of the STR command using the following procedure (Section 3) makes 4 clocks total. (Data is actually written at the 2nd clock of the STR command.) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 123: Dma 4

    (Three NOP commands or one LDR command) + the 1st clock of the STR command by the following procedure (3) equals a total of 4 clocks. (Data is actually written at the 2nd clock of the STR command.) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 124 - Destination address control flag : 10 - Other control bits : No change * Note Please note that the DMA may be started one extra time due to procedure 1 above. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 125: Communication Functions

    Enables high-speed communication by UART system. 4. General Purpose Communication Function Enables communication by any protocol through direct control of the communication terminal. 5. JOY Bus Communication Function Enables communication using Nintendo’s standardized Joy bus. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 126 General Purpose JOY Bus 8-Bit Serial 32-Bit Serial 16-Bit Serial UART (* ... any) Do not change or reset a communication mode during communication, as this may cause a communication malfunction. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 127 -When a peripheral device that is not supported is connected -When different software is connected to other device -When the communication mode is different from the other device -When the AGB Game Link cable is connected incorrectly D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 128: 8-Bit/32-Bit Normal Serial Communication

    SIO Timing Chart The above figure illustrates 8 bit communication. In 32 bit communication, the shift clock sends and receives 32 bits of data. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 129 Data 0 120h 0000h 32_L 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Address Register Initial Attributes Value SIODATA Data 1 122h 0000h 32_H D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 130 If 0, 8-bit transfer is carried out. If 1, 32-bit transfer is carried out. SIOCNT [d07] Start Bit With a setting of 1, a serial transfer starts. The bit is automatically reset after transfer completion. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 131 Using a Game Link cable for DMG/MGB is prohibited in normal serial communication mode. It is possible to communicate at 256KHz and 2MHz with peripheral equipment that does not use a cable. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 132 AGB Game Link cable. Communication cannot be done properly at 2MHz. Also, please note it will be a one-way communication due to cable connection of multi- play communication D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 133 Set start flag for Register SIOCNT and wait for SIOCNT external clock input Start Flag for Register SIOCNT is reset. If the Interrrupt Request Enable Transmit(Receive/Send) Transmit(Receive/Send) Flag is set, an interrupt request is generated D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 134: 16-Bit Multi-Player Communication

    Register SIOMLT_SEND is output, and lastly a “Stop bit” (HI level) is output. After this, the SD terminal goes to pull-up input and LO is output from the SO terminal. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 135 Once the transmission ends, the received data is stored in each of the data registers (SIOMULTI0, SIOMULTI1, SIOMULTI2, and SIOMULTI3). If there is a terminal that is not connected the initial data FFFFh is stored. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 136 Interrupt Request (Sent to GND with Communication Cable) Primary Slave Interrupt Request View of Terminal Status Input Output Input Multi Player AGB Game Link cable Connecting Diagram Small Large Connector Connector D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 137 0000h MULTI2 Initial Address Register Attributes 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Value Data 3 126h 0000h MULTI3 Data Transition Diagram D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 138 Due to individual differences in AGB hardware, there is an error in timing of interrupt occurrence. Always use a timer when sending, and be sure to have enough intervals of communicable minimum send interval + 600 clock (interrupt occurrence error guarantee value). D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 139 LO input to the SI terminal is the master. HI input means that it is a slave. Prior to communication starting, it is not possible to determine the number order of a particular slave. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 140 AGB Programming Manual Communication Functions SIOCNT [d01 - d00] Baud Rate Sets the communication baud rate. Setting Baud Rate 9600 bps 38400 bps 57600 bps 115200 bps D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 141 The multi-play ID# is stored in (d05,d04) of Register SIOCNT Transmit End(Send/Receive) Transmit End(Send/Receive) If the Interrupt Request Enable Flag is set for Register SIOCNT, an interrupt request is generated D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 142: Uart Communication Functions

    If written to a data register SIODATA8, data is written to a send shift register, and if read, data is read from a receive shift register. (Only the lower 8 bits are valid.) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 143 FIFO becomes empty. Also, when read, data is read from a receive FIFO. (Only the lower 8 bits are valid.) Example: Writing Data Registers D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 144 1: Enable Parity Enable Flag 0: Disable 1: Enable Send Enable Flag 0: Disable 1: Enable Receive Enable Flag 0: Disable 1: Enable Interrupt Request Enable Flag 0: Disable 1: Enable D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 145 When using FIFO, first you need to go into UART mode in a status of 0 [FIFO Disable]. By disabling FIFO in UART mode the FIFO sequencer is initialized. SIOCNT [d07] Data Length Select data length as 8 bits or 7 bits. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 146 When set to 0, a send is always possible independent of the SC Terminal. When set to 1, a send is only possible when a LO is being input to the SC Terminal. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 147 AGB Programming Manual Communication Functions SIOCNT [d01 - d00] Baud Rate Sets communication baud rate. Setting Baud Rate 9600 bps 38400 bps 57600 bps 115200 bps D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 148: General Purpose Communication

    [Caution] Always set the SI terminal to an input. If it is set to an output, a problem may occur with some connecting equipment. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 149 When the corresponding terminal is set for input, the status(HI/LO) of the terminal can be confirmed. If the corresponding terminal is set for output, the status of the set bit is output. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 150: Joy Bus Communication

    When this is set, if you write a 1, a reset can be done. JOYCNT [d01] Receive Complete Flag Set upon completion of receive operation. When this is set, if you write a 1, a reset can be done. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 151 JOYSTAT 0000h Receive Status Flag Send Status Flag General Purpose Flag JOYSTAT [d05,d04] General Purpose Flag This flag is not assigned. The user can set the use of this flag arbitrarily. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 152 [Type/Status Data Request] Command(00h) Received Returns 2 byte type number(0004h) and 1 byte communication status. Direction Order Remarks Receive Command 0(00h) Type Number 0400h Send Lower 8 bits of Register JOYSTAT Communication Status D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 153 Upper 8 bits of send data Register JOY_TRANS_L Send Data Send Lower 8 bits of send data Register JOY_TRANS_H Upper 8 bits of send data Register JOY_TRANS_H Lower 8 bits of Register JOYSTAT Communication Status D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 154: Agb Game Link Cable

    AGB Programming Manual Communication Functions 13.6 AGB Game Link Cable When communicating between AGB units, the AGB Game Link cable to be used will vary depending upon the type of Game Pak used. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 155: Key Input

    0000h LFT RT Interrupt Specification Flag 0: Not Specified Interrupt Request Enable Flag 1: Specified 0: Disable 1: Enable Interrupt Condition Specification Flag 0: Logical Addition (OR) 1: Logical Multiplication (AND) D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 156: Interrupt Conditions

    Logical Multiplication (AND) Operation The conditions for interrupt request generation occur when there is simultaneous input for all of the keys specified as interrupt keys. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 157: Interrupt Control

    V Counter Match Timer Serial Communication/General Purpose Communication/JOY Bus Communication/ UART Communication Game Pak(DREQ/IREQ) By resetting the bit, the corresponding interrupt can be prohibited. Setting this to 1 enables the corresponding interrupt. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 158 When the timing of clearing of IME and the timing of an interrupt agree, multiple interrupts will not occur during that interrupt. Therefore, set (enable) IME after saving IME during the interrupt routine. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 159: System-Allocated Area In Work Ram

    User Stack * Specify where to return for SoftReset( ) System Call 0h:08000000h If not 0h:02000000h By changing each CPU Mode SP Initial-value, they can be set to an arbitrary memory map. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 160: Interrupt Operation

    CPU mode to the user mode in user interrupt processing. For the latter method, see the explanation of multiple interrupts that is discussed on the following page. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 161: Multiple Interrupts

    LSR_usr as well. USR Stack IRQ Stack SVC Stack 03007F00 03007FA0 03007FE0 L R _ u s r SP_svc 6 W O R D S User Interrupt Processing SPSR_irq SP_usr SP_irq 03007FA0 03007F00 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 162 03007FE0 L R _ u s r SP_svc 6 W O R D S User Interrupt Processing SPSR_irq SP_usr 6 W O R D S SP_irq 03007FA0 03007F00 àContinue processing (2). D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 163: Power-Down Functions

    Stopped System Clock Stopped Infrared Communication Stopped *Note The LCD controller stops so turn OFF the LCD display before entering Stop Mode. Sound stops in Stop Mode, therefore noise may result. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 164: Halt Function

    Block Working Status AGB-CPU Wait status resulting from wait signal LCD Controller Normal operation Sound Normal operation Timer Normal operation Serial Communication Normal operation Normal operation System Clock Normal operation D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 165: Agb System Calls

    S y s t e m C a l l SP_usr 03007F00 03007FA0 5) Complete processing using each system call. USR Stack IRQ Stack SVC Stack 03007F00 03007FA0 03007FE0 SP_usr SP_irq 4 W O R D S SP_svc 03007F00 03007FA0 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 166 6) Return value to registers R0, R1, and R3, in cases where a system call provides a return value, and then return to the user program. USR Stack IRQ Stack SVC Stack 03007F00 03007FA0 03007FE0 SP_usr SP_irq SP_svc 03007F00 03007FA0 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 167: Multiple Calls

    4 WORDS Save with each SP_irq SP_svc System Call User Interrupt Processing 03007F00 03007FA0 SP_usr àIf System Call occurs during User interrupt processing, the System Call is called using Multiple Calls. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 168 USR Stack IRQ Stack SVC Stack 03007F00 03007FA0 03007FE0 LR_usr 6 WORDS 4 WORDS Save with each SP_irq SP_svc System Call User Interrupt Processing 03007F00 03007FA0 SP_usr D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.
  • Page 169 14) Return value to registers R0, R1, and R3, in cases where a system call provides a return value, and then return to the user program. USR Stack IRQ Stack SVC Stack 03007F00 03007FA0 03007FE0 SP_usr SP_irq SP_svc 03007F00 03007FA0 D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

  • Page 170: Rom Registration Data

    Store the Game title in this area. Game Code Store the Game Code provided by Nintendo in this area. Maker Code The Maker Code, determined by the "maker" of the software and Nintendo, is stored here. Store the fixed code "96h". Main Unit Code Store the code for the hardware on which the software is intended to run.
  • Page 171 The 2’s complement of the total of the data stored in address 80000A0h ~ 80000BCh plus 19h is stored in this location. Reserved Area This is a system allocated area. Set this area to 00h. D.C.N. AGB-06-0001-002B4 ©1999 - 2001 Nintendo of America Inc.

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