Sharp FO IS125N - B/W Laser - All-in-One Service Manual page 94

FO-IS125N
CX95410-12Z (IC100) Terminal Description
Pin Pad Side Pin Signal Name
No. No.
1 1 L
PWRDWNn
2 2 L
BATRSTn
3 3 L
PLL_VSS
4 4 L
PLL_VDD
5 5 L
XIN/EXTCLK
6 6 L
XOUT
7 7 L
JTAG_CPU_TCK
8 8 L
JTAG_CPU_TDI
9 9 L
JTAG_CPU_TDO
10 10 L
JTAG_CPU_TMS
11 11 L
RESETn
12 12 L
TEST_MODE/RCOSC test_mode/rcosc
13 13 L
GPIO[0]
14 14 L
GPIO[1]
15 15 L
GPIO[2]
16 16 L
VDD
17 17 L
VSS
18 19 L
VDDO
19 20 L
GPIO[3]
20 21 L
GPIO[4]
21 22 L
GPIO[5]
22 23 L
GPIO[6]
23 24 L
GPIO[7]
24 25 L
VDD
25 26 L
VSS
26 27 L
GPIO[8]
27 28 L
GPIO[9]
28 29 L
GPIO[10]
29 30 L
GPIO[11]
30 31 L
GPIO[12]
31 32 L
VDD
32 33 L
VSS
33 35 L
VDDO
34 36 L
GPIO[13]
35 37 L
GPIO[14]
36 38 L
GPIO[15]
37 39 L
GPIO[16]
38 40 L
GPIO[17]
39 41 L
ADC_VSS
40 43 L
MADC_IN[0]
41 44 L
MADC_IN[1]
42 45 L
MADC_IN[2]
43 46 L
MADC_IN[3]
44 47 L
ADC_VDDO
45 49 B
ADC_VREF
46 50 B
ADC_RBIAS
47 51 B
ADC_IN
48 52 B
VREG_CTRL
49 53 B
VREG_ENABLE
50 54 B
GPIO[18]
51 55 B
GPIO[19]
52 56 B
GPIO[20]
53 57 B
GPIO[21]
54 58 B
GPIO[22]
Pad Signal Pad Pad Cell
Type
Name
I pcb00rtc
pwrdwnn
I pcb00rtc
bat_rstn
GND pvsnnn
pllvss
PWR pvdnnn
pllvdd
I plx43
xin
O plx43
xout
I plbgp
jtag_tck
I plbgp
jtag_tdi
O plbgp
jtag_tdo
I plbgp
jtag_tms
B plbgp
resetn
I pldosc24 I
B plbgp
gpio[0]
B plbgp
gpio[1]
B plbgp
gpio[2]
PWR pvdcnn
vdd
GND pvscnn
vss
PWR pvdnpo
vddo
B plbgp
gpio[3]
B plbgp
gpio[4]
B plbgp
gpio[5]
B plbgp
gpio[6]
B plbgp
gpio[7]
PWR pvdcnn
vdd
GND pvscnn
vss
B plbgp
gpio[8]
B plbgp
gpio[9]
B plbgp
gpio[10]
B plbgp
gpio[11]
B plbgp
gpio[12]
PWR pvdcnn
vdd
GND pvscnn
vss
PWR pvdnpo
vddo
B plbgp
gpio[13]
B plbgp
gpio[14]
B plbgp
gpio[15]
B plbgp
gpio[16]
B plbgp
gpio[17]
GND pvsnnn
dvss
I pcb00w
afe_madcin0
I pcb00w
afe_madcin1
I pcb00w
afe_madcin2
I pcb00w
afe_madcin3
PWR pvdnnn
avddh
pvdnnn
afe_vref
pvdnnn
afe_rbias
I pdb00w
afe_sadcin
O pcb00w
vctrl12
I pcd10u2
vreg_en
B plbgp
gpio[18]
B plbgp
gpio[19]
B plbgp
gpio[20]
B plbgp
gpio[21]
B plbgp
gpio[22]
5 – 3
Def. Drv. Str. Hys PU / PD
I/O (def.)
I H
I H
I
O
I PU
I PU
O
5
I PU
I H PU
5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM PGM
PGM, 3.5
I PGM PGM
PGM, 3.5
I PGM PGM
PGM, 3.5
I PGM PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I
I
I
I
B
B
I
O
I
I PGM PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
I PGM
PGM, 3.5
Description
Battery Power Down Indication
Battery Reset
PLL Ground
1.25V PLL Power
Crystal/Oscillator Input (10-
60 MHz)
Crystal Output
ARC JTAG clock
ARC JTAG data in.
ARC JTAG data out
ARC JTAG test mode
Reset (active low)
Test Mode/Low Power
Oscillator for HSSD (24 MHz)
General Purpose I/O
General Purpose I/O
General Purpose I/O
1.25V Core Power
Core Ground
3.3V Power
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
1.25V Core Power
Core Ground
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
1.25V Core Power
Core Ground
3.3V Power
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
ADC Digital Core Ground
Monitor ADC Input 0
Monitor ADC Input 1
Monitor ADC Input 2
Monitor ADC Input 3
3.3V Analog Power
Voltage Reference
Reference Bias
Scanner ADC Input
Voltage Regulator control
Voltage Regulator Enable
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O
General Purpose I/O