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FO-2970MU
SH7041 (IC5) Terminal descriptions
Classification
Code
Terminal No.
Data bus
D0 ~ D15
(QFP-112)
D0 ~ D31
(QFP-144)
Bus control
CS0~CS3
RD
WRH
WRL
WAIT
RAS
CASH
CASL
RDWR
AH
WRHH
(QFP-144)
WRHL
(QFP-144)
CASHH
(QFP-144)
CASHL
(QFP-144)
Multi function
TCLKA
timer pulse unit TCLKB
TCLKC
TCLKD
TIOC0A
TIOC0B
TIOC0C
TIOC0D
TIOC1A
TIOC1B
TIOC2A
TIOC1B
TIOC3A
TIOC3B
TIOC3C
TIOC3D
TIOC4A
2,5,143,144
TIOC4B
TIOC4C
TIOC4D
Direct memory
DREQ0,
60,62,109,
access control
DREQ1
111,132,136
(DMAC)
DRAK0,
2,30,33,110,
DRAK1
DACK0,
DACK1
I/O
45,46
O
Data bus
56~60,
62,64~70
72~76,78
80~84
86,88~92
49,50,53
O
Chip select 0 to 3
54,56,57
43
O
Read-out
47
O
Higher side writing
48
O
Lower side writing
39,101
I
Wait
31
O
Low address strobe
34
O
Higher column address Timing signal for column address strobe of DRAM.
strobe
32
O
Lower column address Timing signal for column address strobe of DRAM.
strobe
36
O
DRAM read/write
2,100
O
Address hold
1
O
HH writing
3
O
HL writing
4
O
HH column address
strobe
29
O
HL column address
strobe
51~54
I
MTU timer clock input External clock input terminal for MTU counter.
109~111,
I/O
MTU input capture/
113
output conveyer
(Channel 0)
114,115
I/O
MTU input capture/
output conveyer
(Channel 1)
116,117
I/O
MTU input capture/
output conveyer
(Channel 2)
138~140,
I/O
MTU input capture/
output conveyer
(Channel 3)
I/O
MTU input capture/
output conveyer
(Channel 4)
I
DMA transfer demand Input terminal for external DMA transfer demand.
(Channels 0 and 1)
O
DREQ demand
113
acceptance (Channels input.
0 and 1)
5,58,59
O
DMA transfer strobe
(Channels 0 and 1)
Name
Bilateral data bus for 16 bit (Pin plate QFP-112 ) or 32 bit (Pin plate
QFP-144).
Chip select signals for external memory or device.
Shows reading-out from the external device.
Shows writing in higher 8 bits (bits 15 to 8).
Shows writing in lower 8 bits (bits 7 to 0).
To insert wait cycle into the bus cycle when accessing external space.
Timing signal for low address strobe of DRAM.
It is output when accessing higher eight bits of data.
Strobe signal for DRAM writing.
Address hold timing signal for the device using multiplex bus of
address/data.
Shows writing of bits 31 to 24 of external data.
Shows writing of bits 23 to 16 of external data.
Timing signal for column address strobe of DRAM.
It is output when accessing bits 31 to 24 of data.
Timing signal for column address strobe of DRAM.
It is output when accessing bits 23 to 16 of data.
Channel 0 terminal for inputting Input Capture/outputting Output
Conveyer/outputting PWM.
Channel 1 terminal for inputting Input Capture/outputting Output
Conveyer/outputting PWM.
Channel 2 terminal for inputting Input Capture/outputting Output
Conveyer/outputting PWM.
Channel 3 terminal for inputting Input Capture/outputting Output
Conveyer/outputting PWM.
Channel 4 terminal for inputting Input Capture/outputting Output
Conveyer/outputting PWM.
Outputs sampling acceptance of external DMA transfer demand
Outputs strobe to external I/O of external DMA transfer demand.
5 – 4
Function
(Continuing)
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