Circuit Description Of Control Pwb - Sharp FO-2970M Service Manual

FO-2970MU

[2] Circuit description of control PWB

1. General description
Fig. 2 shows the functional blocks of the control PWB, which is com-
posed of 5 blocks.
MAIN
MODEM/
CONTROL
CONTROL
BLOCK
BLOCK
IMAGE
SIGNAL
PROCESS
BLOCK
Fig. 2 Control PWB functional block diagram
2. Description of each block
(1) Main control block
The main control block is composed of HITACHI CPU (SH2),
ROMX1 (8M bit), SRAMX1 (1M bit), DRAMX3 (16M bit).
Devices are connected to the bus to control the whole unit.
1) SH7041 (IC5) : pin-144 QFP
The CPU Integrated Facsimile Controllers.
SH7041, contains an internal 32 bit microprocessor with an external 16
bit address space and dedicated circuitry optimized for facsimile image
processing and facsimile machine control and monitoring.
RES/VPP
MDTOVF
MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
PLLVCC
PLLCAP
PLLVSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVCC
AVSS
AVREF
ASIC/PRINTING
CONTROL
BLOCK








 

 






PROM/MASKROM







128KB/64KB







P
L
L
 






CPU






     
INTERRUPT USER
CONTROLLER BREAK






 

SERIAL COMMUNICATION
INTERFACE
    
(X2CHANNELS)
COMPARE MATCH TIMER
CONVERTER
(X2CHANNELS)

2) M27C800-90F1 (IC14): pin-42 DIP (ROM)
EPROM of 8M bit equipped with software for the main CPU.
3) W24010S-70LET (IC1): pin-32 SOP (RAM)
Line memory for the main CPU system RAM area and coding/decoding
process. Used as the transmission buffer.
Memory of recorded data such as daily report and auto dials. When the
power is turned off, this memory is backed up by the lithium battery.
4) MSM5118165D (IC11, IC13, IC22): pin-42 SOJ (DRAM)
Image memory for recording process.
•
Memory for recording pixel data at without paper.

  
RAM/CACHE
4KB/1KB

  
DATA TRANSFER
CONTROLLER
DIRECT MEMORY
 
ACCESS CONTROLLER
BUS STATE
CONTROLLER

 
MULTI FUNCTION
TIMER PULSE UNIT

    
WATCHDOG
TIMER

 
Fig. 3
5 – 2
PC15/A15
PC14/A14
PC13/A13
PC12/A12
PC11/A11
PC10/A10
PC9/A9
PC8/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
PD31/D31/ADTRG
PD30/D30/IRQOUT
PD29/D29/CS3
PD28/D28/CS2
PD27/D27/DAK1
PD26/D26/DACK0
PD25/D25/DREQ1
PD24/D24/DREQ0
PD23/D23/IRQ7
PD22/D22/IRQ6
PD21/D21/IRQ5
PD20/D20/IRQ4
PD19/D19/IRQ3
PD18/D18/IRQ2
PD17/D17/IRQ1
PD16/D16/IRQ0
PD15/D15
PD14/D14
PD13/D13
PD12/D12
PD11/D11
PD10/D10
PD9/D9
PD8/D8
PD7/D7
PD6/D6
PD5/D5
PD4/D4
PD3/D3
PD2/D2
PD1/D1
PD0/D0
: PERIPHERAL ADDRESS BUS(32BIT)
: PERIPHERAL DATA BUS(16BIT)
: INTERNAL ADDRESS BUS(32BIT)
: INTERNAL HIGH-ORDER DATA(16BIT)
: INTERNAL LOW-ORDER DATA(16BIT)