Toshiba M500 ST5405 - Satellite - Core 2 Duo 2.13 GHz Maintenance Manual page 69

2.4 System Board Troubleshooting
Table 2-4 Debug port (Boot mode) error status (5/10)
D port status
F106H
IRT_INI_SMBASE_END
Initialization of devices which
need initialization before PCI bus
initialization
F107H
IRT_CHK_INI_SYS1_END
Saving memory configuration to
buffer
Reading of EC version
Update of flash ROM type
Judging of destination (Japan or
other than Japan) based on DMI
data
CMOS default setting check
ACPI table initialization
(for execution of option ROM)
PORTÉGÉ M500 Maintenance Manual (960-559)
Inspection items
2 Troubleshooting Procedures
Details
PIT test (Cold boot only) and initialization
Setting of test pattern to channel 0 of PIT#0
Check whether the set test pattern can be read
Initialization of PIT channel 0
(Setting of timer interruption interval to 55ms)
Initialization of PIT channel 2
(Setting of the sound generator frequency to 664Hz)
Test of PIT channel 1
(Check whether the refresh signal works normally in
30 micro-s refresh interval) HLT, when the time is out
Test of PIT channel 2
(Check whether the speaker gate works normally)
CPU clock measurement
Check of parameter block A
Permission of SMI except auto-off function
Control of excess of rated input power
Battery discharging current control (1CmA)
AC adapter rated over current control
Dividing procedures for time measuring by IRT
Setting for clock generator
CPU Initialization
Judgment of CPU type
Check of supporting Geyserville
Make CPU clock High
Setting of Graphics Aperture Size
Sets default setting if bad battery or bad checksum
(ROM, CMOS) is detected
[CONFIDENTIAL] 2-27