Pausing An Ultra Dma Data Out Burst - Fujitsu MHT2080AH - 80GB 5400 RPM PATA Hard Drive Product Manual

2) The host shall generate an HSTROBE edge to latch the new word no sooner
than t
HSTROBE edge no more frequently than t
Mode. The host shall not generate two rising or falling HSTROBE edges
more frequently than 2 t
3) The host shall not change the state of DD (15:0) until at least t
generating an HSTROBE edge to latch the data.
4) The host shall repeat steps (1), (2) and (3) until the data transfer is complete
or an Ultra DMA burst is paused, whichever occurs first.

5.5.4.3 Pausing an Ultra DMA data out burst

The following steps shall occur in the order they are listed unless otherwise
specifically allowed (see 5.6.3.9 and 5.6.3.2 for specific timing requirements).
a) Host pausing an Ultra DMA data out burst
1) The host shall not pause an Ultra DMA burst until at least one data word
2) The host shall pause an Ultra DMA burst by not generating an
3) The host shall resume an Ultra DMA burst by generating an HSTROBE
b) Device pausing an Ultra DMA data out burst
1) The device shall not pause an Ultra DMA burst until at least one data
2) The device shall pause an Ultra DMA burst by negating DDMARDY-.
3) The host shall stop generating HSTROBE edges within t
4) If the device negates DDMARDY- within t
5) The device shall resume an Ultra DMA burst by asserting DDMARDY-.
C141-E195-02EN
after changing the state of DD (15:0). The host shall generate an
DVS
for the selected Ultra DMA mode.
CYC
of an Ultra DMA burst has been transferred.
HSTROBE edge.
Note: The device shall not immediately negate DMARQ to initiate Ultra
DMA burst termination when the host stops generating
HSTROBE edges. If the host does not assert STOP, in order to
initiate Ultra DMA burst termination, the device shall negate
DDMARDY- and wait t
edge.
word of an Ultra DMA burst has been transferred.
negating DDMARDY-.
an HSTROBE edge, then the device shall be prepared to receive zero or
one additional data words. If the device negates DDMARDY- greater
than t after the host has generated an HSTROBE edge, then the device
SR
shall be prepared to receive zero, one or two additional data words. The
additional data words are a result of cable round trip delay and t
timing for the host.
5.5 Ultra DMA Feature Set
for the selected Ultra DMA
CYC
before negating DMARQ.
RP
after the host has generated
SR
after
DVH
of the device
RFS
RFS
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