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Codes Used In Summary Table - Intel 845 - DESIGN GUIDE Design Manual

Processor in 478-pin package 845 chipset platform for sdr

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Preface

Codes Used in Summary Table

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Document change or update that will be implemented.
Shaded: This item is either new or modified from the previous version of the document.
NO.
Plans
NO.
Plans
1
NO.
Plans
1
2
3
4
5
6
7
8
6
There are no General Design Consideration changes in this Design Guide Update revision.
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Schematic change to the 82845 MCH HSWING Circuit
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Change Section 12.4.2, 3.3V/V5REF Sequencing
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Change Section 14.8, Power and Ground, V5REF_SUS
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Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory
Power Delivery Map
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Add Section 4.6.7, Electrostatic Discharge Platform Recommendations
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Change Table 3, System Bus Routing Summary for the Processor
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Add Section 13.2, Intel® Boxed Processor Mechanical Keep-Outs
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Add Section 15.1.3, Intel® Boxed Processor Mechanical Keep-Outs
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Revise Section 14.1, Schematic Checklist, Host Interface, PWRGOOD
GENERAL DESIGN CONSIDERATIONS
SCHEMATIC, LAYOUT, AND ROUTING UPDATES
DOCUMENTATION CHANGES
R
Design Guide Update

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