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Lauterbach RH850 Manual

Debugger and trace
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RH850 Debugger and Trace
Release 02.2025
MANUAL

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  • Page 1 RH850 Debugger and Trace Release 02.2025 MANUAL...
  • Page 2  TRACE32 Documents ........................ ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... RH850 ............................RH850 Debugger and Trace ....................History ..........................Introduction ........................Available Tools Debugger Software-only Debugger for XCP SFT Trace On-chip Trace High-Speed Serial Off-chip Trace (Aurora NEXUS)
  • Page 3 Connect to Running Program (Hot Plug-In) Troubleshooting ........................ SYStem.Up Errors FAQ ............................. Debugging .......................... RH850 Debug Interface Modes JTAG Mode LPD4 Mode LPD1 Mode UART Mode Breakpoints Software Breakpoints Onchip Breakpoints Breakpoint in ROM Example for Breakpoints Access Classes Access Classes to Memory and Memory Mapped Resources...
  • Page 4 SYStem.Option.OCDID OnChipDebugID setting SYStem.Option.CFID CodeFlashID setting SYStem.Option.DFID DataFlashID setting SYStem.Option.OPtionByTe Option-byte setting SYStem.Option.OPtionByTe8 Option-byte setting SYStem.Option.CIDA Customer-ID A setting SYStem.Option.CIDB Customer-ID B setting SYStem.Option.CIDC Customer-ID C setting SYStem.Option.PERSTOP Disable CPU peripherals if stopped RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 5 NEXUS.SYNC Address-sync trace messaging enable NEXUS.SyncPeriod Set period of timestamp sync messages NEXUS.state Display NEXUS port configuration window NEXUS.TimeStamps On-chip timestamp generation enable Nexus specific TrOnchip Commands ................TrOnchip.Alpha Set special breakpoint function RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 6 Debug Connector ......................Debug Connector 14 pin 100mil Debug Connector 26 Trace Connectors and Adapters ..................Adapter for RH850 (LA-3561) Parallel NEXUS Connector (Debug and Trace) Aurora NEXUS SAMTEC 34-pin (Debug and Trace) Aurora NEXUS SAMTEC 40-pin (Trace only) Aurora NEXUS SAMTEC 46-pin (Debug and Trace)
  • Page 7 RH850 Debugger and Trace Version 13-Feb-2025 History 17-Jan-2025 New command SYStem.Option.CONFIGCLR. 03-Mar-2024 New commands: SYStem.Option.CIDA, SYStem.Option.CIDB, and SYStem.Option.CIDC. 03-May-2023 New command SYStem.Option.DUALPORT. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 8 CPU or for specific family lines, the name(s) of the family/families is/are added in brackets. Available Tools This chapter gives an overview over available Lauterbach tools for the RH850 processors. Debugger Debugging RH850 requires a Lauterbach Debug Cable together with a Lauterbach PowerDebug Module.
  • Page 9 SFT Trace SFT trace (software trace) requires no extra Lauterbach hardware. Trace data can be saved to the On-chip trace or it can be streamed to the debug box in real time (LPD4 mode only). In streaming mode up to 32MRec of trace data can be recorded.
  • Page 10 Co-Processor Debugging (GTM) Debugging the RH850 coprocessors GTM is included free of charge, i.e. there is no additional license required. For details about coprocessor debugging, see the specific Processor Architecture Manuals: • “GTM Debugger and Trace” (debugger_gtm.pdf) Multicore Debugging Lauterbach offers multicore debugging and tracing solutions, which can be done in two different setups: Symmetric Multiprocessing (SMP) and Asymmetric Multiprocessing (AMP).
  • Page 11 You can now search the demo folder and its subdirectories for PRACTICE start-up scripts (*.cmm) and other demo software. You can also manually navigate in the ~~/demo/rh850/ subfolder of the system directory of TRACE32. Brief Overview of Documents for New Users Architecture-independent information: •...
  • Page 12 Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 13 Useful Tips Application Starts Running at SYStem.Up Before TRACE32 can get control of the RH850, the cpu already has started the application startup code. This is a restriction of the RH850 core! It depends on the executed startup code which peripherals are initialized and if this can cause trouble for the debugging session.
  • Page 14 Reset Line Ensure that the debugger signal RESET is connected directly to the RESET of the processor. This will provide the ability for the debugger to drive and sense the status of RESET. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 15 This becomes important if the debugger should attach to an already running application which has entered the STOP- or DeepSTOP mode. TRACE32 displays the message “running (stopmode)” in the state line if the RH850 device enters the STOP- or DeepSTOP-mode. The message will switch to “running (stop occurred)” as soon as there is a wake-up event.
  • Page 16 This figure shows an example of how to connect the TRACE32 hardware to your PC and your target board. PC or Workstation Target Debug Cable POWER DEBUG USB INTERFACE / USB 3 Cable POWER DEBUG INTERFACE / USB 3 RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 17 Select the CPU type to load the CPU specific settings. SYStem.CPU R7F701035 If the TRACE32-ICD hardware is installed properly, the following CPU is the default setting: JTAG Debugger for RH850 R7F701035 Tell the debugger where’s FLASH/ROM on the target. MAP.BOnchip 0x00000000++0x7FFFF This command is necessary for the use of on-chip breakpoints.
  • Page 18 Break.Set 0xFEDF8000 /Program ; Set software breakpoint to address ; 0xFEDF8000 (address 0xFEDF8000 is in ; RAM) *) These commands open windows on the screen. The window position can be specified with the WinPOS command. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 19 Var.View %E my_var your_var Data.Dump E:0x40000100 Set breakpoints or halt core. Break.Set my_func /Onchip Break Display ASM/HLL core at current instruction pointer List For information about SMP and AMP debugging, see “Multicore Debugging”, page 30. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 20 There are additional loads or capacities on the debug lines. DEBUGPORTTYPE selection does not match the Debug-Interface-Mode setting of the OptionBytes. Wrong OSCCLOCK, CORECLOCK or BAUDRATE setting (LPD4, U, CSI mode) JTAG clock (JTAG mode) too high. Please refer to https://support.lauterbach.com/kb. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 21 Debugging RH850 Debug Interface Modes The RH850 offers three Debug Interface Modes (JTAG, LPD1, LPD4) plus the SerialFlashProgramming mode by use of the same debug connection. • The DebugInterface modes are selected by the setting of the CPU OptionBytes. •...
  • Page 22 • TRACE32 command: SYStem.CONFIG DEBUGPORTTYPE LPD1 • Interface baud rate is detected/configured automatically • There are RH850 CPU versions which do not support LPD1 mode! UART Mode • For serial flash programming and OptionByte programming (no debugging!) • All CPU internal flashes can be programmed TRACE32 is configured with the commands: •...
  • Page 23 SerialFlash-Programming mode is only needed if the Option-Bytes or UserBootFlash has to be modified. All other debugging stuff and flash programming can be done in JTAG, LPD1 or LPD4 mode. RH850/F1x WS1.0 and RH850/E1x FCC (R7F701Z00) do not support Flash- READ in SerialFlash-Programming mode! RH850 Debugger and Trace 1989-2025 ©...
  • Page 24 RAM or FLASH areas.There is no restriction in the number of software breakpoints. Onchip Breakpoints Each core of a RH850 device is equipped with 12 Onchip breakpoints. These breakpoints only can be set if the RH850 has stopped program execution.
  • Page 25 The following breakpoint combinations are possible. Software breakpoints: Break.Set 0x100000 /Program ; Software breakpoint 1 Break.Set 0x101000 /Program ; Software breakpoint 2 On-chip breakpoints: Break.Set 0x100 /Program ; On-chip breakpoint 1 Break.Set 0x0ff00 /Program ; On-chip breakpoint 2 RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 26 Description Use real-time memory access. This attribute has no effect if SYStem.MemAccess is set to Denied). Examples of usage: Command: Effect: Data.dump ED:0xFEEE0000 Opens dump window at address 0xFEEE0000 using real-time memory access RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 27 Access Class Description System Register (SR) access The RH850 supports 256 System Registers which are divided into 8 groups (selID) with 32 registers (regID) each. Example: The ISPR register has a regID==10 and selID==2 Using the SR: access class the System Register address is defined by: •...
  • Page 28 Each RH850 core (also called ProcessorElemet PEx) has it’s own set of debug registers. Each set can have up to 8 banks with 256 registers each. • Address bits(7..0) = IR register number • Address bit(11..8) = Bank number •...
  • Page 29 Go, Step, Step.Over command. Runtime measurement is done with a resolution of about 5 µs. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 30 SMP debugging is only possible for cores of the same architecture. TRACE32 also supports mixed AMP/SMP operation. E.g. RH850/P1x-C devices can be controlled with two PowerView instances, one for PE5_core (ICU-M) and one controlling PE1_core and PE2_core in SMP mode.
  • Page 31 Register /CORE 0 Register /CORE 1 List /CORE 0 List /CORE 1 Example scripts for SMP debugging can be found in the demo folder. • ~~/demo/rh850/hardware/ Further demo scripts available for download and upon request. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 32 SYStem.Up SYStem.Mode.Attach Core_0 is halted at the reset address and core_1 remains in reset, In order to halt core_1 as soon as it is released from reset, issue the Break command. Break RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 33 Start core_0. Core_1 will halt at its reset address after being released by core_0. WAIT !RUN() ; wait until cpu stops Example scripts for AMP debugging can be found in the demo folder. • ~~/demo/rh850/hardware/ RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 34 FLASH Programming Support Before Flash programming can work TRACE32 has to be informed about the CPU's flash memory mapping. This is done with the demo scripts in the ~~/demo/rh850/flash directory or by use of the TRACE32 AutoSetup. AutoSetup offers a convenient way to connect to RH850 single-core devices and to configure TRACE32 for flash programming.
  • Page 35 The big advantage of this method is that only modified flash-segments are erased/programmed. Programming is quicker and programming-stress for the FLASH is reduced. NOTE: SerialFlashProgramming of “RH850-F1x WS1.0” and “RH850/E1x FCC (R7F701Z00)” This devices do not support memory-read in UART mode. As result an UART-Error message is displayed in AREA window.
  • Page 36 No extra trace hardware or license is needed. NEXUS On-chip Trace Many processors of the RH850 family implement a feature to store the NEXUS messages of cores and peripheral trace clients into an on-chip trace memory. Using the on-chip trace with just a debug cable (LA-3719) requires the on-chip trace license LA-3734X.
  • Page 37 PowerTrace Serial. Trace tools for the parallel NEXUS AUX interface: • Preprocessor Focus II RH850 (LA-3918) in conjunction with PowerTrace II / PowerTrace III • Preprocessor RH850 (LA-3843) in conjunction with PowerTrace II / PowerTrace III The TRACE32 online help provides a “AutoFocus User’s Guide”...
  • Page 38 Note for OnchipTrace (optional bugfix): There are RH850 devices with a bug in the NEXUS coding for Onchip-Trace. In case of flow-errors in the trace listing please set NEXUS.SYNC ON and try again. Tracing of Data (read/write) Transactions General data tracing is enabled using the command NEXUS.DTM. This command enables the data trace for the full address space.
  • Page 39 Trace Filtering and Triggering with Debug Events Event Breakpoints Each core of a RH850 chip is equipped with 16 Event breakpoints. TRACE32 uses them for: • Trace-recording control: TraceOn, TraceOff, TraceEnable, TraceData, WatchPoints • Trigger control: TraceTrigger, BusTrigger, BusCount The following list gives an overview of the usage of the Event breakpoints by TRACE32:...
  • Page 40 ;at address 0x00008230 is executed. Break.Set 0x00008230 /Program /TraceEnable TraceEnable can also be applied on data trace: ;Only generate a trace message when the core writes to variable flags[3]. Var.Break.Set flags[3] /Write /TraceEnable RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 41 /Program /TraceOFF ;Enable program/data trace when variable flags[3] is written Var.Break.Set flags[3] /Write /TraceON ;Disable program/data trace data when 16-bit value 0x1122 is ;written to address 0x40000230 Break.Set 0x40000230 /Write /Data.Word 0x1122 /TraceOFF RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 42 PowerProbe or PowerIntegrator, as well as with external tools (using the trigger connector) ;Generate PODBUS trigger signal on data write event with data value Var.Break.Set flags[9] /Write /Data.Byte 0x01 /BusTrigger ;forward signal to trigger connector TrBus.Connect Out TrBus.Mode High RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 43 The clients are controlled with the NEXUS.CLIENT<x> commands. As for the core’s data trace, the amount of generated trace messages is usually too high to be sent through the trace port and the on-chip message FIFO will overflow. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 44 All other message types like branch-trace (BTM) or data-trace (DTM) should be set to OFF. All windows related to the SFT recordings are opened with the command prefix “SFTT”. e.g.: SFTT.List SFTT.Chart Demo scripts can be found in the TRACE32 installation subdirectory ~~/demo/rh850/etc/sft_trace/ Use: demo_sfttrace.cmm RH850 Debugger and Trace 1989-2025 ©...
  • Page 45 Select the highest possible LPD4 baud rate to get good trace performance. All windows related to the SFT recordings are opened with the command prefix “SNOOP”. e.g.: SNOOP.List SNOOP.Chart Demo scripts can be found in the TRACE32 installation subdirectory ~~/demo/rh850/etc/sft_trace/ Use: demo_sftsnoop.cmm RH850 Debugger and Trace 1989-2025 ©...
  • Page 46 Informs the debugger about the position of the Test Access Ports (TAP) in the JTAG chain which the debugger needs to talk to in order to access the debug and trace facilities on the chip. RH850 Debugger and Trace 1989-2025 ©...
  • Page 47 Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down resistor, other trigger inputs need to be kept in inactive state. Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701). RH850 Debugger and Trace 1989-2025 ©...
  • Page 48 (default: OFF) If more than one debugger share the same debug port, all except one must have this option active. JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 49 SYStem.CONFIG.IRPOST 8. ; IR Core A + B SYStem.CONFIG.DRPRE ; DR Core D SYStem.CONFIG.DRPOST 2. ; DR Core A + B SYStem.CONFIG.CORE 0. 1. ; Target Core C is Core 0 in Chip 1 RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 50 TapStates Exit2-DR Exit1-DR Shift-DR Pause-DR Select-IR-Scan Update-DR Capture-DR Select-DR-Scan Exit2-IR Exit1-IR Shift-IR Pause-IR Run-Test/Idle Update-IR Capture-IR Test-Logic-Reset RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 51 GUI uses a new chip_index according to its CORE= parameter of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must be merged by calling SYStem.CONFIG.CORE. RH850 Debugger and Trace 1989-2025 ©...
  • Page 52 SYStem.CONFIG.DEBUGPORTTYPE <port_type> <port_type>: JTAG | LDP1 | LDP4 | UART | UART1 | CSI Default: JTAG. It specifies the used debug port type. It assumes the selected type is supported by the target. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 53 The WDTDIS pin is driven high when program is stopped (not XCP). LowwhenStopped The WDTDIS pin is driven low when program is stopped (not XCP). SLAVE The WDTDIS state of the XCP slave is not changed. (XCP only) RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 54 Core clock frequency Format: SYStem.CORECLOCK [<frequency>] Default core clock: 80MHz. This setting informs TRACE32 about the core clock frequency. During Serial-Flash-Programming mode this value is sent to the CPU to configure the CPU internal PLL. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 55 If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give debug access to another tool. RH850 Debugger and Trace 1989-2025 ©...
  • Page 56 StopAndGo Enables memory access while core is running (intrusive). Has to be used if the specified memory location is not accessible with non-intrusive mode. Denied Disables any memory access while core is running. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 57 See also SYStem.Option.RESetBehavior. Resets the target and sets the CPU to debug mode. After execution of this command the CPU is stopped and prepared for debugging. All register are set to the default value. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 58 If possible (nRESET is open collector), this command asserts the nRESET line on the debug connector. This will reset the target including the CPU but not the debug port. The function only works when the system is in SYStem.Mode.Up. RH850 Debugger and Trace 1989-2025 ©...
  • Page 59 Format: SYStem.Option.CFU [ON | OFF] Enables TRACE32 specific support for the RH850 CalibrationFunctionUnits (G4-core variants only!). The CalibrationFunctionUnits are only available in RH850 emulation devices. Typically the CalibrationFunctionUnits are used by other tool vendors to replace FLASH areas by Calibration-RAM.
  • Page 60 Behavior of SYStem.Mode Down Format: SYStem.Option.DOWNMODE TriState | ReSeT Configures the behavior of SYStem.Mode Down: TriState (default) All drivers of the debug port are switched off. ReSeT The CPU is held in reset. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 61 Sets the time that the debugger will drive the reset pin LOW, e.g. at SYStem.Up. If called without parameter, the default reset hold time of 10ms is used. hold time wait time RESET pin RESET RESET/BIST DEBUG_HALT CPU State RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 62 See also SYStem.Option.WaitReset and SYStem.Option.SLOWRESET. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 63 Erase code- and data-flash. ; erase code flash FLASH.Erase 1. ; erase application data-flash FLASH.Erase 0xff200000--(0xff207fff-IcuSize) Disable ICU-S. SYStem.Option.ICUS OFF ; erases icus-data-flash + disable ICU- The setting becomes active with the next reset. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 64 NOTES: SYStem.Option.KEYCODE SYStem.Option.OCDID SYStem.Option.CFID SYStem.Option.DFID • The command only has an effect in UART mode (not in debugging modes). • Programming is done immediate, be sure you have set the right KeyCode values! RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 65 Note: The Renesas Flash Programmer uses a different byte order for the KEYCODE programming. So it is necessary to swap the bytes. Renesas: 0x00112233 44556677 8899AABB CCDDEEFF TRACE32: SYStem.Option.KEYCODE 0x33 0x22 0x11 0x00 0x77 0x66 0x55 0x44 0xBB 0xAA ..RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 66 Note: The Renesas Flash Programmer uses a different byte order for the OCDID programming. So it is necessary to swap the bytes. Renesas: 0x..88776655 76543210 TRACE32: SYStem.Option.OCDID 0x.. 0x..0x55667788 0x10325476 RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 67 (JTAG, LPD4 or LPD1). SYStem.Option.OPtionByTe8 Option-byte setting Format: SYStem.Option.OPtionByTe8 [<8x_32bit_values>] Display and reprogram of CPU OptionBytes(8 to 15). OptionByte programming is only supported in SerialFlashProgramming mode. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 68 ID-code. For details of the flash areas protected by this customer ID, refer to the CPU reference manual. The command is only relevant for devices that support this type of protection. RH850 Debugger and Trace 1989-2025 ©...
  • Page 69 Have to be the same values as present in CPUs CIDC[0..7] registers. SYStem.Option.PERSTOP Disable CPU peripherals if stopped Format: SYStem.Option.PERSTOP [ON | OFF] Stop CPU peripherals if program is stopped. Useful to prevent timer exceptions. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 70 ResetStart RESYNC Defines the debugger’s action when a reset is detected. Default setting is ResetHalt. This option is only supported for RH850 devices with G4-core. If and how a reset can be detected is set using SYStem.Option.ResetDetection. Disabled No actions to the processor take place when a reset is detected.
  • Page 71 Default: ON. Set to OFF if cpu RDY- pin is not available or not connected to the debug connector. The setting is only relevant if debug communication is done in JTAG mode (DEBUGPORTTYPE == JTAG). RH850 Debugger and Trace 1989-2025 ©...
  • Page 72 A wait time of several ms should be sufficient. If a wait time > 10ms is required, the target might require a stronger RESET pull-up resistor. hold time wait time RESET pin RESET RESET/BIST DEBUG_HALT CPU State For related commands, see also SYStem.Option.HoldReset and SYStem.Option.SLOWRESET. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 73 SYStem.Option (Exception Lines Enable) The RH850 supports disabling of several CPU core inputs. This can be useful to lock watchdog- or target resets. SYStem.Option.CPINT CPINT line enable Format: SYStem.Option.CPINT [ON | OFF] (deprecated) No function anymore. SYStem.Option.REQest Request line enable Format: SYStem.Option.REQ [ON | OFF]...
  • Page 74 SYStem.Option.STOP Stop line enable Format: SYStem.Option.STOP [ON | OFF] Default: ON. Enables/disables the stop line. SYStem.Option.WAIT Wait line enable Format: SYStem.Option.WAIT [ON | OFF] Default: ON. Enables/disables the wait line. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 75 SYStem.MemAccess CPU). Performance counters and event counters of RH850 CPUs can be started or stopped using on-chip breakpoints. This A-to-B mode allows to determine performance metrics for a single code block. RH850 CPUs support two different types of benchmark counters: •...
  • Page 76 BMC.BCNT2.RATIO.runtime(X/CLOCK) BMC.BCNT3.EVENT.ATOB ; AtoB Events BMC.BCNT3.ATOB.TOTAL BMC.BCNT3.RATIO.OFF BMC.RESet Break.Delete ;set up counter start / stop events Break.Set sYmbol.BEGIN(sieve) /Onchip /Alpha Break.Set sYmbol.EXIT(sieve) /Onchip /Beta ;run measurement (for 10 seconds) BMC.Init Wait 10s Break RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 77 Counts Core-Clock for BCNT, counts Debug-Clocks for TCNT. ATOB Counts A-to-B events. INST Counts instructions. Counts branch instructions. Counts EI-interrupt acknowledges. Counts FE-interrupt acknowledges. ASEXP Counts asynchronous exception acknowledges. SEXP Counts synchronous exception acknowledges. STALL Counts Stall cycles. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 78 AtoB-MIN --> Trigger if counter-value-min < trigger-value • AtoB-MAX --> Trigger if counter-value-max > trigger-value • AtoB-TOTAL --> Trigger if counter-value-total > trigger-value BMC.<counter>.TRIGVAL BMC trigger value Format: BMC.<counter>.TRIGVAL [<value>] Defines the BenchMarkCounter trigger value. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 79 The debugger can set any user-defined range breakpoint because the debug logic accepts this range breakpoint. The debug logic accepts only certain range breakpoints. The debugger calculates the range that comes closest to the user-defined breakpoint range (see “modified range” in the figure above). RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 80 Aurora trace trigger input. In this case TrOnchip.EVTEN should be set to OFF. Enables the Aurora trace trigger input. Disables the Aurora trace trigger input. TrOnchip.RESet Set on-chip trigger to default state Format: TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 81 If ON, breakpoints on single-byte, two-byte or four-byte address ranges only hit if the CPU accesses this ranges with a byte, word or long bus cycle. TrOnchip.state Display on-chip trigger window Format: TrOnchip.state Opens the TrOnchip.state window. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 82 TrOnchip. Var.Break.Set <scalar> VarCONVert Program debug logic unmodified range Range fits to debug logic? modified range TrOnchip. CONVert Error RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 83 TrOnchip.CONVert. In the Break.List window, you can view the requested address range for all breakpoints, whereas in the Break.List /Onchip window you can view the actual address range used for the on-chip breakpoints. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 84 Sets the data trace mode of the selected trace client. Select the trace client using NEXUS.CLIENT<x>.SELECT before setting the trace mode. When using “DTM” the client trace mode follows the setting of NEXUS.DTM. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 85 Write Data trace messages for write accesses (store instructions) ReadWrite Data trace messages for read and write accesses (load and store instructions) ReadLimited Same as above, but exclude stack operations (sp,r3) WriteLimited ReadWrite-Limited RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 86 Sets the NEXUS trace port frequency. For parallel NEXUS, the setting is the system clock divider. For Aurora NEXUS, the setting is a fixed bit clock which is independent of the system frequency. NOTES: Aurora NEXUS: Set the bit clock according to the processor’s data sheet. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 87 NEXUS FIFO are sent. Enabling this command will affect (delay) the instruction execution timing of the CPU. This system option, which is a representation of a feature of the processor, will remarkably reduce the amount FIFO OVERFLOW errors, but can not avoid them completely. RH850 Debugger and Trace 1989-2025 ©...
  • Page 88 Forces NEXUS address-sync trace messaging on all branch instructions. Note for OnchipTrace (optional bugfix): There are RH850 devices with a bug in the NEXUS coding for Onchip-Trace. If there are flow-errors in the trace listing please set “NEXUS.SYNC ON” and try again.
  • Page 89 (tracing to PowerTrace unit), on-chip timestamps are usually not needed, because the PowerTrace unit will add it’s own timestamp. When using the on-chip trace, enable NEXUS.TimeStamps for run-time measurements. NOTE: Timestamps will consume ~20% of the trace bandwidth/trace memory. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 90 ;Enable data trace messaging NEXUS.DTM ReadWrite ;declare events Alpha/Beta used for trace source control Break.Set my_func /Program /Onchip /Alpha Break.Set 0x40001234 /Write /Onchip /Beta ;Set function of Alpha/Beta events TrOnchip.Alpha DataTraceON TrOnchip.Beta DataTraceOFF RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 91 ; assign events to data trace on/off for client 1 TrOnchip.Alpha TraceONClient1 TrOnchip.Beta TraceOFFClient1 TrOnchip.Beta Set special breakpoint function Format: TrOnchip.Beta <function> See TrOnchip.Alpha. TrOnchip.Charly Set special breakpoint function Format: TrOnchip.Charly <function> See TrOnchip.Alpha. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 92 TrOnchip.Delta Set special breakpoint function Format: TrOnchip.Delta <function> See TrOnchip.Alpha. TrOnchip.Echo Set special breakpoint function Format: TrOnchip.Echo <function> See TrOnchip.Alpha. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 93 The device-id is read from the CPU during the SYStem.Up SYStem.Mode.Prepare processing. Return Value Type: value. CPU.SUBFAMILY() CPU subfamily [build 68566- DVD 02/2016] Syntax: CPU.SUBFAMILY() Returns the CPU subfamily name, e.g. RH850/E2x or RH850/F1L. Return Value Type: String. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 94 TRACE32 autosetup script. Return Value Type: Decimal value. SYStem.CFID() Values of CodeFlashID [build 93608 - DVD 09/2018] Syntax: SYStem.CFID(<0..7>) Returns the values defined with SYStem.Option.CFID command. Return Value Type: value. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 95 SYStem.OPBT8() Values of Option-bytes [build 50281 - DVD 02/2014] Syntax: SYStem.OPBT8(<0..7>) Returns the values of CPU OptionBytes(8 to 15). The option-byte values are read from the CPU during SYStem.Mode.Prepare. Return Value Type: value. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 96 SYStem.RESETDETECTION() Reset detection method [build 134000 - DVD 09/2021] Syntax: SYStem.RESETDETECTION() Returns the option-string entered by the command SYStem.Option.ResetDetection. Return Value Type: String. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 97 Sense target Reset, input for debugger FLMD0 FLASH Mode0 signal, output of FLMD0 FLMD0 FLMD0 debugger • Enable flash programming FLMD1 Mode configuration pin (optional) PullDown PullDown PullDown FLMD2 Mode configuration pin (optional, not used yet) RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 98 Target voltage sense, input for debugger Debug Connector 26 Signal Signal VTREF KEY(GND) GND(PRESENCE) RESET- RESETOUT- WDTDIS TRST- FLMD0 RDY- BREQ- BGRNT- EXTIO RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 99 Trace Connectors and Adapters Adapter for RH850 (LA-3561) Connector Function AUTO26 debug connector JTAG14 debug connector Target connector PowerTrace Serial connector for Serial Port 1 Jumper Function X130 Set: Connects pin 16 (EVTI) of the target connector to TRIGOUT of...
  • Page 100 Open: pin 24 of Auto26 is open Both debug connectors AUTO26 [A] or the JTAG14 [B] hold the same debug signals coming from the target connector [C]. Only one debug connector must be used at the time. RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 101 Signals in brackets are optional. These could be used if no additional 14pin debug connector is available on the target. Please use an adaptor (LA-3885) to split the target signals for debug and trace. RH850 Debugger and Trace 1989-2025 ©...
  • Page 102 This target pin-assignment requires adaptors to connect to the TRACE32 tools. LA-xxxx: Convert SAMTEC 34pin -> SAMTEC 40pin (Trace only) LA-xxxx: Split-adapter SAMTEC 34pin -> SAMTEC 40pin, RH850-14pin, RH850-motive We recommend to place the even numbered pins at the PCB border side (flex cable won't be twisted).
  • Page 103 Aurora NEXUS SAMTEC 40-pin (Trace only) SAMTEC 40-pin (Trace only) Signal Signal TX0+ TX0- TX1+ TX1- EVTI- CREF+ EVTO- CREF- We recommend to place the even numbered pins at the PCB border side (flex cable won't be twisted). RH850 Debugger and Trace 1989-2025 © Lauterbach...
  • Page 104 This target pin-assignment requires adaptors to connect to the TRACE32 tools. LA-3899: Converter for RH850-Samtec34 pin assignment to a target with Samtec46 debug/trace connector We recommend to place the even numbered pins at the PCB border side (flex cable won't be twisted).