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Related Manuals for Lauterbach dsPIC33
Summary of Contents for Lauterbach dsPIC33
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Page 1: Dspic33 Debugger
Debugger Release 02.2022 MANUAL... -
Page 2: Table Of Contents
Debug Monitor Breakpoints Software Breakpoints On-chip Breakpoints for Instructions On-chip Breakpoints for Data Memory Classes Programming the On-chip FLASH of the dsPIC33 Special Hints, Restrictions, and Known Problems Special Hints Restrictions Known Problems CPU specific SYStem Settings ..................SYStem.CLockPrescaler... - Page 3 Disable interrupts while single stepping SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping SYStem.Option.PARTitionconfig Configure the Flash partitions SYStem.Option.PoWeRSaVe Enable PWRSAV instruction SYStem.state Display SYStem.state window CPU specific TrOnchip Commands ................. Target Adaption ......................... Probe Cables Connector Type and Pinout 1989-2022 © Lauterbach dsPIC33 Debugger...
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Page 4: History
Debugger Version 09-Mar-2022 History 01-Jan-21 Added support for dsPIC33E family. 04-May-20 Supplemented section “Start a New Debug Session” with description of implemented feature SYStem.DETECT.CPU. 20-Feb-20 New command: SYStem.Mode Prepare. New section “Programming a Productive Application Binary”. 1989-2022 © Lauterbach... -
Page 5: Warning
Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the debug cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 6: Introduction
(the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice. -
Page 7: Demo And Start-Up Scripts
You can also inspect the demo folder manually in the system directory of TRACE32. The ~~/demo/pic/ folder contains: flash/ Scripts for target based programming and example declarations for internal flash. hardware/ Ready-to-run debugging and flash programming demos for evaluation boards. Recommended for getting started! 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 8: Configuration
Example configuration for a single core debugger. PC or Workstation Target Debug Cable POWER DEBUG USB INTERFACE / USB 3 Cable POWER DEBUG INTERFACE / USB 3 Please consider the tips given in the chapter “Connector Type and Pinout”, page 26. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 9: Quick Start
FLASH.UNSECUREerase If the CPU DSPIC33XXXX is selected, TRACE32 tries to detect the CPU type of the connected target before the system is brought up. Load the program into the program memory. DO ~~/demo/pic/flash/dspic33cxxxx.cmm 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 10: Programming A Productive Application Binary
WinPOS command. NOTE: Due to the architecture of the dsPIC33 microcontroller, the on-chip breakpoints halt the target two instructions after the program counter (PC) reached the address of an on-chip breakpoint. This is called skid. Programming a Productive Application Binary To write an application where the debug access is disabled to the program memory, a different approach must be used. - Page 11 Write the remaining program memory. FLASH.ReProgram 1. Data.LOAD.auto * FLASH.ReProgram off The program binary selected for the Data.LOAD.auto command should be the same as in the previous step. Reset target SYStem.RESet 1989-2022 © Lauterbach dsPIC33 Debugger...
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Page 12: Troubleshooting
Invalid memory access No special event Internal error, please consult your size: <size> bytes (@ Lauterbach representative. address <address>) Memory access timeout: No special event Corrupted debug connection. Check Reading from address debug hardware and settings. <address> 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 13: Faq
• The core has no clock. • The core is kept in reset. • There is a watchdog which needs to be deactivated. Please refer to our Frequently Asked Questions page on the Lauterbach website. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 14: Dspic33 Specific Implementations
The debug monitor is designed to support all basic and advanced debug features offered by a certain dsPIC33 family. The Lauterbach debug monitors require up to 2.908 Bytes of memory and must be loaded to the address P:0x800000. This is a separate area in the flash memory and does not affect the space available for user programs. -
Page 15: On-Chip Breakpoints For Instructions
Up to five on-chip breakpoints of dsPIC33 MCUs can be used as data breakpoints. On the slave core of a dsPIC33CH derivative one data breakpoint is available. -
Page 16: Memory Classes
Memory Classes The dsPIC33 architecture is a Harvard-type processor architecture. Therefore, following different memory access classes are available: Access Class Description Data Program To access a memory class, write the class in front of the address. For example, use D to access the data memory: Data.dump D:0x00... -
Page 17: Programming The On-Chip Flash Of The Dspic33
Programming the On-chip FLASH of the dsPIC33 The PRACTICE script for programming of the on-chip FLASH of a dsPIC33 can be found in the TRACE32 demo folder ~~/demo/pic/flash/. For programming the program memory of a dsPIC33E core, the script dspic33epxxx.cmm should be used. -
Page 18: Cpu Specific System Settings
Opens the SYStem.CONFIG.state window on the specified tab. For tab descriptions, see below. DebugPort The DebugPort tab informs the debugger about the debug connector (default) type and the communication protocol it shall use. For descriptions of the commands on the DebugPort tab, see DebugPort. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 19: System.config
Default: OFF. Default: ON if CORE=... >1 in the configuration file (e.g. config.t32). TriState [ON | OFF] TriState has to be used if several debug cables are connected to a common debug port. Default: OFF. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 20: System.cpu
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the connector of the debugger is tristated. The intention of the SYStem.LOCK command is, for example, to give debug access to another tool. The process can also be automated, see SYStem.CONFIG TriState 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 21: System.memaccess
No real-time To update specific windows that display memory or variables while the program is running, select the memory class E: or the format option %E. Data.dump E:0x100 Var.View %E first 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 22: System.mode
After this command the user program can be stopped with the break command or by any other break condition (e.g a breakpoints). Resets the target and stops the CPU at the reset vector. StandBy Not available for this architecture. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 23: System.option
If enabled, a loaded program can switch the clock group used by the CPU. Otherwise a break occurs. SYStem.Option.ENableWDT Enable watchdog timer Format: System.Option.ENableWDT [ON | OFF] Default: ON. This option enables a global Watchdog timer. The system’s reaction to a Watchdog time-out can be configured by using SYStem.Option.BReakonWDT. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 24: System.option.fastrc
SYStem.Option.FreezePer [ON | OFF] Default: OFF. The on-chip peripherals of a dsPIC33 chip have can be configured to freeze when the program execution is interrupted. Several of those peripherals have no separate FREEZE bit in the configuration registers. All the peripherals lacking such a FREEZE are globally controlled by this configuration bit. -
Page 25: System.option.imaskhll
This option is not supported by all dsPIC33 MCUs. Several dsPIC33 MCUs support an on-chip Flash memory which can be split into two partitions. The active partition begins at address 0x000000 and in case of a dual partition configuration, the inactive partition begins at address 0x400000. -
Page 26: System.state Display System.state Window
If enabled, the PWRSAV instruction will cause the chip to enter Idle or Sleep mode. Otherwise the program execution will be interrupted. SYStem.state Display SYStem.state window Format: SYStem.state Displays the SYStem.state window for system settings that configure debugger and target behavior. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 27: Cpu Specific Tronchip Commands
CPU specific TrOnchip Commands The TrOnchip command group is not available for the dsPIC33 debugger. 1989-2022 © Lauterbach dsPIC33 Debugger... -
Page 28: Target Adaption
Target Adaption Probe Cables For debugging a dsPIC33 single or master core, the following kinds of probe cables can be used to connect the debugger to the target: • Debug Cable • CombiProbe The debug logic of the dsPIC33CH family only allows to debug a single core at a time. Debugging the second core requires either a second Debug Cable with a second tool set or a CombiProbe with two Whiskers.
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