Lauterbach TRACE32 Manual
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Lauterbach TRACE32 Manual

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PQIII Debugger

Release 09.2021
MANUAL

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Summary of Contents for Lauterbach TRACE32

  • Page 1: Pqiii Debugger

    PQIII Debugger Release 09.2021 MANUAL...

  • Page 2: Table Of Contents

    PQIII Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index  TRACE32 Documents ........................ ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... PQIII ............................PQIII Debugger ........................Introduction ........................Brief Overview of Documents for New Users Warning ..........................
  • Page 3 Use alternative method for ASM single step CPU specific MMU Commands ..................MMU.DUMP Page wise display of MMU translation table MMU.List Compact display of MMU translation table MMU.SCAN Load MMU table from CPU MMU.Set Set an MMU TLB entry 1989-2021 © Lauterbach GmbH PQIII Debugger...
  • Page 4 TrOnchip.VarCONVert Adjust HLL breakpoint in on-chip resource TrOnchip.state View on-chip trigger setup window MPC85XX/QorIQ Specific On-chip Trace Settings ............Onchip.Mode.IFSel Select interface to be traced JTAG Connector ........................ Mechanical Description JTAG Connector MPC85XX (COP) 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 5: Introduction

    (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.

  • Page 6: Warning

    Recommendation for the software start: Disconnect the Debug Cable from the target while the target power is off. Connect the host system, the TRACE32 hardware and the Debug Cable. Power ON the TRACE32 hardware. Start the TRACE32 software to load the debugger firmware.

  • Page 7: Target Design Requirement/Recommendations

    The T32 internal buffer/level shifter will be supplied via the VCCS pin. with blue Therefore it is necessary to reduce the VCCS pull-up on the target board to a value smaller 10 . ribbon cable 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 8: Quick Start

    The option of the Data.LOAD command depends on the file format generated by the compiler. A detailed description of the Data.LOAD command is given in the “General Commands Reference”. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 9: Troubleshooting

    SYStem.Option.SLOWRESET, and check signal level of the JTAG HRESET pin. • The target reset is permanently asserted. Check target reset circuitry and reset pull-up • A chip external watchdog caused a reset after the debugger asserted reset. Disable the watchdog and try again. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 10: Faq

    If the bootstrap configuration was found to be wrong or needs to be changed temporarily (e.g. for NAND programming), it is possible to override the bootstrap configuration setting through JTAG. For instructions again please contact support using above email address. Please refer to our Frequently Asked Questions page on the Lauterbach website. 1989-2021 ©...

  • Page 11: Configuration

    PODBUS Cable PODPC PODPAR Debug EPROM PODETH Interface Simulator (optional) Debug Cable   CPU CLK RESET  Target Connector (600 EPROM only)  Target TS4 (400 only) Basic configuration for the BDM Interface 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 12: Powerpc Mpc85Xx/Qoriq Specific Implementations

    You can see the currently set breakpoints with the command Break.List. If no more on-chip breakpoints are available you will get an error message when trying to set a new on-chip breakpoint. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 13: Breakpoints On Program Addresses

    Equal to program address breakpoints, data address breakpoints can be configured to stop if the break event occurred a given number of times: ;stop on the 8th write to arrayindex Break.Set arrayindex /Write /COUNT 20. Data address breakpoint limitations: 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 14: Breakpoints On Data Access At Program Address

    Break.Set sYmbol.RANGE(test_func) /EXclude /MemoryWrite nTestValue Breakpoints on Data Value The e500 core does not support onchip breakpoints on data values, but TRACE32 supports them by software emulation. When a data value breakpoint is set, the debugger will use one of the data address breakpoint s.
  • Page 15 ;Break when a value not equal 0x98 is written to the 8-bit variable xval Break.Set xval /Write /Data.Byte !0x98 ;Break when decimal 32-bit value 4000 is written ;to variable count within function foo Break.Set sYmbol.RANGE(foo) /MemoryWrite count /Data.Long 4000. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 16: Access Classes

    Access Classes Access classes are used to specify how TRACE32 PowerView accesses memory, registers of peripheral modules, addressable core resources, coprocessor registers and the TRACE32 Virtual Memory. Addresses in TRACE32 PowerView consist of: • An access class, which consists of one or more letters/numbers followed by a colon (:) •...

  • Page 17: Access Classes To Other Addressable Core And Peripheral Resources

    TS (translation space) == 1 (user memory) TS (translation space) == 0 (supervisor memory) If an Access class attributes is specified without an access class, TRACE32 PowerView will automatically add the default access class of the used command. For example, Data.List...
  • Page 18 (*) updated updated (*) Depending on the debugger configuration, the coherency of the instruction cache will not be achieved by updating the instruction cache, but by invalidating the instruction cache. See SYStem.Option.ICFLUSH for details. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 19: Mesi States And Cache Status Flags

    Status bits of the cache line v(alid), d(irty), s(hared) MESI state l(ocked). 00 04 08 ... Address offsets within cache line corresponding to the cached data address (right field) Debug symbol assigned to address 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 20: Debugging Information

    CORE <core_index> command. The currently selected core is displayed in the status line. If the cores are running and one of the cores hits a breakpoint, the debugger’s view will automatically switch to this core. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 21: Amp Debugging

    AMP Debugging For AMP debugging, a separate instance of TRACE32 has to be started for each core. It is recommended to use TRACE32 Start to start the TRACE32 instances. Optionally the second instance can also be started by PRACTICE script. Each TRACE32 instance has to be configured to address one of the cores. This is done using the commands SYStem.CONFIG.CORE...

  • Page 22: On-Chip Trace On Mpc85Xx/Qoriq

    0x20000000 source ID enable 0x04000000 method trace events 0x00020000 Data.Set iobase.address()+0x000E2040 %LONG 0x64020000 ; TBCR1 src ID = d-fetch 0x00110000 Data.Set iobase.address()+0x000E2044 %LONG 0x00110000 ; enable automatically when CPU is started Onchip.AutoArm ON 1989-2021 © Lauterbach GmbH PQIII Debugger...
  • Page 23 Also data trace is limited to uncached accesses. The data value of the load/store access is not contained in the trace data. For more information about general trace commands see ’Trace’ in ’General Commands Reference Guide T’ ’Onchip Trace Commands’ in ’General Commands Reference Guide O’. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 24: Powerpc Mpc85Xx/Qoriq Specific System Commands

    Alternatively, you can modify the target configuration settings via the TRACE32 command line with the SYStem.CONFIG commands. Note that the command line provides additional SYStem.CONFIG commands for settings that are not included in the SYStem.CONFIG.state window.

  • Page 25: System.config

    NOTE: When using the TriState mode, nTRST/JCOMP must have a pull-up resistor on the target. In TriState mode, a pull-down is recommended for TCK, but targets with pull- up are also supported. 1989-2021 © Lauterbach GmbH PQIII Debugger...
  • Page 26 (default: OFF) If more than one debugger share the same JTAG port, all except one must have this option active. Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). 1989-2021 © Lauterbach GmbH PQIII Debugger...
  • Page 27 ; So type just the DR of TAP4, i.e. 1. SYStem.CONFIG DRPOST ; DRPOST: Add up one DR bit per TAP which ; is in BYPASS mode, i.e. 1. + 1. + 1. = 3. ; This completes the configuration. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 28: System.config.chkstpin

    Exit1-IR Shift-IR Pause-IR Run-Test/Idle Update-IR Capture-IR Test-Logic-Reset SYStem.CONFIG.CHKSTPIN Control pin 8 of debug connector Format: SYStem.CONFIG.CHKSTPIN LOW | HIIGH Default: HIGH. Controls the level of pin 8 (/CHKSTP_IN or /PRESENT) of the debug connector. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 29: System.config.driverstrength

    Controls the level and function of pin 2 (/QACK) of the debug connector. Default: TRISTATE. TRISTATE Pin is disabled (tristate). QREQ Pin is driven to level of QREQ (pin 5). Pin is driven to GND permanently. HIGH Pin is driven to JTAG_VREF permanently. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 30: System.cpu

    If the processor release occurred after the debugger software release, the processor is most likely not supported. Please check the Lauterbach download center (www.lauterbach.com) for updates. If the debugger software version from the download center also does not support the processor, please contact technical support and request a software update.

  • Page 31: System.memaccess

    Data.dump E:0x100) or by using the format option %E (e.g. Var.View %E var1). It is also possible to activate this non-intrusive memory access for all memory ranges displayed on the TRACE32 screen by setting SYStem.Option.DUALPORT Denied Memory access is disabled while the CPU is executing code.

  • Page 32: System.mode

    The debugger will wait until power on is detected and then stop the CPU at the first instruction at the reset address. Resets the target/processor and sets the CPU to debug mode. After execution of this command the CPU is stopped and prepared for debugging. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 33: Cpu Specific System.option Commands

    This option has impact on the real-time behavior. Releasing a secondary core from reset / disable state will be delayed for a few milliseconds. SYStem.Option.DCFREEZE Prevent data cache line load/flush in debug mode Format: SYStem.Option.DCFREEZE [ON | OFF] Default: OFF. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 34: System.option.dcread

    Please note that while the CPU is running, MMU address translation can not be accesses by the debugger. Only physical addresses accesses are possible. Use the access class modifier “A:” to declare the access physical addressed, or declare the address translation in the debugger-based MMU manually using TRANSlation.Create. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 35: System.option.freeze

    Invalidates the instruction cache before starting the target program (Step or Go). If this option is disabled, the debugger will update Memory and instruction cache for program memory downloads, modifications and breakpoints. Disabling this option might cause performance decrease on memory accesses. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 36: System.option.icread

    MSR_EE while the CPU is running and restore it after the CPU stopped. If a part of the application is executed that disables MSE_EE, the debugger cannot detect this change and will restore MSE_EE. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 37: System.option.mmuspaces

    If a debug session requires space IDs, you must observe the following sequence of steps: 1. Activate SYStem.Option.MMUSPACES. 2. Load the symbols with Data.LOAD. Otherwise, the internal symbol database of TRACE32 may become inconsistent. Examples: ;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x012A:...

  • Page 38: System.option.notrap

    MPC82XX, MPC5200, RHPPC (G2/G2_LE cores) and MPC830X, MPC831X, MPC832X and MPC512X (e300c2/3/4). Gives the ability to use the program interrupt in the application without halting for JTAG. Illegal instructions as software breakpoints will preserve SRR0/1 registers. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 39: System.option.overlay

    WithOVS Like option ON, but also enables support for software breakpoints. This means that TRACE32 writes software breakpoint opcodes to both, the execution area (for active overlays) and the storage area. This way, it is possible to set breakpoints into inactive overlays. Upon activation of the overlay, the target’s runtime mechanisms copies the breakpoint opcodes to...

  • Page 40: System.option.resetbehavior

    SYStem.Option.STEPSOFT [ON | OFF] This method uses software breakpoints to perform an assembler single step instead of the processor’s built- in single step feature. Works only for software in RAM. Do not turn ON, unless advised by Lauterbach. 1989-2021 ©...
  • Page 41 If the debugger is servicing the watchdog, conditions might occur, where the watchdog times out before the debugger is able to service it. Unintended resets or interrupts can occur. Further, SWT window mode is not supported by the debugger. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 42: Cpu Specific Mmu Commands

    Displays the entries of an MMU translation table. • if <range> or <address> have a space ID: displays the translation table of the specified process • else, this command displays the table the CPU currently uses for MMU translation. 1989-2021 © Lauterbach GmbH PQIII Debugger...
  • Page 43 This command reads the table of the specified process, <space_id>:0x0 and displays its table entries. • For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 44: Mmu.list

    Lists the entries of an MMU translation table. • if <range> or <address> have a space ID: list the translation table of the specified process • else, this command lists the table the CPU currently uses for MMU translation. 1989-2021 © Lauterbach GmbH PQIII Debugger...
  • Page 45 This command reads the table of the specified process, <space_id>:0x0 and lists its address translation. • For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 46: Mmu.scan

    This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debugger- internal static translation table. See also the appropriate OS Awareness Manual. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 47: Mmu.set

    MAS7 contains the most significant bits of the physical 36 bit address (e500v2 cores only). Sets the specified MMU TLB table entry in the CPU. The parameter <tlb> is not available for CPUs with only one TLB table. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 48: Cpu Specific Benchmarkcounter Commands

    If contradicting states are enabled (e.g. SUPERVISOR and USER), the counter will be permanently frozen. The table below explains the meaning of the individual states. <state> Dependency in core USER Counter frozen if MSR[PR]==1 SUPERVISOR Counter frozen if MSR[PR]==0 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 49: Bmc..Size

    MASKSET Counter frozen if MSR[PMM]==1 MASKCLEAR Counter frozen if MSR[PMM]==0 BMC.<counter>.SIZE No function Format: BMC.<counter>.SIZE <size> Since only one counter size is possible, this command is only available for compatibility reasons. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 50: Cpu Specific Tronchip Commands

    NEXUS block. This option can be used to manually set up the NEXUS trace registers. The NEXUS memory access is not affected by this command. To re-enable NEXUS register control, use command TrOnchip.ENable. Per default, NEXUS register control is enabled. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 51: Tronchip.enable

    Enables NEXUS register control by the debugger. By default, NEXUS register control is enabled. This command is only needed after disabling NEXUS register control using TrOnchip.DISable. TrOnchip.RESet Reset on-chip trigger settings Format: TrOnchip.RESet Resets the on-chip trigger system to the default state. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 52: Tronchip.set

    Break on debug interrupt - do not clear if breakpoints are used. SPEU Break on SPE APU unavailable interrupt. SPED Break on SPE floating-point data interrupt. SPER Break on SPE floating-point round interrupt. Break on performance monitor interrupt. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 53: Tronchip.varconvert

    An error message is displayed when the user wants to set a new data address breakpoint after all on-chip breakpoints are spent by a data address breakpoint to an HLL variable. TrOnchip.VarCONVert ON Var.Break.Set flags Var.Break.Set ast Data.View flags Data.View ast 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 54: Tronchip.state View On-Chip Trigger Setup Window

    TrOnchip.state View on-chip trigger setup window Format: TrOnchip.state Display the trigger setup dialog window. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 55: Mpc85Xx/Qoriq Specific On-Chip Trace Settings

    Interface selection. Specifies the interface that sources information for both comparison/buffer control and buffer data capture. The availability of certain <interface> options depends on the target processor. Please check the processor user’s manual for which interfaces are available. 1989-2021 © Lauterbach GmbH PQIII Debugger...

  • Page 56: Jtag Connector

    This is a standard 16 pin double row (two rows of eight pins) connector (pin-to-pin spacing: 0.100 in.). (Signals in brackets are not strong necessary for basic debugging, but its recommended to take in consideration for future designs.) 1989-2021 © Lauterbach GmbH PQIII Debugger...

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