Lauterbach TRACE32 Manual
  1. Manuals
  2. Brands
  3. Lauterbach Manuals
  4. Computer Accessories
  5. TRACE32
  6. Manual

Lauterbach TRACE32 Manual

Meta debugger
Hide thumbs Also See for TRACE32:
Table of Contents

Advertisement

Quick Links

Download this manual

Meta Debugger

Release 02.2022
MANUAL

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the TRACE32 and is the answer not in the manual?

Questions and answers

Related Manuals for Lauterbach TRACE32

Summary of Contents for Lauterbach TRACE32

  • Page 1: Meta Debugger

    Meta Debugger Release 02.2022 MANUAL...

  • Page 2: Table Of Contents

    Meta Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index  TRACE32 Documents ........................ ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... Meta ............................Meta Debugger ........................Introduction ........................Brief Overview of Documents for New Users Demo and Start-up Scripts Warning ..........................
  • Page 3 SYStem.state Display SYStem.state window TrOnchip.RESet Set on-chip trigger to default state TrOnchip.state Display on-chip trigger window Target Adaption ......................... Interface Standards JTAG, Serial Wire Debug, cJTAG Connector Type and Pinout Debug Cable 1989-2022 © Lauterbach Meta Debugger...
  • Page 4 Meta Debugger Version 09-Mar-2022 1989-2022 © Lauterbach Meta Debugger...

  • Page 5: Introduction

    (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.

  • Page 6: Demo And Start-Up Scripts

    File menu > Search for Script. You can now search the demo folder and its subdirectories for PRACTICE start-up scripts (*.cmm) and other demo software: You can also inspect the demo folder manually in the system directory of TRACE32. The ~~/demo/meta/ folders contain: hardware/ Ready-to-run debugging and flash programming demos for evaluation boards.

  • Page 7: Warning

    Recommendation for the software start: Disconnect the Debug Cable from the target while the target power is off. Connect the host system, the TRACE32 hardware and the Debug Cable. Power ON the TRACE32 hardware. Start the TRACE32 software to load the debugger firmware.

  • Page 8: Quick Start Of The Debugger

    Starting up the debugger is done as follows: Reset the debugger. RESet RESet command is only necessary if you do not start directly after booting the TRACE32 development tool. Set the target CPU to configure the debugger. SYStem.CPU <cpu> The default values of all other options are set in such a way that it should be possible to work without modifications.
  • Page 9 *) These commands open windows on the screen. The window position can be specified with the WinPOS command. 1989-2022 © Lauterbach Meta Debugger...

  • Page 10: Troubleshooting

    You might have several TAP controllers in a JTAG-chain. Example: You have a multicore system with chained TAPs. In this case you have to check your pre- and post-bit configuration. See SYStem.CONFIG IRPRE SYStem.CONFIG DRPRE. Please refer to our Frequently Asked Questions page on the Lauterbach website. 1989-2022 © Lauterbach Meta Debugger...

  • Page 11: Meta Specific Implementations

    Core, by setting the MinimEnable flag in the TXPRIVEXT register. To provide HLL debugging capabilities for this concept the T32 Lauterbach SW is reading the MiniM opcodes from the storage- and encodes it to the linker execution address. The HLL debug information are disposed by additionally loading the referring *.elf file with the /NoCODE option.

  • Page 12: Access Classes

    Access classes are used to specify which memory to access. For background information about the term access class, see “TRACE32 Glossary” (glossary.pdf). The following common access classes have the same meaning for all CPUs of the Meta architecture. Access Class Description Program or data memory access.

  • Page 13: Breakpoints

    M core into debug mode. On-chip watchpoints are break before make. In TRACE32, the on-chip watchpoint functionality is mapped to data address breakpoints. That means to set a watchpoint, the Break.Set...
  • Page 14 Break.Set 0x80001000 /Read ; Same as above, since read ; breakpoints are always on-chip Break.Set 0x80001000 /Write ; Write watchpoint for store ; instructions Break.Set 0x80001000 /ReadWrite ; ReadWrite watchpoint for load and ; store instructions 1989-2022 © Lauterbach Meta Debugger...

  • Page 15: System.config

    The commands are not case sensitive. Capital letters show how the command can be shortened. Example: “SYStem.CONFIG.TriState ON” -> “SYStem.CONFIG.TS ON” The dots after “SYStem.CONFIG” can alternatively be a blank. Example: “SYStem.CONFIG.TriState ON” or “SYStem.CONFIG TriState ON” 1989-2022 © Lauterbach Meta Debugger...

  • Page 16: Parameters> Describing The "Debugport

    The command might be required in a multicore environment if you use multiple debugger instances (multiple TRACE32 PowerView GUIs) to simultaneously debug different cores on the same target system. Because of the default setting of this command debugger#1: <core>=1 <chip>=1...
  • Page 17 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2022 © Lauterbach Meta Debugger...

  • Page 18: Parameters> Describing The "Jtag" Scan Chain And Signal Behavior

    TDO signal. See example below. Default: 0. NOTE: If you are not sure about your settings concerning IRPRE, IRPOST, DRPRE, and DRPOST, you can try to detect the settings automatically with the SYStem.DETECT.DaisyChain command. 1989-2022 © Lauterbach Meta Debugger...
  • Page 19 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2022 © Lauterbach Meta Debugger...
  • Page 20 In many cases, the number of TAPs equals the number of cores. But in many other cases, additional TAPs have to be taken into account; for example, the TAP of an FPGA or the TAP for boundary scan. 1989-2022 © Lauterbach Meta Debugger...

  • Page 21: System.config.state

    The choice of the CPU will determine pre-configurations made by the debugger. It will also determine the supported debug monitor. META-MTP Generic CPU for Meta-MTP targets. MSR1-DRPU Meta core DRPU on the MSR1 board SYStem.JtagClock Define JTAG frequency Format: SYStem.JtagClock [<frequency>] <frequency>: 10000. … 40000000. Default frequency: 5 MHz. 1989-2022 © Lauterbach Meta Debugger...

  • Page 22: System.lock

    If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give debug access to another tool. 1989-2022 © Lauterbach Meta Debugger...

  • Page 23: System.memaccess

    Example: If specific windows that display memory or variables should be updated while the program is running, select the access class prefix E or the format option %E. SYStem.MemAccess Enable Data.dump EP:0x100 List E: Var.View %E var1 1989-2022 © Lauterbach Meta Debugger...

  • Page 24: System.mode

    The state of the CPU remains unchanged. Debug mode is not active. In this mode the target behaves as if the debugger is not connected. StandBy Not available. SYStem.Option.IMASKASM Disable interrupts while single stepping Format: SYStem.Option.IMASKASM [ON | OFF] 1989-2022 © Lauterbach Meta Debugger...
  • Page 25 A pending interrupt will be executed on a single-step, but it does not halt there. The specific interrupt handler is completely executed even if single steps are done, i.e. step over is forced per default. If the core should halt in the interrupt routine, use TrOnchip.StepVector ON. 1989-2022 © Lauterbach Meta Debugger...

  • Page 26: System.option.imaskhll

    This command is only needed for Large Minim address ranges! Small Minim handling is done automatically in T32 Software without defining Minim address ranges. SYStem.state Display SYStem.state window Format: SYStem.state Displays the SYStem.state window for system settings that configure debugger and target behavior. 1989-2022 © Lauterbach Meta Debugger...
  • Page 27 TrOnchip.RESet Set on-chip trigger to default state Format: TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. TrOnchip.state Display on-chip trigger window Format: TrOnchip.state Opens the TrOnchip.state window. 1989-2022 © Lauterbach Meta Debugger...
  • Page 28 Interface Standards JTAG, Serial Wire Debug, cJTAG The Debug Cable supports the JTAG (IEEE 1149.1) interface standard. Connector Type and Pinout Debug Cable Adaption for ARM Debug Cable: See https://www.lauterbach.com/adarmdbg.html. These adaptations also cover the Meta possibilities. Mechanical description of the 20-pin Debug Cable: Signal...

Table of Contents