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Related Manuals for Lauterbach XC800
Summary of Contents for Lauterbach XC800
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Page 1: Xc800 Debugger
XC800 Debugger Release 09.2021 MANUAL... -
Page 2: Table Of Contents
Brief Overview of Documents for New Users Warning ..........................Quick Start ......................... Troubleshooting ........................ SYStem.Up Errors FAQ ............................. Configuration ........................XC800 Specific Implementations ..................Breakpoints Software Breakpoints On-chip Breakpoints CPU specific SYStem Settings and Restrictions ............SYStem.state Open system window SYStem.CONFIG... - Page 3 TrOnchip Commands ......................TrOnchip.CONVert Adjust range breakpoint in on-chip resource TrOnchip.RESet Set on-chip trigger to default state TrOnchip.state Display on-chip trigger window TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource OCDS1 Connector ......................Memory Classes ........................ 1989-2021 © Lauterbach GmbH XC800 Debugger...
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Page 4: Introduction
(the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice. -
Page 5: Warning
Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 6: Quick Start
A detailed description of the Data.LOAD command and all available options is given in the “General Commands Reference”. 1989-2021 © Lauterbach GmbH XC800 Debugger... - Page 7 ; Load the application, verify the ; process Go main ; Run and break at main() Data.List ; Open source window Register.view /SpotLight ; Open register window Var.Local ; Open window with local variables 1989-2021 © Lauterbach GmbH XC800 Debugger...
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Page 8: Troubleshooting
Use the SYStem.CONFIG command to specify the position of the device in the JTAG-chain. • There are additional loads or capacities on the JTAG lines. Please refer to our Frequently Asked Questions page on the Lauterbach website. 1989-2021 © Lauterbach GmbH... -
Page 9: Configuration
Target Debug Cable POWER DEBUG USB INTERFACE / USB 3 Cable POWER DEBUG INTERFACE / USB 3 The processor type must be selected by the SYStem.CPU command before issuing any other target related commands. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 10: Xc800 Specific Implementations
There is no restriction in the number of software breakpoints. On-chip Breakpoints The resources for the on-chip breakpoints are provided by the CPU. The following list gives an overview of the on-chip breakpoints for the XC800: • On-chip breakpoints: Total amount of available on-chip breakpoints. -
Page 11: Cpu Specific System Settings And Restrictions
The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisy-chain Example. For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the required system configuration of these CPUs is known. 1989-2021 © Lauterbach GmbH XC800 Debugger... - Page 12 (default: 7 = Select-DR-Scan) This is the state of the TAP controller when the debugger switches to tristate mode. All states of the JTAG TAP controller are selectable. TCKLevel (default: 0) Level of TCK signal when all debuggers are tristated. 1989-2021 © Lauterbach GmbH XC800 Debugger...
- Page 13 (default: OFF) If more than one debugger share the same debug port, all except one must have this option active. JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). 1989-2021 © Lauterbach GmbH XC800 Debugger...
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Page 14: Daisy-Chain Example
SYStem.CONFIG.IRPOST 8. ; IR Core A + B SYStem.CONFIG.DRPRE ; DR Core D SYStem.CONFIG.DRPOST 2. ; DR Core A + B SYStem.CONFIG.CORE 0. 1. ; Target Core C is Core 0 in Chip 1 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 15: Tapstates
TapStates Exit2-DR Exit1-DR Shift-DR Pause-DR Select-IR-Scan Update-DR Capture-DR Select-DR-Scan Exit2-IR Exit1-IR Shift-IR Pause-IR Run-Test/Idle Update-IR Capture-IR Test-Logic-Reset 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 16: System.config.core Assign Core To Trace32 Instance
GUI uses a new chip_index according to its CORE= parameter of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must be merged by calling SYStem.CONFIG.CORE. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 17: System.config.state
XC866 | XC866L | XC886 | XC888 | XC886C | XC888C | XC886CM | XC888CM | XC886LM | XC888LM | XC886CLM | XC888CLM | XC878 | XC878M | XC878CM | XC878L | XC878C | TC2X_SCR | TLE9832 | TLE9834 Selects the processor type. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 18: System.memaccess
Temporarily halts the core(s) to perform the memory access. Each stop takes some time depending on the speed of the JTAG port, the number of the assigned cores, and the operations that should be performed. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 19: System.mode
Resets the target, sets the CPU to debug mode and stops the CPU. After the execution of this command the CPU is stopped and all register are set to defaults. StandBy Not supported. SYStem.LOCK Tristate the JTAG port Format: SYStem.LOCK [ON | OFF] Default: OFF. 1989-2021 © Lauterbach GmbH XC800 Debugger... - Page 20 If the system is locked, no access to the JTAG port will be performed by the debugger. While locked the JTAG connector of the debugger is tristated. The intention of the SYStem.LOCK command is, for example, to give JTAG access to another tool. 1989-2021 © Lauterbach GmbH XC800 Debugger...
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Page 21: System Options
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to SYStem.Option.LittleEndian Treat memory as little endian Format: SYStem.Option.LittleEndian [ON | OFF] Default: OFF. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 22: System.option.trapen
Extended Operation (EO) register before executing the next GO command. • The XC800 extends the 8051 instruction set with the special command MOVC @(DPTR++),A to write data (e.g. from a I2C LPC memory IC) into program RAM. As the 8051 instruction set is only 8 bit wide, and there were no unused opcodes available, the TRAP opcode 0A5h is re-used for this instruction. -
Page 23: System.jtagclock
Besides a decimal number like “100000.’” short forms like “10kHz” or “15MHz” can also be used. The short forms imply a decimal value, although no “.” is used. When the debugger is not working correctly (e.g. memory is flickering), decrease the JtagClock. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 24: Tronchip Commands
; gives an error message TrOnchip.RESet Set on-chip trigger to default state Format: TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. TrOnchip.state Display on-chip trigger window Format: TrOnchip.state Opens the TrOnchip.state window. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 25: Tronchip.varconvert Adjust Complex Breakpoint In On-Chip Resource
CPU may be not powerful enough to cover the whole structure. If the option TrOnchip.VarCONVert is set to ON, the breakpoint will automatically be converted into a single address breakpoint. This is the default setting. Otherwise an error message is generated. 1989-2021 © Lauterbach GmbH XC800 Debugger... -
Page 26: Ocds1 Connector
BRKIN and BRKOUT- must be configured in MCBS (Multi Core Break Switch) for before they can be used. • VIHmin = 2.0 V, VILmax = 0.8 V for the input pins TDO, BRKOUT-. For an example design please see the Infineon Evaluation Board schematics. 1989-2021 © Lauterbach GmbH XC800 Debugger... - Page 27 Connect to digital ground. Ground Plan Test Data In No other devices in the JTAG chain are allowed between the Debug Cable and the XC800. Reset Connect to /PORST and connect /PORST to RESET VCC via a 10 K pull-up resistor.
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Page 28: Memory Classes
128 bytes in the memory class D represent the Special Function Registers SFR (standard). The Special Function Registers (standard, mapped and paged) can be accessed in the peripherie window. XRAM can be read/written as program memory or external memory. 1989-2021 © Lauterbach GmbH XC800 Debugger...
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