Lauterbach TRACE32-ICD Manual
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Lauterbach TRACE32-ICD Manual

Starcore debugger and trace
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StarCore Debugger and Trace

Release 02.2022
MANUAL

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Summary of Contents for Lauterbach TRACE32-ICD

  • Page 1: Starcore Debugger And Trace

    StarCore Debugger and Trace Release 02.2022 MANUAL...

  • Page 2: Table Of Contents

    Sets the SUI base address SYStem.Option.DCFLUSH Data cache flush before step/run SYStem.Option.DTM Enables data trace messages SYStem.Option.EnReset Allow the debugger to drive nRESET/nSRST SYStem.Option.EnTrst Allow debugger to drive TRST SYStem.Option.HalfRate Enable Nexus DDR mode 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 3 Select mode to control trace buffer and contents Onchip.VTBA Set the destination address of the onchip trace General Restrictions ......................Floating Point Formats ..................... Integer Access Keywords ....................File I/O Support ........................Metrowerks MSLIO Support JTAG Connection ......................1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 4 Mechanical Description of the 20-pin Debug Cable Electrical Description of the 20-pin Debug Cable JTAG Connector 14-pin Memory Classes ........................ 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 5 StarCore Debugger and Trace Version 09-Mar-2022 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 6: Introduction

    (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.

  • Page 7: Warning

    Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 8: Quick Start

    Please consider that this is probably not the best configuration for your target. Set up data for electrical interface SYStem.JtagClock <frequency> Normally the default value is 1.0 MHz, but the it can be increased up to 80.0 MHz. SYStem.Option.EnReset SYStem.Option.EnTrst SYStem.Option.WaitReset 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 9 /Verify that verifies all written data. This test discovers a problem with the electrical connection, wrong chip configurations or linker command file settings. A detailed description of the Data.LOAD command and all available options is given in the “General Commands Reference”. 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 10 ; Load the application, verify the /VERFY ; process Go main ; Run and break at main() List.Mix ; Open source window Register.view /SpotLight ; Open register window Var.Local ; Open window with local variables 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 11: Troubleshooting

    The external bus is not released by the bus master. In this case it is possible to execute a SYStem.Mode.Attach command to attach to the core and wait until the bus becomes ready. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 12: Memory Access Errors

    D:XXXXXXXX bus error generated by CPU When a unrecoverable bus error occurs the target processor has to be reset. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 13: Nexus Flow Errors And Fifo Overflow Messages

    Flow Errors can be internal processing errors of the TRACE32 software. The analysis of the NEXUS message is not clear in some rare situations. If Flow Errors occur the LAUTERBACH support has to be contacted in order to fine tune to software to detect this situations.

  • Page 14: Faq

    Another way to prevent the FIFO from becoming full is stalling the core or suppressing less important trace data trace messages. The option SYStem.Option.OVC can be used to specify this behavior. Please refer to our Frequently Asked Questions page on the Lauterbach website. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 15: Configuration

    PODPAR Power Debug PODETH Interface Dongle Debug Cable JTAG Connector Basic configuration for the BDM Interface The processor type must be selected by the SYStem.CPU command before issuing any other target related commands. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 16: Cpu Specific System Settings And Restrictions

    Note that the command line provides additional SYStem.CONFIG commands for settings that are not included in the SYStem.CONFIG.state window. <tab> Opens the SYStem.CONFIG.state window on the specified tab. For tab descriptions, see below. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 17: System.config

    Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down resistor, other trigger inputs need to be kept in inactive state. Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701). 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 18 (default: OFF) If more than one debugger share the same debug port, all except one must have this option active. JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 19: Daisy-Chain Example

    SYStem.CONFIG.IRPOST 8. ; IR Core A + B SYStem.CONFIG.DRPRE ; DR Core D SYStem.CONFIG.DRPOST 2. ; DR Core A + B SYStem.CONFIG.CORE 0. 1. ; Target Core C is Core 0 in Chip 1 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 20: Tapstates

    TapStates Exit2-DR Exit1-DR Shift-DR Pause-DR Select-IR-Scan Update-DR Capture-DR Select-DR-Scan Exit2-IR Exit1-IR Shift-IR Pause-IR Run-Test/Idle Update-IR Capture-IR Test-Logic-Reset 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 21: System.config.core Assign Core To Trace32 Instance

    GUI uses a new chip_index according to its CORE= parameter of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must be merged by calling SYStem.CONFIG.CORE. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 22: System.cpu

    The main intention of the SYStem.LOCK command is to give debug access to another tool. SYStem.MemAccess Real-time memory access (non-intrusive) Format: SYStem.MemAccess Enable | NEXUS | Cerberus | Denied | StopAndGo 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 23 Temporarily halts the core(s) to perform the memory access. Each stop takes some time depending on the speed of the JTAG port, the number of the assigned cores, and the operations that should be performed. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 24: System.mode

    Resets the target, sets the CPU to debug mode and stops the CPU. After the execution of this command the CPU is stopped and all register are set to the default level. SYStem.Option.BASE Sets the SUI base address Format: SYStem.Option.BASE [AUTO | VALUE] Default: AUTO. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 25: System.option.dcflush

    From the view of the StarCore core it is not necessary that nRESET / nSRST becomes active at the start of a debug session (SYStem.Up), but there may be other logic on the target which requires a reset. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 26: System.option.entrst

    DDR NEXUS mode is active. Use System.Option.HalfRate ON if the bandwidth of the clock line is too small and to activate the DDR mode. If the option is set to ON the data and clock lines will need the same bandwidth. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 27: System.option.icflush

    If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 28: System.option.ipldi

    The option can be set when the chip has nexus trace support and defines the frequency of the nexus output clock based on the processor frequency. High frequencies can cause electrical connection problems during the record of trace messages. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 29: System.option.mpu

    Base address for OnCE registers Format: SYStem.Option.OCEBASE [AUTO | ADDRESS] Default: AUTO. Defines the base address for the memory mapped OnCE Register. Customer SOCs with addresses differing from 0x80000000 must set this option. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 30: System.option.ocecore

    Enables program trace messages Format: SYStem.Option.PTM [ON | OFF] Default: OFF. The option can be switched when the chip has nexus trace support. When PTM is ON, the chip will produce program trace messages. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 31: System.option.sample

    SYStem.Option.SLOWRESET Expand reset time for additional reset module Format: SYStem.Option.SLOWRESET [ON | OFF] Default: OFF. Defines that the debugger waits additional time for asserting the reset line through an additional reset controller. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 32: System.option.vba Set Up Vba Value For Analysis

    VBA address my be not up to date, therefore it is possible to use a fixed VBA address specified by this command. The option AUTO will force the debugger to use the last known value. If any address is set by this command then this address will be used. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 33: System.option.waitreset

    JTAG port is reset in normal operation. If the WaitReset option is disabled the debugger first de-asserts nTRST, then it executes a JTAG sequence to enter the debug mode and then it de-asserts nRESET/nSRST. nSRST nTRST reset debug CPU State 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 34: System.option.watchdog Enable Watchdog

    Therefore we recommend to use the default setting if possible. <frequency>: The debugger cannot select all frequencies accurately. It chooses the next possible frequency and displays the real value in the SYStem.state window. 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 35 ARM11) of the ARM core processor clock. For designs using a very low processor clock we offer a different mode (ARTCK) which does not work as recommended by ARM and might not work on all target systems. In 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 36 (Compensation by TCK). This feature can be used with a debug cable versions 3b or newer. If it is selected, although the debug cable is not suitable, a fix JTAG clock will be selected instead (minimum of 10 MHz and selected clock). 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 37 In contrast to the RTCK option, the TCK is always output with the selected, fixed frequency. The mode CRTCK can not be used if a debug cable with 14-pin flat cable (LA- 7834) is used. And it is required that the target provides an RTCK signal. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 38: Cpu Specific Mmu Commands

    Displays the contents of the Instruction Translation Lookaside Buffer. DTLB Displays the contents of the Data Translation Lookaside Buffer. MMU.List Compact display of MMU translation table Format: MMU.List This command shows the debugger-internal translation table. See TRANSlation.List. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 39: Mmu.scan Load Mmu Table From Cpu

    MMU.SCAN Load MMU table from CPU Format: MMU.SCAN Loads the CPU-specific MMU translation table from the CPU to the debugger-internal static translation table. This command is not supported. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 40: Benchmarkcounter

    BenchMarkCounter For information about architecture-independent BMC commands, refer to “BMC” (general_ref_b.pdf). 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 41: Tronchip

    The options TrOnchip.CONVert and TrOnchip.VarCONVert help to convert ranges to single addresses. Also the ECNT unit has only one input line so that data range address breakpoints cannot be counted. 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 42 If no component uses the counter then it will be used as cycle counter and is accessible by the CYCLO and CYCHI register of the register window. 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 43 OCE/EOnce status registers ESR and EMCR. The ESR register contains bits to show why the core entered debug mode. If there was no break indication bit true, the reason was probably a manual break coming from JTAG. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 44: Tronchip Control Of On-Chip Resources

    ; EDCA2_REFA: REFA = main D.S DBG:0x394 %LONG %LE main ; ESEL_CTRL: SELDM = OR D.S DBG:0x3E8 %LONG %LE 0x0 ; ESEL_DM: EDCA2 = ON D.S DBG:0x3EC %LONG %LE 0x4 ; go and break enddo 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 45: Tronchip.convert

    When enabled (default) the data address on-chip breakpoints are automatically converted from a range to a single address if required. If the switch is off, the system will only accept breakpoints which exactly fit to the on-chip breakpoint hardware. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 46: Tronchip.state Opens Configure Panel

    TrOnchip.state Opens configure panel Format: TrOnchip.state Control panel to configure the on-chip breakpoint and trace registers. The details are described in section TrOnchip. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 47: On-Chip Trace

    Leash mode or counting other events like breakpoints. To derive a timestamp from the clock cycles the options SYStem.Clock or OnChip.CLOCK need to be set to a correct value. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 48: Onchip.vtba Set The Destination Address Of The Onchip Trace

    The speed of post analysis is limited to the download speed of the target via JTAG. Higher JTAG frequencies will speed up the process as well as smaller trace buffer ranges. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 49: General Restrictions

    Make sure that the EE0 signal is high while reset in order to halt the core just after reset. “System.Option.WaitReset 0us” will also work, but the core will execute some instructions before it halts. 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 50: Floating Point Formats

    Word Word (16 bit) TByte Triple byte (24 bit) Long Double Word (32 bit), upper and lower word swapped HByte Hexabyte (48 bit) Quad Tertiary Word (64 bit), upper and lower word swapped 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 51: File I/O Support

    VLES is executed. To trigger the Terminal Protocol to the right Program Counter, just add 0x2 to the Term.Method MSLIO address: Break.Set __syscall /ONCHIP ; Sets on-chip breakpoint to __syscall ; function Term.Method MSLIO __syscall+0x2 ; Set MSLIO protocol activated by ; break point __syscall 1989-2022 © Lauterbach StarCore Debugger and Trace...

  • Page 52: Jtag Connection

    We strongly recommend to use a connector on your target with housing and having a center polarization (e.g. AMP: 2-827745-0). A connection the other way around indeed causes damage to the output driver of the debugger. 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 53 JTAG connector is tristated by the debugger and it is pulled low otherwise. This signal is normally not required, but can be used to detect the tristate state if more than one debug tools are connected to the same JTAG port. 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 54 Test Clock Add 10 k pull-up resistor to VCC. 7, 13, No Connect Leave unconnected. Mechanical Pin should be removed. Keying /RESET Reset May be tied to HRESET. Test Mode None. Select 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 55 When using more than one debug dongle driving this signal it is not recommended to pull down the signal in debug mode, because during the dongle source switch the signal output is set to tristate. 1989-2022 © Lauterbach StarCore Debugger and Trace...
  • Page 56 MMU settings. Example Address Description UD:0x0 References to logical user data memory at 0x0. AD:0x1000 References to absolute physical address data memory at 0x1000. SP:0x2000 References to logical supervisor program memory at 0x2000. 1989-2022 © Lauterbach StarCore Debugger and Trace...

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