Lauterbach TRACE32-ICD Manual
  1. Manuals
  2. Brands
  3. Lauterbach Manuals
  4. Computer Accessories
  5. TRACE32-ICD
  6. Manual

Lauterbach TRACE32-ICD Manual

Pqiii debugger
Hide thumbs Also See for TRACE32-ICD:
Table of Contents

Advertisement

Quick Links

Download this manual

PQIII Debugger

TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
PQIII ..........................................................................................................................................
PQIII Debugger .....................................................................................................................
Introduction .......................................................................................................................
Warning ..............................................................................................................................
Target Design Requirement/Recommendations ............................................................
Quick Start .........................................................................................................................
Troubleshooting ................................................................................................................
FAQ .....................................................................................................................................
Configuration .....................................................................................................................
PowerPC MPC85XX specific Implementations ...............................................................
PQIII Debugger
©1989-2020 Lauterbach GmbH
1
1
4
4
5
6
6
7
8
8
9
10
10
11
11
11
11
12
12
13
13
15
15
16
17
18
18
19
20

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the TRACE32-ICD and is the answer not in the manual?

Questions and answers

Related Manuals for Lauterbach TRACE32-ICD

Summary of Contents for Lauterbach TRACE32-ICD

  • Page 1: Table Of Contents

    Breakpoints on Data Access at Program Address Breakpoints on Data Value Access Classes Access Classes to Memory and Memory Mapped Resources Access Classes to Other Addressable Core and Peripheral Resources Memory Classes Cache Memory Coherency MESI States Debugging Information ©1989-2020 Lauterbach GmbH PQIII Debugger...
  • Page 2 Set behavior when target reset detected SYStem.Option.STEPSOFT Use alternative method for ASM single step SYStem.Option.SLOWRESET Relaxed reset timing CPU specific MMU Commands ..................MMU.DUMP Page wise display of MMU translation table MMU.List Compact display of MMU translation table ©1989-2020 Lauterbach GmbH PQIII Debugger...
  • Page 3 Select interface to be traced CPU specific TrBus Commands ..................TrBus.Out Define source for the external trigger pulse TrBus.Set Define the target for the incoming trigger JTAG Connector ........................ Mechanical Description JTAG Connector MPC85XX (COP) ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 4: Introduction

    (the document you are reading at the moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your first choice.

  • Page 5: Warning

    Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the debug cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 6: Target Design Requirement/Recommendations

    The T32 internal buffer/level shifter will be supplied via the VCCS pin. with blue Therefore it is necessary to reduce the VCCS pull-up on the target board to a value smaller 10 . ribbon cable ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 7: Quick Start

    (ELF specifies the format, demo.elf is the file name) The option of the Data.LOAD command depends on the file format generated by the compiler. A detailed description of the Data.LOAD command is given in the “General Commands Reference”. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 8: Troubleshooting

    SYStem.Option.SLOWRESET, and check signal level of the JTAG HRESET pin. • The target reset is permanently asserted. Check target reset circuitry and reset pull-up • A chip external watchdog caused a reset after the debugger asserted reset. Disable the watchdog and try again. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 9: Faq

    If the bootstrap configuration was found to be wrong or needs to be changed temporarily (e.g. for NAND programming), it is possible to override the bootstrap configuration setting through JTAG. For instructions again please contact support using above email address. Please refer to our Frequently Asked Questions page on the Lauterbach website. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 10: Configuration

    System Overview PODBUS Cable PODPC PODPAR Debug EPROM PODETH Interface Simulator (optional) Debug Cable   CPU CLK RESET  Target Connector (600 EPROM only)  Target TS4 (400 only) Basic configuration for the BDM Interface ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 11: Powerpc Mpc85Xx Specific Implementations

    1 breakpoint ranges range You can check your currently set breakpoints with the command Break.List. If no more on-chip breakpoints are available you will get an error message on trying to set a new on-chip breakpoint. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 12: Breakpoints On Program Addresses

    Equal to program address breakpoints, data address breakpoints can be configured to stop if the break event occurred a given number of times: ;stop on the 8th write to arrayindex Break.Set arrayindex /Write /COUNT 20. Data address breakpoint limitations: ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 13: Breakpoints On Data Access At Program Address

    If the value matches, the debugger will stop execution, if it does not match, the debugger will restart the application. Using software emulated data value breakpoints will cause the target application to slow down. ©1989-2020 Lauterbach GmbH PQIII Debugger...
  • Page 14 ;Break when a value not equal 0x98 is written to the 8-bit variable xval Break.Set xval /Write /Data.Byte !0x98 ;Break when decimal 32-bit value 4000 is written ;to variable countwithin function foo Break.Set sYmbol.RANGE(foo) /MemoryWrite count /Data.Long 4000. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 15: Access Classes

    In addition to the access classes, there are access class attributes: Examples: Command: Effect: Data.List SP:0x1000 Opens a List window displaying supervisor program memory ED:0x3330 0x4F Write 0x4F to address 0x3330 using real-time memory access ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 16: Access Classes To Other Addressable Core And Peripheral Resources

    Access Classes to Other Addressable Core and Peripheral Resources The following access classes are used to access registers which are not mapped into the processor’s memory address space. Access Class Description Special Purpose Register (SPR) access Performance Monitor Register (PMR) access ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 17: Memory Classes

    TS (translation space) == 0 (supervisor memory) Memory class attributes can also be used without a memory class, but U: and S: are usually combined with D: and P: (UD: user data, SD: supervisor data, UP: user program, UD: user data). ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 18: Cache

    (*) Depending on the debugger configuration, the coherency of the instruction cache will not be achieved by updating the instruction cache, but by invalidating the instruction cache. See “SYStem.Option ICFLUSH Invalidate instruction cache before go/step” (ppce.pdf) for details. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 19: Mesi States

    The Cache logic of PPC e500 cores is described as MESI states. The debugger however displays the cache state using valid/dirty/shared flags according to the following table. State translation table: MESI state Flag M (modified) V(alid) && D(irty) E (exclusive) V(alid) && NOT D(irty) S (shared) S(hared) I (invalid) NOT V(alid) ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 20: Debugging Information

    Data.LOAD.Elf demo.elf /NoCODE Break ; with this command ; z0 will stop when ; reset is released ; start z1 WAIT !RUN() ; wait until cpu stops ; application will start z0 ; core Break.Set somez0function ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 21: Multicore Debugging E500 Cores

    AMP mode, or always if SMP mode is selected, the core that did not hit a breakpoint will be stopped by the debugger. The missing hardware implementation on the processor causes a delay between both cores typically in the 1..10 millisecond range. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 22: Programming Flash On Mpc85Xx / Qoriq P10Xx/P20Xx, Psc93Xx

    ID and the byte count. The interface can be selected with the command Onchip.Mode.IFSel. All other configurations can be done directly via the menu for CPU peripherals in the section “Debug Features and Watchpoint Facility”. ©1989-2020 Lauterbach GmbH PQIII Debugger...
  • Page 23 Also data trace is limited to uncached accesses. The data value of the load/store access is not contained in the trace data. For more information about general trace commands see ’Trace’ in ’General Commands Reference Guide T’ ’Onchip Trace Commands’ in ’General Commands Reference Guide O’. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 24: General System Commands

    SYStem.CONFIG.state window. <tab> Opens the SYStem.CONFIG.state window on the specified tab. For tab descriptions, see below. DebugPort Lets you configure the electrical properties of the debug connection, such as the communication protocol or the used pinout. ©1989-2020 Lauterbach GmbH PQIII Debugger...
  • Page 25 Informs the debugger about the position of the Test Access Ports (TAP) in the JTAG chain which the debugger needs to talk to in order to access the debug and trace facilities on the chip. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 26: System.config

    NOTE: When using the TriState mode, nTRST/JCOMP must have a pull-up resistor on the target. In TriState mode, a pull-down is recommended for TCK, but targets with pullup are also supported. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 27: Example

    The data register length per device is typically 1 bit. SYStem.CPU P2020 ; select processor SYStem.CONFIG IRPRE 6. ; IR Device_D SYStem.CONFIG IRPOST 8. ; IR Device_A + Device_B SYStem.CONFIG DRPRE 1. ; DR Device_D SYStem.CONFIG DRPOST 2. ; DR Device_A + Device_B SYStem.Up ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 28: System.config.chkstpin

    Exit1-IR Shift-IR Pause-IR Run-Test/Idle Update-IR Capture-IR Test-Logic-Reset SYStem.CONFIG.CHKSTPIN Control pin 8 of debug connector Format: SYStem.CONFIG CHKSTPIN LOW | HIIGH Default: HIGH. Controls the level of pin 8 (/CHKSTP_IN or /PRESENT) of the debug connector. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 29: System.config.driverstrength

    Controls the level and function of pin 2 (/QACK) of the debug connector. Default: TRISTATE. TRISTATE Pin is disabled (tristate). QREQ Pin is driven to level of QREQ (pin 5). Pin is driven to GND permanently. HIGH Pin is driven to JTAG_VREF permanently. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 30: System.cpu

    CPUs that appeared later than the software release are usually not supported. Please check www.lauterbach.com for updates. If the needed CPU appeared after the release date of the debugger software, please contact technical support and request a software update.

  • Page 31: System.cpuaccess

    If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the SYStem.LOCK command is to give debug access to another tool. The command has no effect for the simulator. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 32: System.memaccess

    This option is available for both the NEXUS and JTAG-only debugger solution. Memory accesses via the NEXUS block can not snoop caches. Data in cache can not be modified with this access. If the cache operates in copy-back mode, reading cached data is also not possible. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 33: System.mode

    CPU at the first instruction at the reset address. Resets the target and sets the CPU to debug mode. After execution of this command the CPU is stopped and prepared for debugging. All register are set to the default value. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 34: Cpu Specific System Commands

    This option has impact on the real-time behavior. Releasing a secondary core from reset / disable state will be delayed for a few milliseconds. SYStem.Option DCFREEZE Prevent data cache line load/flush in debug mode Format: SYStem.Option DCFREEZE [ON | OFF] Default: OFF. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 35: System.option Dcread

    Please note that while the CPU is running, MMU address translation can not be accesses by the debugger. Only physical addresses accesses are possible. Use the memory class modifier “A:” to declare the access physical addressed, Or declare the address translation in the debugger-based MMU manually using MMU.CREATE. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 36: System.option Freeze

    Default: ON. Invalidates the instruction cache before starting the target program (Step or Go). If this option is disabled, the debugger will update Memory and instruction cache for program memory downloads, modifications and breakpoints. Disabling this option might cause performance decrease on memory accesses. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 37: System.option Icread

    MSR_EE while the CPU is running and restore it after the CPU stopped. If a part of the application is executed that disables MSE_EE, the debugger can not detect this change and will restore MSE_EE. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 38: System.option Mmuspaces

    Enable this option if the CPU should not stop for JTAG on debug events, in order to allow a target application to use the debug interrupt. Typical usages for this option are run-mode debugging (e.g. with t32server/gdbserver) or setting up the system for a branch trace via LOGGER (trace data in target RAM) or INTEGRATOR. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 39: System.option Overlay

    The data buffers of TSEC etc. can overflow, because the target application does not process the data when stopped. NOTE: If SYStem.Option.PERSTOP is disabled, it is recommended to also disable SYStem.Option.DCFREEZE, in order to see the memory accesses performed by the peripherals. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 40: System.option Resetbehavior

    JTAG_HRESET, but instead waits 4 s and then assumes that the boards HRESET is released. SYStem.Option.SLOWRESET Relaxed reset timing Format: SYStem.Option SLOWRESET [ON | OFF] This method uses software breakpoints to perform an assembler single step instead of the processor’s builtin ©1989-2020 Lauterbach GmbH PQIII Debugger...
  • Page 41 Works only for software in RAM. Do not turn ON, unless advised by Lauterbach. NOTE: All CPUs: servicing watchdog If the debugger is servicing the watchdog, conditions might occur, where the watchdog times out before the debugger is able to service it. Unintended resets or interrupts can occur.

  • Page 42: Cpu Specific Mmu Commands

    Displays the entries of an MMU translation table. • if <range> or <address> have a space ID: displays the translation table of the specified process • else, this command displays the table the CPU currently uses for MMU translation. ©1989-2020 Lauterbach GmbH PQIII Debugger...
  • Page 43 For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. CPU specific tables: TLB0 Displays the contents of TLB0. TLB1 Displays the contents of TLB1. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 44: Mmu.list

    This command reads the table of the specified process, <space_id>:0x0 and lists its address translation. • For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 45: Mmu.scan

    This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debugger- internal static translation table. See also the appropriate OS Awareness Manual. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 46: Mmu.set

    MAS7 contains the most significant bits of the physical 36 bit address (e500v2 cores only) Sets the specified MMU TLB table entry in the CPU. The parameter <tlb> is not available for CPUs with only one TLB table. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 47: Cpu Specific Tronchip Commands

    TrOnchip.CONVert ON Break.Set 0x6020++0x1f Break.Set 0x7400++0x3f Data.View 0x6020 Data.View 0x7400 TrOnchip.RESet Reset on-chip trigger settings Format: TrOnchip.RESet Resets the on-chip trigger system to the default state. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 48: Tronchip.set

    SPEU (break on SPE APU unavailable interrupt) SPED (break on SPE floating-point data interrupt) SPER (break on SPE floating-point round interrupt) PM (break on performance monitor interrupt) Enables the specified on-chip trigger facility to stop the CPU on several events. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 49: Tronchip.varconvert

    An error message is displayed when the user wants to set a new data address breakpoint after all on-chip breakpoints are spent by a data address breakpoint to an HLL variable. TrOnchip.CONVert ON Var.Break.Set flags Var.Break.Set ast Data.View flags Data.View ast ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 50: Tronchip.view View On-Chip Trigger Setup Window

    TrOnchip.view View on-chip trigger setup window Format: TrOnchip.view Display the trigger setup dialog window. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 51: Mpc85Xx Specific Onchip Trace Settings

    NOTE: When a watchpoint is set via a Break.Set command, the NEXUS.WTM setting will be internally overridden. For not CPU-specific keywords, see non-declarable input variables “ICE/FIRE Analyzer Trigger Unit Programming Guide” (analyzer_prog.pdf). • • ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 52: Cpu Specific Trbus Commands

    Generate a trigger for the trace when the external trigger signal becomes active. A trigger for the trace can be used to stop the sampling to the trace buffer directly or after a specified delay Analyzer.TDelay. ©1989-2020 Lauterbach GmbH PQIII Debugger...

  • Page 53: Jtag Connector

    This is a standard 16 pin double row (two rows of eight pins) connector (pin-to-pin spacing: 0.100 in.). (Signals in brackets are not strong necessary for basic debugging, but its recommended to take in consideration for future designs.) ©1989-2020 Lauterbach GmbH PQIII Debugger...

Table of Contents