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Lauterbach C6000 Manual

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C6000 Debugger

Release 09.2022
MANUAL

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Summary of Contents for Lauterbach C6000

  • Page 1: C6000 Debugger

    C6000 Debugger Release 09.2022 MANUAL...

  • Page 2: Table Of Contents

    TRACE32 Documents ........................ ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... TI DSPs ............................. C6000 Debugger ........................Brief Overview of Documents for New Users ..............Converter from GEL to PRACTICE .................. Warning ..........................DSP specific Implementations ..................Trigger Breakpoints...
  • Page 3 Trace Breakpoints JTAG Connection ......................Mechanical Description of the 20-pin Debug Cable Electrical Description of the 20-pin Debug Cable Mechanical Description of the TI Connector Electrical Description of the TI Connector FAQ ............................. Operation Voltage ......................1989-2022 © Lauterbach C6000 Debugger...

  • Page 4: Brief Overview Of Documents For New Users

    C6000 Debugger Version 26-Oct-2022 Brief Overview of Documents for New Users Architecture-independent information: • “Training - Debugger Basics” (training_debugger.pdf): Get familiar with the basic features of a TRACE32 debugger. • “T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger.

  • Page 5: Warning

    Switch the target power ON. Configure your debugger e.g. via a start-up script. Power down: Switch off the target power. Disconnect the Debug Cable from the target. Close the TRACE32 software. Power OFF the TRACE32 hardware. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 6: Dsp Specific Implementations

    On-chip Breakpoints for Data To stop the CPU after a read or write access to a memory location on-chip breakpoints are required. In the DSP notation these breakpoints are called watch points (WP). 1989-2022 © Lauterbach C6000 Debugger...
  • Page 7 — — C64x up to 4 up to 4 single — — address C67x 1 single address — — C674x up to 4 single 1 single — C64x+ address address or range as bit mask 1989-2022 © Lauterbach C6000 Debugger...

  • Page 8: Memory Classes

    To access a memory class, write the class in front of the address. Prepending an E as attribute to the memory class will make memory accesses possible, even when the target CPU is running. See SYStem.MemAccess SYStem.CpuAccess for more information. Examples: Data.dump D:0--0xff Data.dump ED:80000 Data.List EP:main 1989-2022 © Lauterbach C6000 Debugger...

  • Page 9: Dsp Specific System Commands

    Level Test Access Port. The debugger might need to control it in order to reconfigure the JTAG chain or to control power, clock, reset, and security of different chip components. For descriptions of the commands on the MultiTap tab, see MultiTap. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 10: System.config

    SWDPTargetSel <value> TriState [ON | OFF] <parameter>: DAPDRPOST <bits> DAPDRPRE <bits> (JTAG cont.) DAPIRPOST <bits> DAPIRPRE <bits> DRPOST <bits> DRPRE <bits> ETBDRPOST <bits> (C5000 only) ETBDRPRE <bits> (C5000 only) ETBIRPOST<bits> (C5000 only) ETBIRPRE <bits> (C5000 only) 1989-2022 © Lauterbach C6000 Debugger...
  • Page 11 APBAPn.XtorName <name> AXIAPn.ACEEnable [ON | OFF] AXIAPn.Base <address> AXIAPn.CacheFlags <value> AXIAPn.HPROT [<value> | <name>] AXIAPn.Port <port> AXIAPn.RESet AXIAPn.view AXIAPn.XtorName <name> DEBUGAPn.Port <port> DEBUGAPn.RESet DEBUGAPn.view DEBUGAPn.XtorName <name> JTAGAPn.Base <address> JTAGAPn.Port <port> JTAGAPn.CorePort <port> JTAGAPn.RESet JTAGAPn.view JTAGAPn.XtorName <name> 1989-2022 © Lauterbach C6000 Debugger...
  • Page 12 MEMORYAPn.view MEMORYAPn.XtorName <name> <parameter>: ADTF.Base <address> ADTF.RESet COmponents ADTF.Type [NONE | ADTF | ADTF2 | GEM] ADTF.view AET.Base <address> (C5000, C6000, C7000 only) AET.RESet (C5000, C6000, C7000 only) AET.view (C5000, C6000, C7000 only) <parameter>: CMI.Base <address> (COmponents CMI.RESet cont.) CMI.TraceID <id>...
  • Page 13 TBR.Base <address> TBR.Name <string> TBR.NoFlush [ON | OFF] TBR.RESet TBR.STackMode [NotAvailbale | TRGETM | FULLTIDRM | NOTSET | FULL- STOP | FULLCTI] TBR.view TPIU.ATBSource <source> TPIU.Base <address> TPIU.Name <string> TPIU.RESet TPIU.Type [CoreSight | Generic] TPIU.view 1989-2022 © Lauterbach C6000 Debugger...
  • Page 14 TRACETPIUFUNNELPORT <port> view AHBACCESSPORT <port> APBACCESSPORT <port> AXIACCESSPORT <port> COREJTAGPORT <port> DEBUGACCESSPORT <port> JTAGACCESSPORT <port> MEMORYACCESSPORT <port> The SYStem.CONFIG commands inform the debugger about the available on-chip debug and trace components and how to access them. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 15 This is a common description of the SYStem.CONFIG command group for the TI C2000, C5000, C6000 and C7000 DSPs. Each debugger will provide only a subset of these commands. Some commands need a certain CPU type selection (SYStem.CPU <type>) to become active and it might additionally depend on further settings.

  • Page 16: Parameters> Describing The "Debugport

    But sometimes it is a must to tell the debugger that these cores share resources on the same <chip>. Whereby the “chip” does not need to be identical with the device on your target board: debugger#1: <core>=1 <chip>=1 debugger#2: <core>=2 <chip>=1 1989-2022 © Lauterbach C6000 Debugger...
  • Page 17 JTAG: Only one debugger - the “master” - is allowed to control the signals nTRST and nSRST (nRESET). The other debuggers need to have the setting Slave ON. Default: OFF. Default: ON if CORE=... >1 in the configuration file (e.g. config.t32). 1989-2022 © Lauterbach C6000 Debugger...
  • Page 18 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 19: Parameters> Describing The "Jtag" Scan Chain And Signal Behavior

    TDO signal. See possible TAP types and example below. Default: 0. NOTE: If you are not sure about your settings concerning IRPRE, IRPOST, DRPRE, and DRPOST, you can try to detect the settings automatically with the SYStem.DETECT.DaisyChain command. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 20 Please note: • nTRST must have a pull-up resistor on the target. • TCK can have a pull-up or pull-down resistor. • Other trigger inputs need to be kept in inactive state. Default: OFF. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 21 Example: ARM11 TAP ETB TAP OfNoInterest TAP DAP TAP IR: 5bit IR: 4bit IR: 7bit IR: 4bit SYStem.CONFIG IRPRE 15. SYStem.CONFIG DRPRE SYStem.CONFIG DAPIRPOST 16. SYStem.CONFIG DAPDRPOST SYStem.CONFIG ETBIRPOST SYStem.CONFIG ETBDRPOST SYStem.CONFIG ETBIRPRE SYStem.CONFIG ETBDRPRE 1989-2022 © Lauterbach C6000 Debugger...
  • Page 22 1989-2022 © Lauterbach C6000 Debugger...

  • Page 23: Parameters> Describing A System Level Tap "Multitap

    Used if MULTITAP=Icepickx. DEBUGTAP <tap> Specifies the TAP number which needs to be activated to get the core TAP in the JTAG chain. E.g. ARM11 TAP if you intend to debug an ARM11. Used if MULTITAP=Icepickx. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 24 Number of a Non-JTAG Control Register (NJCR) which shall be used by the debugger. Used if MULTITAP=Icepickx. SLAVETAP <tap> Specifies the TAP number to get the Icepick of the sub-system in the JTAG scan chain. Used if MULTITAP=IcepickXY (two Icepicks). 1989-2022 © Lauterbach C6000 Debugger...

  • Page 25: Parameters> Configuring A Coresight Debug Access Port "Ap

    “Port” or “Base” (with “DP:” access) in case XtorName remains empty. Example 1: SoC-400 SoC-400 ROM table Memory Access Port CoreSight (MEM-AP) Component Debug ROM table Memory Port Access Port (DP) (MEM-AP) CoreSight Component JTAG Access Port (JTAG-AP) 1989-2022 © Lauterbach C6000 Debugger...
  • Page 26 MEMORYAPn.HPROT Default: 0. [<value> | <name>] This option selects the value used for the HPROT bits in the Control Status Word (CSW) of a CoreSight Memory Access Port, when using the E: memory class. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 27 =0x06: Domain=0x0, Cache=0x6 ReadAllocateInnerShareable =0x16: Domain=0x1, Cache=0x6 ReadAllocateOuterShareable =0x26: Domain=0x2, Cache=0x6 WriteAllocateNonShareable =0x0A: Domain=0x0, Cache=0xA WriteAllocateInnerShareable =0x1A: Domain=0x1, Cache=0xA WriteAllocateOuterShareable =0x2A: Domain=0x2, Cache=0xA ReadWriteAllocateNonShareable =0x0E: Domain=0x0, Cache=0xE ReadWriteAllocateInnerShareable =0x1E: Domain=0x1, Cache=0xE ReadWriteAllocateOuterShareable =0x2E: Domain=0x2, Cache=0xE 1989-2022 © Lauterbach C6000 Debugger...
  • Page 28 ..RESet Undo the configuration for this access port. This does not cause a physical reset for the access port on the chip..view Opens a window showing the current configuration of the access port. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 29 AP access port number (0-255) of a SoC-400 system where MEMORYACCESSPORT system memory can be accessed even during runtime (typically <port> (deprecated) an AHB). Used for “E:” access class while running, assuming “SYStem.MemAccess DAP”. Default: <port>=0. SoC-600 Specific Commands 1989-2022 © Lauterbach C6000 Debugger...
  • Page 30 Example: SYStem.CONFIG.JTAGAP1.Base DP:0x80005000 Meaning: The control register block of the JTAG access ports starts at address 0x80005000. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 31: Parameters> Describing Debug And Trace "Components

    If you press the button with the three dots you get the corresponding command in the command line where you can view and maybe copy it into a script file. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 32 FUNNEL TPIU SYStem.CONFIG.COREDEBUG.Base 0x80010000 0x80012000 SYStem.CONFIG.BMC.Base 0x80011000 0x80013000 SYStem.CONFIG.ETM.Base 0x8001c000 0x8001d000 SYStem.CONFIG.STM1.Base EAHB:0x20008000 SYStem.CONFIG.STM1.Type ARM SYStem.CONFIG.STM1.Mode STPv2 SYStem.CONFIG.FUNNEL1.Base 0x80004000 SYStem.CONFIG.FUNNEL2.Base 0x80005000 SYStem.CONFIG.TPIU.Base 0x80003000 SYStem.CONFIG.FUNNEL1.ATBSource ETM.0 0 ETM.1 1 SYStem.CONFIG.FUNNEL2.ATBSource FUNNEL1 0 STM1 7 SYStem.CONFIG.TPIU.ATBSource FUNNEL2 1989-2022 © Lauterbach C6000 Debugger...
  • Page 33 HTM on port 1 and from STM on port 7. In an SMP (Symmetric MultiProcessing) debug session where you used a list of base addresses to specify one component per core you need to indicate which component in the list is meant: 1989-2022 © Lauterbach C6000 Debugger...
  • Page 34 ETM, ETR a list of base addresses to specify one component per core. Example assuming four cores: SYStem.CONFIG COREDEBUG.Base 0x80001000 0x80003000 0x80005000 0x80007000 For a list of possible components including a short description Components and Available Commands. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 35 ID (ETM.TraceID <id>). The default setting is typically fine because the debugger uses different default trace IDs for different components. For a list of possible components including a short description Components and Available Commands. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 36 It is possible that different funnels have the same address for their control register block. This assumes they are on different buses and for different cores. In this case it is needed to give the funnel different names to differentiate them. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 37 See the description of the commands above. Please note that there is a common description for ..ATBSource, ..Base, , ..RESet, ..TraceID. ADTF.Base <address> ADTF.RESet ADTF.Type [None | ADTF | ADTF2 | GEM] 1989-2022 © Lauterbach C6000 Debugger...
  • Page 38 REPlicatorB can be used from other ATB sinks to connect to output A or B to the Replicator. OCP.Base <address> OCP.RESet OCP.TraceID <id> OCP.Type <type> Open Core Protocol watchpoint unit (OCP) - Texas Instruments Trace source module delivering bus trace information to a system trace module. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 39 Trace source delivering system trace information e.g. sent by software in printf() style. TPIU.ATBSource <source> TPIU.Base <address> TPIU.RESet TPIU.Type [CoreSight | Generic] Trace Port Interface Unit (TPIU) - ARM CoreSight module Trace sink sending the trace off-chip on a parallel trace port (chip pins). 1989-2022 © Lauterbach C6000 Debugger...

  • Page 40: Parameters> Which Are "Deprecated

    RAM which accesses shall be traced. The trace packages include only relative addresses to PERBASE and RAMBASE. For a list of possible components including a short description Components and Available Commands. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 41 QV1: This mode is not yet used. TIOCPTYPE <type> Specifies the type of the OCP module from Texas Instruments (TI). view Opens a window showing most of the SYStem.CONFIG settings and allows to modify them. 1989-2022 © Lauterbach C6000 Debugger...
  • Page 42 ETMFUNNELPORT <port> FUNNEL1.ATBSource ETM <port> (1) ETMTPIUFUNNELPORT <port> FUNNEL3.ATBSource ETM <port> (1) FILLDRZERO [ON | OFF] CHIPDRPRE 0 CHIPDRPOST 0 CHIPDRLENGTH <bits_of_complete_dr_path> CHIPDRPATTERN.Alternate 0 FUNNEL2BASE <address> FUNNEL2.Base <address> FUNNELBASE <address> FUNNEL1.Base <address> HSMBASE <address> HSM.Base <address> 1989-2022 © Lauterbach C6000 Debugger...
  • Page 43 OCP.Base <address> TIOCPTYPE <type> OCP.Type <type> TIPMIBASE <address> PMI.Base <address> TISCBASE <address> SC.Base <address> TISTMBASE <address> STM1.Base <address> STM1.Mode STP STM1.Type TI TPIUBASE <address> TPIU.Base <address> TPIUFUNNELBASE <address> FUNNEL3.Base <address> TRACEETBFUNNELPORT <port> FUNNEL4.ATBSource ADTF <port> (1) 1989-2022 © Lauterbach C6000 Debugger...

  • Page 44: System.cpu

    Select the used CPU Format: SYStem.CPU <cpu> <cpu>: C64X | C6416 | C6455 | C6713 | … Default selection: C64X. Selects the processor type. If your ASIC is not listed, select the type of the integrated DSP core. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 45: System.jtagclock

    (ARM7, ARM9), below 1/8 of the processor clock (ARM11), respectively. When RTCK is selected, the frequency depends on the processor clock and on the propagation delays. The maximum reachable frequency is about 16 MHz. SYStem.JtagClock RTCK 1989-2022 © Lauterbach C6000 Debugger...

  • Page 46: System.lock

    SYStem.CONFIG TCKLevel must be set properly. They define the TAP state and TCK level which is selected when the debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 47: System.memaccess

    The run-time memory access has to be activated for each window by using the memory class E: (e.g. Data.Dump ED:0x800000) or by using the format option %E (e.g. Var.View %E var1). NOTE: SYStem.MemAccess Enable is only selectable on cores of C64x and C64x+ series since the hardware has to support this feature. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 48: System.mode

    Resets the target via the reset line, initializes the debug port (JTAG, SWD, cJTAG), and starts the program execution. For a reset, the reset line has to be connected to the debug connector. Program execution can, for example, be stopped by the Break command. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 49: System.option.ahbhprot

    Select AHB-AP HPROT bits Format: SYStem.Option.AHBHPROT <value> (deprecated) SYStem.CONFIG.AHBAPn.HPROT instead. Default: 0 Selects the value used for the HPROT bits in the Control Status Word (CSW) of a CoreSight AHB Access Port, when using the AHB: memory class. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 50: System.option.axiaceenable

    SYStem.Option.AXIHPROT <value> (deprecated) SYStem.CONFIG.AXIAPn.HPROT instead. Default: 0 This option selects the value used for the HPROT bits in the Control Status Word (CSW) of a CoreSight AXI Access Port, when using the AXI: memory class. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 51: System.option.bigendian

    The Debug Access Port (DAP) can be used for memory access during runtime. If the mapping on the DAP is different than the processor view, then this re-mapping command can be used NOTE: Up to 16 <address_range>/<address> pairs are possible. Each pair has to contain an address range followed by a single address. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 52: System.option.debugportoptions

    Use nTRST the same way as in JTAG mode which is typically a low-pulse on debugger start-up followed by keeping it high. Keep nTRST low during serial wire operation. HIGH Keep nTRST high during serial wire operation 1989-2022 © Lauterbach C6000 Debugger...

  • Page 53: System.option.imaskasm Disable Interrupts While Single Stepping

    If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 54: System.option.dapdbgpwrupreq

    GUIs because they cannot access the debug interface anymore. To keep the debug interface active, it is recommended that SYStem.Option.DAPDBGPWRUPREQ is set to AlwaysON. SYStem.Option.DAPSYSPWRUPREQ Force system power in DAP Format: SYStem.Option.DAPSYSPWRUPREQ [AlwaysON | ON | OFF] Default: ON. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 55: System.option.dualport

    From the view of the core, it is not necessary that nRESET (nSRST) becomes active at the start of a debug session (SYStem.Up), but there may be other logic on the target which requires a reset. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 56: System.option.entrst

    If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 57: System.option.intdis

    If possible (nRESET is open collector), this command asserts the nRESET line on the debug connector. This will reset the target including the CPU but not the debug port. The function only works when the system is in SYStem.Mode.Up. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 58: C64X+ Specific System Commands

    This option doubles the download rate. In case the user application uses the same DMA resource, the transfer will not work. Therefore we recommend to use that option for downloading data after reset at the beginning of a debug session, only. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 59: Cpu Specific Benchmarkcounter Commands

    ; set a marker Alpha to the entry ; of the function sieve Break.Set V.END(sieve)-1 /Beta ; set a marker Beta to the exit ; of the function sieve BMC.<counter>.ATOB ON ; advise <counter> to count only ; in AB-range 1989-2022 © Lauterbach C6000 Debugger...

  • Page 60: Tronchip Commands

    ; sets breakpoint at range Break.Set 0x1000--0x17ff /Write ; 1000--17ff Break.Set 0x1001--0x17ff /Write ; gives an error message TrOnchip.RESet Set on-chip trigger to default state Format: TrOnchip.RESet Sets the TrOnchip settings and trigger module to the default settings. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 61: Tronchip.varconvert Adjust Complex Breakpoint In On-Chip Resource

    CPU may be not powerful enough to cover the whole structure. If the option TrOnchip.VarCONVert is set to ON, the breakpoint will automatically be converted into a single address breakpoint. This is the default setting. Otherwise an error message is generated. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 62: Tracing

    Tracing Depending on the chip the C6000 trace can either be directly output on dedicated trace pins or sent into a Coresight trace bus using an ADTF component. Another option is to store the trace onchip in trace buffers (e.g. ETB). For further information about Coresight component configuration please refer to “Setup of the...

  • Page 63: Jtag Connection

    JTAG Connection Mechanical Description of the 20-pin Debug Cable This connector is defined by ARM. LAUTERBACH’s debuggers ’JTAG Debugger for ARM7’ (LA-7746) and ’JTAG Debugger for ARM9’ (LA-7742) and ’JTAG Debugger for TMS320’ are supplied with this connector: Signal Signal...

  • Page 64: Electrical Description Of The 20-Pin Debug Cable

    JTAG connector is tristated by the debugger and it is pulled low otherwise. This signal is normally not required, but can be used to detect the tristate state if more than one debug tools are connected to the same JTAG port. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 65: Mechanical Description Of The Ti Connector

    Mechanical Description of the TI Connector This connector is defined by Texas Instruments. It is typically used on TMS320 designs. LAUTERBACH’s debuggers are not supplied with this connector, but an adapter is available (LA-7748: JTAG ARM Converter ARM-TI). Signal Signal...

  • Page 66: Faq

    Please refer to https://support.lauterbach.com/kb. 1989-2022 © Lauterbach C6000 Debugger...

  • Page 67: Operation Voltage

    Operation Voltage Adapter OrderNo Voltage Range JTAG Debugger for C6000 DSP (ICD) LA-7838 1.8 .. 3.6 V 1989-2022 © Lauterbach C6000 Debugger...

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