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Intel altera Agilex 5 FPGA E 065B User Manual
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Intel altera Agilex 5 FPGA E 065B User Manual

Intel altera Agilex 5 FPGA E 065B User Manual

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5 FPGA E-Series 065B
814550
2025.03.07

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Summary of Contents for Intel altera Agilex 5 FPGA E 065B

  • Page 1 Explore more resources ® Altera Design Hub ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide 814550 Online Version Send Feedback 2025.03.07...
  • Page 2 2.3.1. Installing the Quartus Prime Pro Edition Software......... 10 2.3.2. Installing the Development Kit..............11 2.3.3. Installing the Ashling* RiscFree Integrated Development Environment (IDE)..11 2.3.4. Installing the Intel FPGA Download Cable II Driver........12 2.4. Quick Start Guide....................13 3. Development Kit Setup....................14 3.1.
  • Page 3 Contents 5.4.2. HPS NAND Board (HPS-NB)............... 79 5.4.3. HPS Test Board (HPS-TB)................80 6. Custom Projects for the Development Kit..............81 6.1. Golden Top......................81 6.2. EMIF Pin Swizzling Setting..................81 7. Document Revision History for the Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide..................
  • Page 4 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 5 1. Overview 814550 | 2025.03.07 Related Information Development Kit Components on page 85 1.1. Block Diagram Figure 2. Agilex 5 FPGA E-Series 065B Premium Development Kit Block Diagram Nios 2 Gb Flash QSPI Hyper DDR4 MAX 10 COMP Pin Header ASx4 2 Gb Button/...
  • Page 6 Active Serial (AS) x4 configuration mode support — 2 Gb flash for Avalon streaming interface x8 configuration mode — 2 Gb flash for AS x4 configuration mode ® — Built-in Intel FPGA Download Cable II for JTAG mode device programming • Programmable clock sources •...
  • Page 7 — 1x 4 GB LPDDR4-1600 x32 for fabric I/O memory • Communication ports — JTAG header — Micro USB onboard Intel FPGA Download Cable II • Buttons, switches, and LEDs — HPS reset push button — Four dedicated user push buttons —...
  • Page 8 1. Overview 814550 | 2025.03.07 1.3. Box Contents • Agilex 5 FPGA E-Series 065B Premium Development Kit • HPS Expansion Board • USB 2.0 Micro USB cable • USB 2.0 Mini USB cable • Micro SD card • Micro SD card reader •...
  • Page 9 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 10 Agilex 5 FPGA E-Series 065B Premium Development Kit software • Ashling* RiscFree* Integrated Development Environment (IDE) • Intel FPGA Download Cable II driver 2.3.1. Installing the Quartus Prime Pro Edition Software 1. Download the Quartus Prime Pro Edition software from the FPGA Software Download Center webpage of the Intel website.
  • Page 11 Agilex 5 FPGA E-Series 065B Premium Development Kit webpage on the Intel website. 2. Unzip the Agilex 5 FPGA E-Series 065B Premium Development Kit installer package. The package creates the directory structure shown in the figure below.
  • Page 12 The Agilex 5 FPGA E-Series 065B Premium Development Kit includes onboard Intel FPGA Download Cable II circuits for FPGA and system MAX 10 programming. However, for the host computer and board to communicate, you must install the Intel FPGA Download Cable II driver on the host computer.
  • Page 13 2. Getting Started 814550 | 2025.03.07 2.4. Quick Start Guide Refer to the Agilex 5 FPGA E-Series 065B Premium Development Kit Quick Start Guide webpage to learn how the development kit works by default after power up. Related Information Agilex 5 FPGA E-Series 065B Premium Development Kit Quick Start Guide Instructions for the initial setup of the development kit.
  • Page 14 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 15 3. Development Kit Setup 814550 | 2025.03.07 Figure 5. Plastic Washers on Development Kit (Angle View) 2. Align and insert the HPS board connector to the connector on development kit board. 3. Tighten the hex thumb screws on standoff #1 and #2, as shown in the following figure.
  • Page 16 3. Development Kit Setup 814550 | 2025.03.07 Figure 6. HPS Board Installation on Development Kit Thumb Screw ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 17 OFF—Selects the factory default SW16 image • ON—Bypasses the HPS JTAG chain SW16 • OFF—Includes the HPS JTAG chain • ON—Selects the embedded Intel FPGA Download Cable II SW16 • OFF—Selects the external Intel FPGA Download Cable II dongle continued... ™ Agilex...
  • Page 18 3. Development Kit Setup 814550 | 2025.03.07 Switch Default Position Function • ON—Bypasses the FMC JTAG chain SW16 • OFF—Includes the FMC JTAG chain OFF/ON/ON/OFF Mode SW27[1] SW27[2] SW27[3] [1:4] SW27 MSEL0 MSEL1 MSEL2 Active Serial (AS) x4 Fast (Default) AS x4 Normal Avalon streaming interface x8...
  • Page 19 3. Development Kit Setup 814550 | 2025.03.07 3.3. Powering Up the Development Kit 1. Use the provided power adapter to supply power through 2. Set the power switch to the ON position. SW22 When the board powers up, the LED illuminates, which indicates that the board power up is successful.
  • Page 20 3. Development Kit Setup 814550 | 2025.03.07 3.4.3. Restoring SD Card with the Default Factory Image Note: The SD card is pre-programmed with . Completing the steps overwrites this sdimage image. Refer to RocketBoards.org to recover and update on SD card. sdimage 1.
  • Page 21 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 22 The BTS requires user access to the Agilex 5 FPGA E-Series 065B Premium Development Kit embedded Intel FPGA Download Cable. 1. If the computer connected to the embedded Intel FPGA Download Cable is running on Linux, then follow the instructions in...
  • Page 23 4. Board Test System 814550 | 2025.03.07 4.1.3. Running the BTS GUI on Windows With the power to the board off, follow these steps. 1. Connect the micro-USB cable to your computer and the board. Figure 9. USB and Power Connection to Run BTS GUI Power On Switch (SW22) Power Supply...
  • Page 24 4. Board Test System 814550 | 2025.03.07 Figure 10. BTS Package Folder Figure 11. Windows Console of BTS Launching ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 25 4. Board Test System 814550 | 2025.03.07 4.1.4. Running the BTS GUI on Linux 4.1.4.1. Configuring the Linux UART Environment Add current user to the group to ensure the access to UART, using the dialout following commands: ls -l /dev/ttyUSB* sudo chmod 666 /dev/ttyUSB* sudo usermod -a -G dialout $USER groups...
  • Page 26 4. Board Test System 814550 | 2025.03.07 Figure 12. Linux Console of BTS Launching ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 27 4. Board Test System 814550 | 2025.03.07 4.2. Troubleshooting for Launching BTS No Available Serial Ports Figure 13. Failure of "Could not find any available serial ports" 1. Check if the micro-USB is connected physically. 2. Check if the FTDI UART driver is installed successfully. a.
  • Page 28 4. Board Test System 814550 | 2025.03.07 Figure 14. UART Port List Figure 15. UART Manufacturer ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 29 4. Board Test System 814550 | 2025.03.07 Figure 16. UART Port Configuration ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 30 4. Board Test System 814550 | 2025.03.07 Figure 17. UART VID/PID No Response after Message Sent Figure 18. Failure of "sending msg is successful, but no response received" The issue roots that the UART does not work correctly, follow the check list below: ™...
  • Page 31 4. Board Test System 814550 | 2025.03.07 1. Check if the BTS is launched before the board is ready. 2. Check if there are some third-party UART tools that have occupied the port. 3. Check if there are other BTS instances and close them. 4.
  • Page 32 4. Board Test System 814550 | 2025.03.07 4.3. BTS Functionalities This section describes each control in the BTS. 4.3.1. Diagnostic GUI The Diagnostic menu provides the functionality of checking the status of the devices. To trigger a basic board diagnostic, click the Start button. After it is completed, the color of the light indicates if the test is a pass or a fail.
  • Page 33 4. Board Test System 814550 | 2025.03.07 Figure 19. Diagnostic ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 34 4. Board Test System 814550 | 2025.03.07 4.3.2. Clock Controller GUI The Clock Controller GUI can change the onboard programmable PLLs to a large range of customized frequency. Select the Clock icon on the BTS GUI to launch the Clock Controller feature.
  • Page 35 4. Board Test System 814550 | 2025.03.07 4.3.2.1. Si5332 Clock Figure 21. The Si5332 Setting Page ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 36 4. Board Test System 814550 | 2025.03.07 • Default: Restores to factory default settings. • Read: Reads the current real-time frequency setting for the oscillator associated with the active tab. • Set: Sets the programmable oscillator frequency for the selected clock to the value in the OUTx output controls.
  • Page 37 4. Board Test System 814550 | 2025.03.07 4.3.2.2. Si5518 Clock Figure 23. The Si5518 Setting Page ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 38 4. Board Test System 814550 | 2025.03.07 • Status: Displays the current configured status. • Default: Restores to factory default settings. • Soft Reset: Reboots the device without downloading the firmware and frequency plan from the NVM. • Import: Imports configurable Si5518 firmware and user boot binary files, which are generated from the tool of the Skyworks* Clockbuilder Pro software.
  • Page 39 4. Board Test System 814550 | 2025.03.07 4.3.3. Power Monitor GUI The Power Monitor GUI reports most power rails’ voltage, current, and power information on the board. It also collects temperature from the FPGA die, power modules, and diodes assembled on PCB. The Power Monitor GUI communicates with the System MAX 10 through UART, using only a micro-USB cable.
  • Page 40 4. Board Test System 814550 | 2025.03.07 4.3.3.1. Power Monitor The Power Monitor module reads the real-time data from power chips, for example, LTC7883. BTS supports 10 rails listed below. For detailed information, refer to the schematic document. • VCC_1 •...
  • Page 41 4. Board Test System 814550 | 2025.03.07 4.3.3.2. Temperature Monitor The BTS can monitor the temperature and presents the data visually, including the historical data and real-time data. The board hardware is designed with a specialized temperature, and can monitor temperatures at four different locations on the board. •...
  • Page 42 4. Board Test System 814550 | 2025.03.07 4.3.4. MAX 10 Controller GUI The Agilex 5 FPGA E-Series 065B Premium Development Kit provides you with a UART based controller to manage I/O devices and HPS card, as well as perform other system functions.
  • Page 43 4. Board Test System 814550 | 2025.03.07 4.3.4.1. Remote I/O Control 4.3.4.1.1. Remote Control You can use the remote control to access I/O devices remotely. The BTS supports the remote access of four types of remote control to device: • Push button •...
  • Page 44 4. Board Test System 814550 | 2025.03.07 Figure 29. The Remote Control of User Push Button User Switch All the user switches located on the main board are defined as follows: Type Switch Board Label DIP Switch USER SW1 SW21.1 DIP Switch USER SW2 SW21.2...
  • Page 45 4. Board Test System 814550 | 2025.03.07 Figure 30. The Remote Control of User Switch MSEL All the user MSEL located on the main board are defined as follows: Type Switch Board Label DIP Switch MSEL0 SW27.1 DIP Switch MSEL1 SW27.2 DIP Switch MSEL2...
  • Page 46 4. Board Test System 814550 | 2025.03.07 Figure 31. The Remote Control of MSEL Si569-1V8 The control of Si569-1V8 targets for swapping the Si569 input frequency remotely. There are two input source frequencies: • 148.35 MHz (default) • 148.5 MHz ™...
  • Page 47 4. Board Test System 814550 | 2025.03.07 Figure 32. The Remote Control of Si569-1V8 4.3.4.1.2. MISC LED Control You can use the BTS to control the user LEDs. Click on the LED icon to turn on and turn off the LED. The All button operates and reverses the states of all the LEDs. This function is useful to verify if the LED physical channel is okay or not.
  • Page 48 4. Board Test System 814550 | 2025.03.07 Figure 33. The Control of MISC LED 4.3.4.2. Expansion Board Control BTS also extends its functionality to the HPS expansion boards. The Agilex 5 FPGA E- Series 065B Premium Development Kit has three types of HPS expansion boards: •...
  • Page 49 4. Board Test System 814550 | 2025.03.07 Figure 34. The Control of Expansion Board 4.3.4.3. System Control You could power cycle the Agilex 5 FPGA E-Series using this tab. ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 50 4. Board Test System 814550 | 2025.03.07 Figure 35. The Control of System ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 51 4. Board Test System 814550 | 2025.03.07 4.3.5. Agilex 5 FPGA Functionality Figure 36. The Entry of Launching Agilex 5 Application ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 52 4. Board Test System 814550 | 2025.03.07 4.3.5.1. The GPIO Tab The GPIO design provides a basic general-purpose input/output test and supports LED operation. In this design, three LEDs ( , and ) are user control. One LED ) is controlled by the Agilex register transfer level (RTL), and it blinks periodically. The status of the user control LEDs can be turned on and off by clicking on the LED icon itself.
  • Page 53 4. Board Test System 814550 | 2025.03.07 Figure 38. GPIO Test Page • All: Turn on and off all the LEDs ( , and ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 54 4. Board Test System 814550 | 2025.03.07 4.3.5.2. The Memory Tab This tab allows you to read and write DDR4-COMP and LPDDR4-COMP memory on your board. Download the design through BTS Configure menu. 4.3.5.2.1. The DDR4 COMP Tab Figure 39. The DDR4 COMP Test Tab ™...
  • Page 55 4. Board Test System 814550 | 2025.03.07 The following sections describe controls on this tab. • Start: Initiates DDR4 memory transaction performance analysis. • Stop: Terminates transaction performance analysis. • Test Control — Test Mode: Infinite Read and Write (default), Single Read and Write. —...
  • Page 56 4. Board Test System 814550 | 2025.03.07 Figure 40. The DDR4 COMP Test Parameter Tab • Test Size: You can choose the size of the memory to test. The available options are 64 KB, 256 KB, 1 MB, 4MB, 16 MB, 64 MB, 256 MB, 1 GB, 4 GB, and 8 GB (default).
  • Page 57 4. Board Test System 814550 | 2025.03.07 4.3.5.2.2. The HPS DDR4 COMP Tab Same with DDR4-COMP. Figure 41. The HPS DDR4 COMP Test Tab ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 58 4. Board Test System 814550 | 2025.03.07 Figure 42. The HPS DDR4 COMP Test Parameter Tab Related Information The DDR4 COMP Tab on page 54 ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 59 4. Board Test System 814550 | 2025.03.07 4.3.5.2.3. The LPDDR4 COMP Tab Same with DDR4-COMP. Figure 43. The LPDDR4 COMP Test Tab ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 60 4. Board Test System 814550 | 2025.03.07 Figure 44. The LPDDR4 COMP Test Parameter Tab Related Information The DDR4 COMP Tab on page 54 ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 61 4. Board Test System 814550 | 2025.03.07 4.3.5.3. The Transceiver Tab 4.3.5.3.1. QSFP Test Select Configure with QSFP Design to launch the QSFP test application. The BTS automatically enables the specific application after downloading the design file ( .sof Figure 45. QSFP Test Entry ™...
  • Page 62 4. Board Test System 814550 | 2025.03.07 • Data Type: The Data Type control specifies the type of data pattern contained in the transactions. Select the following available data types for analysis: — PRBS7: Pseudo-random 7-bit binary sequences. — PRBS15: Pseudo-random 15-bit binary sequences. —...
  • Page 63 4. Board Test System 814550 | 2025.03.07 Figure 46. QSFP Test Page ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 64 4. Board Test System 814550 | 2025.03.07 4.3.5.3.2. SFP+ Test The SFP+ test shares the same test flow and test page with the QSFP test except the difference of the RTL design. Refer to the QSFP Test section for details. Figure 47.
  • Page 65 4. Board Test System 814550 | 2025.03.07 Figure 48. SFP+ Test Page Related Information QSFP Test on page 61 ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 66 4. Board Test System 814550 | 2025.03.07 4.3.5.3.3. FMC+ Test The FMC+ test shares the same test flow and test page with the QSFP test except the difference of the RTL design. Refer to the QSFP Test section for details. Figure 49.
  • Page 67 4. Board Test System 814550 | 2025.03.07 Figure 50. FMC+ Test Page Related Information QSFP Test on page 61 ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 68 4. Board Test System 814550 | 2025.03.07 4.3.5.3.4. SMA Test The SMA test shares the same test flow and test page with the QSFP test except the difference of the RTL design. Refer to the QSFP Test section for details. Figure 51.
  • Page 69 4. Board Test System 814550 | 2025.03.07 Figure 52. SMA Test Page Related Information QSFP Test on page 61 ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 70 4. Board Test System 814550 | 2025.03.07 4.3.6. Information Display 4.3.6.1. Sys Info The Sys Info menu presents the basic system information of the development kit. • Dev Kit Name: The official development kit name. • Board Revision: The silicon version. •...
  • Page 71 4. Board Test System 814550 | 2025.03.07 Figure 54. Connection 4.3.6.3. The Bottom Status Bar The bottom status bar shows the status of the UART connection and the recognized Quartus Prime software version. • UART: Shows if the board is connected to BTS successfully. •...
  • Page 72 To update LPDDR4_REFCLK_P/N from 116.625 MHz to 100 MHz, follow these steps: 1. Download the installer package v24.2 from the Agilex 5 FPGA E-Series 065B Premium Development Kit webpage on the Intel website. 2. From the BTS GUI, select Factory Writer from the Tools menu. ™ Agilex...
  • Page 73 4. Board Test System 814550 | 2025.03.07 Figure 56. The Entry of Launching Factory Writer Application 3. Select Write Si5332-U411 in the Factory Writer page and wait until the write process is complete. Figure 57. The Factory Writer Page ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 74 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 75 5. Development Kit Hardware and Configuration 814550 | 2025.03.07 5.3. Configuring the FPGA Device by Avalon Streaming Modes 1. Set (or use BTS for remote control) to Avalon streaming interface x8 mode. SW27 Note: The default MAX 10 image and hardware design supports the Avalon streaming interface x8 configuration only.
  • Page 76 5. Development Kit Hardware and Configuration 814550 | 2025.03.07 5.4. Expansion Boards The Agilex 5 FPGA E-Series 065B Premium Development Kit supports the following HPS IO48 expansion boards: • HPS Expansion Board • HPS NAND Board • HPS Test Board You can demonstrate HPS functions through these HPS cards and cables.
  • Page 77 5. Development Kit Hardware and Configuration 814550 | 2025.03.07 5.4.1. HPS Expansion Board (HPS-EB) Figure 58. HPS Expansion Board (Top View) UART Connector User LED Connector Ethernet Connector Push Button 1. Plug HPS-EB in 2. To test HPS Ethernet capability, connect HPS-EB’s RJ45 port to the Internet.
  • Page 78 5. Development Kit Hardware and Configuration 814550 | 2025.03.07 4. Connect the mini-USB cable from the vertical mini-USB connector on OOBE to the host PC. 5. Install the OOBE onto the development kit. 6. Launch the UART terminal application on the host PC, and configure it to use the settings based on the steps above.
  • Page 79 5. Development Kit Hardware and Configuration 814550 | 2025.03.07 5.4.2. HPS NAND Board (HPS-NB) Figure 59. HPS NAND Board (Top View) User LED UART Connector Ethernet Connector Push Button 1. Plug HPS-NB in 2. To test HPS Ethernet capability, connect HPS-NB’s RJ45 port to the Internet.
  • Page 80 5. Development Kit Hardware and Configuration 814550 | 2025.03.07 5.4.3. HPS Test Board (HPS-TB) Figure 60. HPS Test Board (Top View) UART User LED Connector Ethernet Connector Push Button 1. Plug HPS-TB in 2. To test HPS Ethernet capability, connect HPS-TB’s RJ45 port to the Internet.
  • Page 81 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 82 6. Custom Projects for the Development Kit 814550 | 2025.03.07 PIN_SWIZZLE_CH0_DQS2=17,21,19,23,16,22,18,20; PIN_SWIZZLE_CH0_DQS3=29,31,27,25,30,26,24,28; PIN_SWIZZLE_CH0_ECC=1,3,7,5,6,2,0,4; Related Information External Memory Interfaces (EMIF) IP User Guide: Agilex 5 FPGAs and SoCs ™ Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide Send Feedback...
  • Page 83 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 84 7. Document Revision History for the Agilex 5 FPGA E-Series 065B Premium Development Kit User Guide 814550 | 2025.03.07 Document Changes Version • Updated the Board Test System section: — Added new topics: • Setting Up the Programmer • Running the BTS GUI on Linux •...
  • Page 85 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 86 The development kit utilizes MAX 10 FPGA (10M50DAF484) for system management. It handles power sequencing, FPGA Avalon streaming interface configuration, embedded Intel FPGA Download Cable II, JTAG chain topology, I C bus access, fan speed control, system reset functions, supervise power regulators/switches status, supervise temperature sensor, clock control, and remote control.
  • Page 87 A. Development Kit Components 814550 | 2025.03.07 A.3. Power Figure 63. Power Tree Power Sequence FPGA Recommendation: PWR_ON MAX10 Group0 Group1 Group2 Group3 Group4 The development kit power tree design are for the reference. SWITCH Scale power solution based on design requirements. 12V_IN MAX16545 12V_SYS...
  • Page 88 A. Development Kit Components 814550 | 2025.03.07 Figure 64. Power Sequence POWER IN 12V_IN POWER ON 12V_EARLY 12V_EARLY_PG 5V0_SYS 5V0_SYS_PG 3V3_SYS 3V3_SYS_PG 3V3_MAX 2V5_MAX 1V8_MAX POWER OK 1V2_MAX 3V3_USB 1V1_USB 3V3_Si5518A 1V8_Si5518A Group 0 12V_SYS PWRGD_G0 12V_HPS Group 1 FPGA_VCC VCC_HSSI PWRGD_G1 VCCERT_UX...
  • Page 89 A. Development Kit Components 814550 | 2025.03.07 MAX 10 also shuts down significant power rails when temperature cross the acceptable range. A.4. Clocks Table 8. Onboard Clock Sources Source Signal Name Default I/O Standard Application Frequency 1 Hz LVCMOS 3.3 V 1PPS to FPGA 1PPS_3V3_SI5518_TO_FPGA 1 Hz...
  • Page 90 A. Development Kit Components 814550 | 2025.03.07 Figure 65. Clock Tree (50 MHz) MAX10_50M_CLK NIOS_CLK CFG_FLASH_1V8_CLK MAX10 USB_T_CLK A5ED065BB32A – Fabric AVSTx8_1V8_CLK AVSTx8_CLK OSC_CLK_1 Si5518 (125 MHz) 1PPS_GRAND_MASTER_LOOPBACK (LVCMOS 3.3V) OUT0n QSFP1_RCVD_REFCLK 1PPS_3V3_SI5518_TO_FPGA (LVCMOS 3.3V) OUT0p IN3n PTP_SAMPLE_CLK_250M (250 MHz LVDS) QSFP1_REFCLK 1PPS SMA IN OUT1...
  • Page 91 A. Development Kit Components 814550 | 2025.03.07 A.5. General Input/Output Table 9. MAX 10 Schematic Signal Name Description Interrupt pin status output for SI5518A or chip select of secondary SPI MAX10_SI5518A_GPIO0 port. Loss of lock status output for DSPLL A or SDIO of secondary SPI port. MAX10_SI5518A_GPIO1 Output enable control pin or SCLK of secondary SPI port.
  • Page 92 A. Development Kit Components 814550 | 2025.03.07 Table 10. Agilex 5 FPGA Schematic Signal Name Description GPIO pin for FPGA HVIO bank FPGA_USER_IO1 GPIO pin for FPGA HVIO bank FPGA_USER_IO2 GPIO pin for FPGA HVIO bank FPGA_USER_IO3 GPIO pin for FPGA HVIO bank FPGA_USER_IO4 GPIO pin for FPGA HVIO bank FPGA_USER_IO5...
  • Page 93 OFF to enable HPS JTAG chain • ON to select embedded Intel FPGA Download SW16.3 USB_MAX_JTAG_SEL Cable II • OFF to select external Intel FPGA Download Cable II dongle • ON to bypass FMC JTAG chain SW16.4 SW_FMC_JTAG_BYPASS • OFF to enable FMC JTAG chain User switch 1 SW21.1...
  • Page 94 A. Development Kit Components 814550 | 2025.03.07 Board Reference Schematic Signal Name Description User switch 2 SW21.2 FPGA_USER_SW2 User switch 3 SW21.3 FPGA_USER_SW3 User switch 4 SW21.4 FPGA_USER_SW4 ON/OFF development kit SW22 POWER_ON • ON to select the RS232 path from the 3-pin SW23 RS232_SEL external header...
  • Page 95 A. Development Kit Components 814550 | 2025.03.07 Board Reference Schematic Signal Name Description Green when remote access is enabled. REMOTE ACCESS User LED1 (Green) USER_SW1 User LED2 (Green) USER_SW2 User LED3 (Green) USER_SW3 User LED4 (Green) USER_SW4 Green when Active Serial (AS) x4 fast is selected. ASx4 FAST Green when AS x4 normal is selected.
  • Page 96 A. Development Kit Components 814550 | 2025.03.07 A.7. Memory Interfaces FPGA Dedicated External Memory Interface (LPDDR4) The Agilex 5 FPGA E-Series 065B Premium Development Kit supports 4GB LPDDR4 (x32 no ECC), which is connected to bank 2A. It targets up to 2667 Mbps. Micron* MT53E1G32D2FW-046 IT:C is soldered down on the development kit.
  • Page 97 A. Development Kit Components 814550 | 2025.03.07 A.8. Communication Interfaces A.8.1. QSFP+ The Agilex 5 FPGA E-Series 065B Premium Development Kit includes 2x QSFP+ ports with 4 channels connected to transceiver bank 1A and another 4 channels connected to bank 1B. The interface is PMA direct mode, which can run up to 17.16 Gbps NRZ. Each QSFP+ port has a connector and cage that support up to Class 3 power.
  • Page 98 A. Development Kit Components 814550 | 2025.03.07 Table 16. SFP1 Connector (J14) Schematic Signal Name Description Transmitter disable SFP1_3V3_TX_DIS Module rate select 0 SFP1_3V3_RS0 Module rate select 1 SFP1_3V3_RS1 Module present SFP1_3V3_PRSNTn Loss of signal SFP1_3V3_RX_LOS Transmitter fault indication SFP1_3V3_TX_FAULT C clock SFP1_3V3_SCL C data...
  • Page 99 A. Development Kit Components 814550 | 2025.03.07 RGMII (IO48 HPS) The Agilex 5 FPGA E-Series 065B Premium Development Kit provides one 10M/ 100M/1G RGMII interface through the IO48 HPS interface. The Marvell 88E1512 and connector are mounted on the HPS card. RGMII (HVIO Bank 6D) The Agilex 5 FPGA E-Series 065B Premium Development Kit provides one 10M/ 100M/1G RGMII interface through the HVIO interface.
  • Page 100 A. Development Kit Components 814550 | 2025.03.07 A.8.4. FMC The Agilex 5 FPGA E-Series 065B Premium Development Kit consists of one FMC+ slots that selective support FMC Vita 57.1 for functional expandability. FMC_TX/ are from transceiver bank 4C and are from RX[0:3]_P/N FMC_TX/RX[4:7]_P/N bank 4B.
  • Page 101 A. Development Kit Components 814550 | 2025.03.07 Agilex 5 FPGA E-Series 065B Premium Development Kit FMC Connector (J34) Schematic Signal Name I/O Bank Voltage Level (V) V57.1 Name Pin Number UX 4B — FMC_TX2_P DP2_C2M_P UX 4B — FMC_TX2_N DP2_C2M_N UX 4B —...
  • Page 102 A. Development Kit Components 814550 | 2025.03.07 Agilex 5 FPGA E-Series 065B Premium Development Kit FMC Connector (J34) Schematic Signal Name I/O Bank Voltage Level (V) V57.1 Name Pin Number HSIO 3B FMC_1V2_LA_N10 LA10_N HSIO 3B FMC_1V2_LA_P11 LA11_P HSIO 3B FMC_1V2_LA_N11 LA11_N HSIO 3B...
  • Page 103 A. Development Kit Components 814550 | 2025.03.07 Agilex 5 FPGA E-Series 065B Premium Development Kit FMC Connector (J34) Schematic Signal Name I/O Bank Voltage Level (V) V57.1 Name Pin Number HVIO 6C 1.2 (converted) FMC_1V2_LA_P27 LA27_P HVIO 6C 1.2 (converted) FMC_1V2_LA_N27 LA27_N HVIO 6C...
  • Page 104 A. Development Kit Components 814550 | 2025.03.07 Agilex 5 FPGA E-Series 065B Premium Development Kit FMC Connector (J34) Schematic Signal Name I/O Bank Voltage Level (V) V57.1 Name Pin Number — FMC_SDA — FMC_TCK — FMC_TDI — FMC_TD0 — FMC_TMS —...
  • Page 105 A. Development Kit Components 814550 | 2025.03.07 A.8.7. HPS IO48 Interface The Agilex 5 FPGA E-Series 065B Premium Development Kit connects the 48 HPS I/Os to ADM connector ( ) for the HPS Out of Box Experience (OOBE) card installation. This HPS OOBE card provides the HPS with USB, UART, Ethernet, SD card, I C, and JTAG accessibility.
  • Page 106 A. Development Kit Components 814550 | 2025.03.07 Figure 66. C Serial Bus MAX_I2C_SDA/SCL U401 Header M24128-BWMN6TP MAX31730ATC+ MAX16545 MAX16545 LTC7883AY LTC7883AY EEPROM (FRUID/CFG) Temp Sensor 0X57/0X5F OX1C 0X40 0X42 Global: 0X5A & Global: 0X5A & FPGA_3V3_SVID_SDA/SCL 12V_EARLY 12V_SYS 0X5B 0X5B CHA: 0X74 CHA: 0X47 CHB:0X75...
  • Page 107 A. Development Kit Components 814550 | 2025.03.07 A.9. Expansion Boards A.9.1. HPS Expansion Board (HPS-EB) HPS Expansion Board (HPS-EB) • RGMII 10/100/1000 Mbps Ethernet port • UART port: Standard USB Mini-B Receptacle • Micro SD card connector • Type C USB connector •...
  • Page 108 A. Development Kit Components 814550 | 2025.03.07 IO48 Interface Type Signal Name I/O Direction IOA23 USB1 DATA6 IOA24 USB1 DATA7 IOB01 SDMMC DATA0 IOB02 SDMMC DATA1 IOB03 SDMMC IOB04 IOB05 IOB06 SDMMC DATA2 IOB07 SDMMC DATA3 IOB08 SDMMC IOB09 JTAG IOB10 JTAG IOB11...
  • Page 109 A. Development Kit Components 814550 | 2025.03.07 A.9.2. HPS NAND Board (HPS-NB) HPS NAND Board (HPS-NB) • RGMII 10/100/1000 Mbps Ethernet port • UART port: Standard USB Mini-B Receptacle • C header Table 28. HPS IO48 Pinout for HPS NAND Board (HPS-NB) IO48 Interface Type Signal Name...
  • Page 110 A. Development Kit Components 814550 | 2025.03.07 IO48 Interface Type Signal Name I/O Direction IOB03 NAND WE_N IOB04 NAND RE_N IOB05 NAND WP_N IOB06 NAND DATA2 IOB07 NAND DATA3 IOB08 NAND IOB09 NAND DATA4 IOB10 NAND DATA5 IOB11 NAND DATA6 IOB12 NAND DATA7...
  • Page 111 A. Development Kit Components 814550 | 2025.03.07 A.9.3. HPS Test Board (HPS-TB) HPS Test Board (HPS-TB) • RGMII 10/100/1000 Mbps Ethernet port • UART port: Standard USB Mini-B Receptacle • Micro SD card connector • Type C USB connector • Mictor* 38-pin connector (JTAG only without Trace signals) •...
  • Page 112 A. Development Kit Components 814550 | 2025.03.07 IO48 Interface Type Signal Name I/O Direction IOA24 EMAC0 RXD3 IOB01 SDMMC DATA0 IOB02 SDMMC DATA1 IOB03 SDMMC IOB04 Lvl_Shift_Sel IOB05 IOB06 SDMMC DATA2 IOB07 SDMMC DATA3 IOB08 SDMMC IOB09 JTAG IOB10 JTAG IOB11 JTAG IOB12...
  • Page 113 A. Development Kit Components 814550 | 2025.03.07 A.10. Connectors and Headers Table 30. Connectors and Headers Board Reference Description Part Number JTAG Header 10-pins 70247-1051 (Molex*) RS232 Debug header 3-pins HTSW-103-07-L-S (Samtec*) HSIO bank IO header 10-pins TSM-105-01-T-DV-TR (Samtec) HVIO bank IO header 10-pins TSM-105-01-T-DV-TR (Samtec) MIPI connector 22-pins 52437-2271 (Molex)
  • Page 114 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 115 Altera or Intel. Altera and Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
  • Page 116 C. Safety and Regulatory Compliance Information 814550 | 2025.03.07 C.1.1. Safety Warnings Power Supply Hazardous Voltage AC mains voltages are present within the power supply assembly. No user serviceable parts are present inside the power supply. Power Connect and Disconnect The AC power supply cord is the primary disconnect device from mains (AC power) and used to remove all DC power from the board/system.
  • Page 117 C. Safety and Regulatory Compliance Information 814550 | 2025.03.07 Power Cord Requirements The plug on the power cord must be a grounding-type male plug designed for use in your region. It must have certification marks showing certification by an agency in your region.
  • Page 118 C. Safety and Regulatory Compliance Information 814550 | 2025.03.07 Cooling Requirements Maintain a minimum clearance area of 5 centimeters (2 inches) around the side, front and back of the board for cooling purposes. Do not block power supply ventilation holes and fan. Electro-Magnetic Interference (EMI) This equipment has not been tested for compliance with emission limits of FCC and similar international regulations.
  • Page 119 Failure to use wrist straps can damage components within the system. Attention: Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of this product in unsorted municipal waste.
  • Page 120 C. Safety and Regulatory Compliance Information 814550 | 2025.03.07 Please return this product to Intel for proper disposition. If it is not returned, refer to local environmental regulations for proper recycling. Do not dispose of product in unsorted municipal waste.

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