Epson S1C17M30 Technical Manual
Epson S1C17M30 Technical Manual

Epson S1C17M30 Technical Manual

Cmos 16-bit single chip
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CMOS 16-BIT SINGLE CHIP MICROCONTROLLER
S1C17M30/M31/M32/M33/M34
Technical Manual
Rev. 1.3

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Summary of Contents for Epson S1C17M30

  • Page 1 CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17M30/M31/M32/M33/M34 Technical Manual Rev. 1.3...
  • Page 2 Epson evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed by the use of it.
  • Page 3: Notational Conventions And Symbols In This Manual

    PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17M30/M31/ M32/M33/M34. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.
  • Page 4: Table Of Contents

    1.1 Features .......................... 1-1 1.2 Block Diagram ......................... 1-3 1.3 Pins ..........................1-4 1.3.1 S1C17M30 Pin Configuration Diagram (TQFP12-48PIN) ......... 1-4 1.3.2 S1C17M31 Pin Configuration Diagram (TQFP12-48PIN) ......... 1-5 1.3.3 S1C17M32 Pin Configuration Diagram (TQFP13-64PIN) ......... 1-6 1.3.4 S1C17M33 Pin Configuration Diagram (TQFP14-80PIN) ......... 1-7 1.3.5 S1C17M33 Pad Configuration Diagram (Chip) ..........
  • Page 5 6.2.3 Pull-Up/Pull-Down .................... 6-3 6.2.4 CMOS Output and High Impedance State ............6-3 6.3 Clock Settings ......................... 6-3 6.3.1 PPORT Operating Clock ................... 6-3 6.3.2 Clock Supply in SLEEP Mode ................6-4 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 6 9.2 Output Pin and External Connection ................9-1 9.2.1 Output Pin ......................9-1 9.3 Clock Settings ......................... 9-2 9.3.1 RTCA Operating Clock ..................9-2 9.3.2 Theoretical Regulation Function ............... 9-2 9.4 Operations ........................9-3 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 7 11.4.2 Counter Underflow ..................11-3 11.4.3 Operations in Repeat Mode ................11-3 11.4.4 Operations in One-shot Mode ............... 11-3 11.4.5 Counter Value Read ..................11-4 11.5 Interrupt ........................11-4 11.6 Control Registers ......................11-4 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 8 13.2.4 Input Pin Pull-Up/Pull-Down Function ............13-3 13.3 Clock Settings ......................13-3 13.3.1 SPIA Operating Clock ..................13-3 13.3.2 Clock Supply in DEBUG Mode ..............13-4 13.3.3 SPI Clock (SPICLKn) Phase and Polarity ............13-4 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 9 15.2 Input/Output Pins ......................15-2 15.3 Clock Settings ......................15-3 15.3.1 T16B Operating Clock ................... 15-3 15.3.2 Clock Supply in SLEEP Mode ............... 15-3 15.3.3 Clock Supply in DEBUG Mode ..............15-3 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 10 17.3.2 Clock Supply in SLEEP Mode ............... 17-2 17.3.3 Clock Supply in DEBUG Mode ..............17-2 17.4 Operations ........................17-2 17.4.1 Initialization ....................17-2 17.4.2 Data Transmission Procedures ..............17-3 17.4.3 REMO Output Waveform ................17-3 Seiko Epson Corporation viii S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 11 18.6.2 Segment Pin Assignment ................18-12 18.6.3 Common Pin Assignment ................18-12 18.7 Interrupt ........................18-14 18.8 Control Registers ......................18-14 LCD8A Clock Control Register ....................18-14 LCD8A Control Register ......................18-15 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 12 ADC12A Ch.n Trigger/Analog Input Select Register ..............20-7 ADC12A Ch.n Configuration Register ..................20-8 ADC12A Ch.n Interrupt Flag Register ..................20-9 ADC12A Ch.n Interrupt Enable Register ................. 20-10 ADC12A Ch.n Result Register m ..................... 20-10 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 13 0x4100–0x4106 Supply Voltage Detector (SVD3) ..........AP-A-6 0x4160–0x416c 16-bit Timer (T16) Ch.0..............AP-A-6 0x41b0 Flash Controller (FLASHC) ............AP-A-7 0x4200–0x42e2 I/O Ports (PPORT) ............... AP-A-7 0x4300–0x431e Universal Port Multiplexer (UPMUX) ........... AP-A-24 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 14 B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Appendix F EEPROM Function ................... AP-F-1 Revision History Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 15: Overview

    16-bit CPU. It is suitable for battery-driven applications that require an LCD display and a temperature measurement function. The S1C17M30/M31/M32/M33/M34 allows use of a part of the Flash area or a dedicated area as an EEPROM by implementing a specific library. For more information, refer to “Appendix F EEPROM Function.”...
  • Page 16 Flash 2.4 to 5.5 V (When V (7.5 V) is supplied externally) programming 2.4 to 5.5 V (When V is generated internally) Operating temperature Operating temperature range -40 to 85 °C Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 17: Block Diagram

    SDO0–1 (SPIA) SPICLK0–1 2 Ch. #SPISS0–1 * The pin configuration and peripheral circuit function depends on the model. For detailed information, refer to Section 1.3, “Pins.” Figure 1.2.1 S1C17M30/M31/M32/M33/M34 Block Diagram Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 18: Pins

    Pin name P00/SENB0/UPMUX/SEG24 P01/SENA0/UPMUX/SEG23 P02/REF0/UPMUX/SEG22 PD4/OSC4 P03/RFIN0/UPMUX/SEG21 PD3/OSC3 P04/EXCL00/UPMUX/SEG20 P23/RFIN1/UPMUX/SEG45 P22/REF1/UPMUX/SEG46 P05/EXCL01/UPMUX/SEG19 S1C17M30 P06/CLPLS/UPMUX/SEG18 P21/SENA1/UPMUX/SEG47 P07/REMO/UPMUX/SEG17 P20/SENB1/UPMUX/SEG48 P10/FOUT/UPMUX/SEG16 P73/EXOSC/ADIN01 P11/UPMUX/SEG15 P72/RFCKO0/ADIN00 P71/LFRO/VREFA0 P12/UPMUX/SEG14 P13/UPMUX/SEG13 P45/EXSVD0/SEG49 Figure 1.3.1.1 S1C17M30 Pin Configuration Diagram (TQFP12-48PIN) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 19: S1C17M31 Pin Configuration Diagram (Tqfp12-48Pin)

    Pin name P00/SENB0/UPMUX/SEG24 P01/SENA0/UPMUX/SEG23 PD4/OSC4 P02/REF0/UPMUX/SEG22 P03/RFIN0/UPMUX/SEG21 PD3/OSC3 P04/EXCL00/UPMUX/SEG20 P23/RFIN1/UPMUX/SEG45 P05/EXCL01/UPMUX/SEG19 P22/REF1/UPMUX/SEG46 S1C17M31 P06/CLPLS/UPMUX/SEG18 P21/SENA1/UPMUX/SEG47 P20/SENB1/UPMUX/SEG48 P07/REMO/UPMUX/SEG17 P10/FOUT/UPMUX/SEG16 P73/EXOSC/ADIN01 P72/RFCKO0/ADIN00 P11/UPMUX/SEG15 P71/LFRO/VREFA0 P45/EXSVD0/SEG49 Figure 1.3.2.1 S1C17M31 Pin Configuration Diagram (TQFP12-48PIN) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 20: S1C17M32 Pin Configuration Diagram (Tqfp13-64Pin)

    P02/REF0/UPMUX/SEG22 P27/UPMUX/SEG41 P03/RFIN0/UPMUX/SEG21 P26/UPMUX/SEG42 P04/EXCL00/UPMUX/SEG20 P25/UPMUX/SEG43 P05/EXCL01/UPMUX/SEG19 P24/UPMUX/SEG44 S1C17M32 P23/RFIN1/UPMUX/SEG45 P06/CLPLS/UPMUX/SEG18 P22/REF1/UPMUX/SEG46 P07/REMO/UPMUX/SEG17 P21/SENA1/UPMUX/SEG47 P10/FOUT/UPMUX/SEG16 P11/UPMUX/SEG15 P20/SENB1/UPMUX/SEG48 P12/UPMUX/SEG14 P73/EXOSC/ADIN01 P13/UPMUX/SEG13 P72/RFCKO0/ADIN00 P14/UPMUX/SEG12 P71/LFRO/VREFA0 P15/UPMUX/SEG11 P45/EXSVD0/SEG49 Figure 1.3.3.1 S1C17M32 Pin Configuration Diagram (TQFP13-64PIN) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 21: S1C17M33 Pin Configuration Diagram (Tqfp14-80Pin)

    P03/RFIN0/UPMUX/SEG21 P25/UPMUX/SEG43 P04/EXCL00/UPMUX/SEG20 P24/UPMUX/SEG44 P05/EXCL01/UPMUX/SEG19 P23/RFIN1/UPMUX/SEG45 P06/CLPLS/UPMUX/SEG18 P22/REF1/UPMUX/SEG46 S1C17M33 P07/REMO/UPMUX/SEG17 P21/SENA1/UPMUX/SEG47 P10/FOUT/UPMUX/SEG16 P20/SENB1/UPMUX/SEG48 P11/UPMUX/SEG15 P76/ADIN04 P12/UPMUX/SEG14 P75/ADIN03 P13/UPMUX/SEG13 P74/ADIN02 P14/UPMUX/SEG12 P73/EXOSC/ADIN01 P15/UPMUX/SEG11 P72/RFCKO0/ADIN00 P71/LFRO/VREFA0 P45/EXSVD0/SEG49 Figure 1.3.4.1 S1C17M33 Pin Configuration Diagram (QFP14-80PIN) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 22: S1C17M33 Pad Configuration Diagram (Chip)

    OSC1 OSC1 OSC2 OSC2 P65/COM2 P66/COM1 P67/COM0 #RESET #RESET 2.922 mm Figure 1.3.5.1 S1C17M33 Pad Configuration Diagram (Chip) Pad opening: X = 68 µm, Y = 68 µm Chip thickness: 400 µm Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 23 -1,376.3 -410.0 615.0 -1,416.3 1,376.3 795.0 -660.0 1,416.3 -1,376.3 -805.0 725.0 -1,416.3 1,376.3 875.0 -810.0 1,416.3 -1,376.3 -915.0 898.4 -1,416.3 1,376.3 955.0 -910.0 1,416.3 -1,376.3 -1,025.0 988.4 -1,416.3 1,376.3 1,035.0 -1,010.0 1,416.3 Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 24: S1C17M34 Pin Configuration Diagram (Tqfp13-64Pin)

    PD3/OSC3 P04/EXCL00/UPMUX/SEG20 P24/UPMUX/SEG44 P05/EXCL01/UPMUX/SEG19 P23/RFIN1/UPMUX/SEG45 P06/CLPLS/UPMUX/SEG18 P22/REF1/UPMUX/SEG46 P07/REMO/UPMUX/SEG17 P21/SENA1/UPMUX/SEG47 S1C17M34 P20/SENB1/UPMUX/SEG48 P10/FOUT/UPMUX/SEG16 P76/ADIN04 P11/UPMUX/SEG15 P75/ADIN03 P12/UPMUX/SEG14 P13/UPMUX/SEG13 P74/ADIN02 P14/UPMUX/SEG12 P73/EXOSC/ADIN01 P15/UPMUX/SEG11 P72/RFCKO0/ADIN00 P71/LFRO/VREFA0 P45/EXSVD0/SEG49 Figure 1.3.6.1 S1C17M34 Pin Configuration Diagram (TQFP13-64PIN) Seiko Epson Corporation 1-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 25: Pin Descriptions

    IR remote controller clear pulse output ✓ ✓ ✓ ✓ ✓ UPMUX User-selected I/O (universal port multiplexer) ✓ ✓ ✓ ✓ ✓ SEG18 LCD segment output ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 1-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 26 12-bit A/D converter Ch.0 trigger input ✓ ✓ ✓ ✓ ✓ UPMUX User-selected I/O (universal port multiplexer) ✓ ✓ ✓ ✓ ✓ SEG40 LCD segment output ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 1-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 27 16-bit PWM timer Ch.1 event counter input 0 ✓ ✓ ✓ ✓ ✓ COM7 LCD common output ✓ ✓ ✓ ✓ ✓ SEG3 LCD segment output ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 1-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 28 ✓ ✓ ✓ ✓ ✓ OSC4 OSC3 oscillator circuit output ✓ ✓ ✓ ✓ ✓ Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name. Seiko Epson Corporation 1-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 29 16-bit PWM timer (T16B) TOUTn0/CAPn0 n = 0, 1, 2 T16B Ch.n PWM output/capture input 0 TOUTn1/CAPn1 T16B Ch.n PWM output/capture input 1 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation 1-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 30: Power Supply, Reset, And Clocks

    Use the V regulator in automatic mode when no spe- cial control is required. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 31: System Reset Controller (Src)

    #RESET pin, so the pin can be left open. For the #RESET pin characteris- tics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 32: Reset Sources

    Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and con- trol bits, refer to the “CPU and Debugger” chapter or “Control Registers” in each peripheral circuit chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34...
  • Page 33: Clock Generator (Clg)

    - The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation. • Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state. Figure 2.3.1.1 shows the CLG configuration. Table 2.3.1.1 CLG Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30...
  • Page 34: Input/Output Pins

    2.3.3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 35: Osc1 Oscillator Circuit

    Figure 2.3.3.2 OSC1 Oscillator Circuit Configuration For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Dia- gram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respec- tively. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 36: Osc3 Oscillator Circuit

    EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 37: Operations

    Figure 2.3.4.2 shows an operation example when the oscillation startup control circuit is used. (1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1N[1:0] setting gain Oscillation waveform Normal operation Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 38 In addition to the above, configure the following bits when using the crystal/ceramic oscillator: - CLGOSC3.OSC3INV[1:0] bits (Set oscillation inverter gain) Configure the following bits when using the internal oscillator: - CLGOSC3.OSC3FQ bit (Select oscillation frequency) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 39: System Clock Switching

    This allows flexible clock control according to the wake-up process. Configure the clock using the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit to enable this function. Seiko Epson Corporation 2-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 40 10 ms is required. When OSC3CLK is be- ing used as the system clock or a peripheral circuit clock, do not use the auto-trimming function. Seiko Epson Corporation 2-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev.
  • Page 41: Operating Mode

    RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source. Seiko Epson Corporation 2-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 42 CLGSCLK.CLKSRC[1:0] = 0x3 EXOSC HALT OSC3 OSC3 ∗ In RUN and HALT modes, the clock sources not used HALT as SYSCLK can be all disabled. Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram Seiko Epson Corporation 2-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 43: Interrupts

    Bits 15–2 Reserved Bits 1–0 REGMODE[1:0] These bits control the internal regulator operating mode. Table 2.6.1 Internal Regulator Operating Mode PWGVD1CTL.REGMODE[1:0] bits Operating mode Economy mode Normal mode Reserved Automatic mode Seiko Epson Corporation 2-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 44: Clg System Clock Control Register

    These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation 2-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 45: Clg Oscillation Control Register

    Stop oscillating or clock input Each bit corresponds to the clock source as follows: CLGOSC.EXOSCEN bit: EXOSC clock input CLGOSC.OSC3EN bit: OSC3 oscillator circuit CLGOSC.OSC1EN bit: OSC1 oscillator circuit CLGOSC.IOSCEN bit: IOSC oscillator circuit Seiko Epson Corporation 2-16 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 46: Clg Osc1 Control Register

    ” in the “Electrical Characteristics” chapter. GI1C Bits 7–6 INV1B[1:0] These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 crystal os- cillator circuit. Seiko Epson Corporation 2-17 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 47: Clg Osc3 Control Register

    1 (R/WP): 16 MHz 0 (R/WP): 12 MHz Bit 9 OSC3MD This bit selects an oscillator type of the OSC3 oscillator circuit. 1 (R/WP): Crystal/ceramic oscillator 0 (R/WP): Internal oscillator Bits 8–6 Reserved Seiko Epson Corporation 2-18 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 48: Clg Interrupt Flag Register

    Reset Remarks CLGINTF 15–8 – 0x00 – – – – – OSC1STPIF Cleared by writing 1. OSC3TEDIF – – – OSC3STAIF Cleared by writing 1. OSC1STAIF IOSCSTAIF Bits 15–6, 3 Reserved Seiko Epson Corporation 2-19 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 49: Clg Interrupt Enable Register

    CLGINTE.OSC3TEDIE bit: OSC3 oscillation auto-trimming completion interrupt CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt Seiko Epson Corporation 2-20 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 50: Clg Fout Control Register

    These bits set the frequency trimming value for the OSC3 internal oscillator circuit. This setting does not affect the OSC3 crystal/ceramic oscillation frequency. Table 2.6.11 Oscillation Frequency Trimming Setting of OSC3 Internal Oscillator Circuit CLGTRIM1.OSC3AJ[6:0] bits OSC3 internal oscillator frequency 0x7f High 0x00 Seiko Epson Corporation 2-21 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 51: Clg Oscillation Frequency Trimming Register 2

    “Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC1 oscillator circuit is inactive. Seiko Epson Corporation 2-22 S1C17M30/M31/M32/M33/M34...
  • Page 52: Cpu And Debugger

    3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...
  • Page 53: Cpu Core

    DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DE- BUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd in- struction. Neither hardware interrupts nor NMI are accepted during DEBUG mode. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 54: Resource Requirements And Debugging Tools

    For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resis- tor R ” in the “Electrical Characteristics” chapter. R is not required when using the DSIO pin as a general- purpose I/O port pin. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 55: Flash Security Function

    The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit. Bit 0 PSRN The value (0 or 1) of the PSR N (negative) flag can be read out with this bit. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 56: Debug Ram Base Register

    – 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 57: Memory And Bus

    Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer) Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can be accessed with an 8-bit, 16-bit, or 32-bit instruction. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 58: Flash Memory

    The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 59: Flash Programming

    The embedded display data RAM is used to store display data for the LCD driver. Areas unused for display data in the display data RAM can be used as a general-purpose RAM. For specific information on the display data RAM, refer to “Display Data RAM” in the “LCD Driver” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 60: Peripheral Circuit Control Registers

    0x416c T16_0INTE T16 Ch.0 Interrupt Enable Register Flash controller (FLASHC) 0x41b0 FLASHCWAIT FLASHC Flash Read Cycle Register I/O ports (PPORT) 0x4200 P0DAT P0 Port Data Register 0x4202 P0IOEN P0 Port Enable Register Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 61 P7 Port Interrupt Flag Register 0x4278 P7INTCTL P7 Port Interrupt Control Register 0x427a P7CHATEN P7 Port Chattering Filter Enable Register 0x427c P7MODSEL P7 Port Mode Select Register 0x427e P7FNCSEL P7 Port Function Select Register Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 62 T16B Ch.0 Timer Counter Data Register 0x5008 T16B0CS T16B Ch.0 Counter Status Register 0x500a T16B0INTF T16B Ch.0 Interrupt Flag Register 0x500c T16B0INTE T16B Ch.0 Interrupt Enable Register 0x5010 T16B0CCCTL0 T16B Ch.0 Compare/Capture 0 Control Register Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 63 REMC3 Data Bit Length Register 0x532a REMINTF REMC3 Status and Interrupt Flag Register 0x532c REMINTE REMC3 Interrupt Enable Register 0x5330 REMCARR REMC3 Carrier Waveform Register 0x5332 REMCCTL REMC3 Carrier Modulation Control Register Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 64: System-Protect Function

    0x54c2 TSRVR0VCTL TSRVR Ch.0 Reference Voltage Generator Control Register *1 Cannot be used in the S1C17M30. *2 Cannot be used in the S1C17M31. *3 Cannot be used in the S1C17M32. *4 Cannot be used in the S1C17M34. 4.6.1 System-Protect Function The system-protect function protects control registers and bits from writings.
  • Page 65: Control Registers

    FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 17.12 MHz (max.) 17.12 MHz (max.) 12.6 MHz (max.) 6.3 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 66: Interrupt Controller (Itc)

    Address misaligned interrupt Memory access instruction – (0xfffc00) Debugging interrupt brk instruction, etc. 2 (0x02) TTBR + 0x08 Watchdog timer overflow 3 (0x03) TTBR + 0x0c Reserved for C compiler – – Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 67 R/F converter Ch.1 interrupt • Reference oscillation completion • Sensor A oscillation completion • Sensor B oscillation completion • Measurement counter overflow error • Time base counter overflow error 22 (0x16) TTBR + 0x58 16-bit timer Ch.2 interrupt Underflow Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 68: Vector Table Base Address (Ttbr)

    ITC if the status is changed to interrupt enabled when the interrupt flag is 1. For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective pe- ripheral circuit descriptions. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 69: Itc Interrupt Request Processing

    (0–7) to be set to the IL[2:0] bits in the PSR. The software inter- rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation as that of the hardware interrupt. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 70: Interrupt Processing By The Cpu

    – 2–0 ILVy [2:0] Bits 15–11 Reserved Bits 7–3 Reserved Bits 10–8 ILVy [2:0] = 2x +1) Bits 2–0 ILVy [2:0] = 2x) These bits set the interrupt level of each interrupt. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 71 (ILVREMC3_0) ITCLV8 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV17[2:0] R/F converter Ch.1 interrupt Setup Register 8) (ILVRFC_1) 7–3 – 0x00 – – 2–0 ILV16[2:0] R/F converter Ch.0 interrupt (ILVRFC_0) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 72 2–0 ILV20[2:0] – 16-bit timer Ch.3 interrupt (ILVT16_3) ITCLV11 15–8 – 0x00 – – (ITC Interrupt Level 7–3 – 0x00 – Setup Register 11) 2–0 ILV22[2:0] – 16-bit PWM timer Ch.2 interrupt (ILVT16B_2) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 73: O Ports (Pport)

    Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 6.1.1 shows the configuration of PPORT. Table 6.1.1 Port Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30...
  • Page 74: I/O Cell Structure And Functions

    Figure 6.2.1 I/O Cell Configuration Refer to “Pin Descriptions” in the “Overview” chapter for the cell type, either the over voltage tolerant fail-safe type I/O cell or the standard I/O cell, included in each port. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 75: Schmitt Input

    (Clock division ratio selection = Clock frequency setting) 4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Settings in Step 3 determine the input sampling time of the chattering filter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 76: Clock Supply In Sleep Mode

    When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings: 1. Set the PxIOEN.PxOENy bit to 1. (Enable output) 2. Set the PxMODSEL.PxSELy bit to 0. (Enable GPIO function) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 77: Port Input/Output Control

    6.4.2 Port Input/Output Control Peripheral I/O function control The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor- mation, refer to the respective peripheral circuit chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 78: Interrupts

    Clearing PxINTF.PxIFy Interrupt edge selection Port input interrupts will occur at the falling edge of the input signal when setting the PxINTCTL.PxEDGEy bit to 1, or the rising edge when setting to 0. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 79: Control Registers

    *2: The bit configuration differs depending on the port group. Bits 15–8 PxIEN[7:0] These bits enable/disable the GPIO port input. 1 (R/W): Enable (The port pin status is input.) 0 (R/W): Disable (Input data is fixed at 0.) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 80: Px Port Pull-Up/Down Control Register

    Initial Reset Remarks PxINTCTL 15–8 PxEDGE[7:0] 0x00 – 7–0 PxIE[7:0] 0x00 *1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 81: Px Port Chattering Filter Enable Register

    *1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–14 Px7MUX[1:0] Bits 1–0 Px0MUX[1:0] These bits select the peripheral I/O function to be assigned to each port pin. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 82: P Port Clock Control Register

    The PPORT operating clock should be configured by selecting the clock source using the PCLK. CLKSRC[1:0] bits and the clock division ratio using the PCLK.CLKDIV[3:0] bits as shown in Table 6.6.3. These settings determine the input sampling time of the chattering filter. Seiko Epson Corporation 6-10 S1C17M30/M31/M32/M33/M34...
  • Page 83: P Port Interrupt Flag Group Register

    A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 6-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 84: Control Register And Port Function Configuration Of This Ic

    ✓ P0OEN4 ✓ ✓ ✓ ✓ ✓ P0OEN3 ✓ ✓ ✓ ✓ ✓ P0OEN2 ✓ ✓ ✓ ✓ ✓ P0OEN1 ✓ ✓ ✓ ✓ ✓ P0OEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 85 ✓ P0CHATEN4 ✓ ✓ ✓ ✓ ✓ P0CHATEN3 ✓ ✓ ✓ ✓ ✓ P0CHATEN2 ✓ ✓ ✓ ✓ ✓ P0CHATEN1 ✓ ✓ ✓ ✓ ✓ P0CHATEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 86: P1 Port Group

    ✓ P1IN4 – – ✓ ✓ ✓ P1IN3 – ✓ ✓ ✓ ✓ P1IN2 – ✓ ✓ ✓ ✓ P1IN1 ✓ ✓ ✓ ✓ ✓ P1IN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 87 ✓ P1IE4 – – ✓ ✓ ✓ P1IE3 – ✓ ✓ ✓ ✓ P1IE2 – ✓ ✓ ✓ ✓ P1IE1 ✓ ✓ ✓ ✓ ✓ P1IE0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 88 – UPMUX – – LCD8A SEG10 – – ✓ ✓ ✓ – – UPMUX – – LCD8A SEG9 – – ✓ ✓ ✓ *1: Refer to the “Universal Port Multiplexer” chapter. Seiko Epson Corporation 6-16 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 89: P2 Port Group

    ✓ P2REN4 – – ✓ ✓ ✓ P2REN3 ✓ ✓ ✓ ✓ ✓ P2REN2 ✓ ✓ ✓ ✓ ✓ P2REN1 ✓ ✓ ✓ ✓ ✓ P2REN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-17 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 90 ✓ ✓ ✓ 7–6 P23MUX[1:0] ✓ ✓ ✓ ✓ ✓ 5–4 P22MUX[1:0] ✓ ✓ ✓ ✓ ✓ 3–2 P21MUX[1:0] ✓ ✓ ✓ ✓ ✓ 1–0 P20MUX[1:0] ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-18 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 91: P3 Port Group

    ✓ P3OEN4 ✓ ✓ ✓ ✓ ✓ P3OEN3 ✓ ✓ ✓ ✓ ✓ P3OEN2 ✓ ✓ ✓ ✓ ✓ P3OEN1 ✓ ✓ ✓ ✓ ✓ P3OEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-19 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 92 ✓ P3CHATEN4 ✓ ✓ ✓ ✓ ✓ P3CHATEN3 ✓ ✓ ✓ ✓ ✓ P3CHATEN2 ✓ ✓ ✓ ✓ ✓ P3CHATEN1 ✓ ✓ ✓ ✓ ✓ P3CHATEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-20 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 93: P4 Port Group

    ✓ P4IN4 – – – – ✓ P4IN3 – – – – ✓ P4IN2 – – – – ✓ P4IN1 – – ✓ ✓ ✓ P4IN0 – – ✓ ✓ ✓ Seiko Epson Corporation 6-21 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 94 ✓ P4IE4 – – – – ✓ P4IE3 – – – – ✓ P4IE2 – – – – ✓ P4IE1 – – ✓ ✓ ✓ P4IE0 – – ✓ ✓ ✓ Seiko Epson Corporation 6-22 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 95 ✓ ✓ ✓ ✓ ✓ – – – – – – LCD8A SEG32 – – ✓ ✓ ✓ – – – – – – LCD8A SEG31 – – – – ✓ Seiko Epson Corporation 6-23 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 96: P5 Port Group

    ✓ P5REN4 – – – ✓ ✓ P5REN3 – – – – ✓ P5REN2 – – – – ✓ P5REN1 – – – – ✓ P5REN0 – – – – ✓ Seiko Epson Corporation 6-24 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 97 – – – – ✓ – – – – – – LCD8A SEG26 – – – ✓ ✓ – – – – – – LCD8A SEG25 – – – ✓ ✓ Seiko Epson Corporation 6-25 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 98: P6 Port Group

    ✓ P6REN4 ✓ ✓ ✓ ✓ ✓ P6REN3 ✓ ✓ ✓ ✓ ✓ P6REN2 ✓ ✓ ✓ ✓ ✓ P6REN1 ✓ ✓ ✓ ✓ ✓ P6REN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-26 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 99 ✓ ✓ ✓ 7–6 P63MUX[1:0] ✓ ✓ ✓ ✓ ✓ 5–4 P62MUX[1:0] ✓ ✓ ✓ ✓ ✓ 3–2 P61MUX[1:0] ✓ ✓ ✓ ✓ ✓ 1–0 P60MUX[1:0] ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-27 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 100: P7 Port Group

    ✓ P7OEN4 – – – ✓ ✓ P7OEN3 ✓ ✓ ✓ ✓ ✓ P7OEN2 ✓ ✓ ✓ ✓ ✓ P7OEN1 ✓ ✓ ✓ ✓ ✓ P7OEN0 – – – – ✓ Seiko Epson Corporation 6-28 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 101 ✓ P7CHATEN4 – – – ✓ ✓ P7CHATEN3 ✓ ✓ ✓ ✓ ✓ P7CHATEN2 ✓ ✓ ✓ ✓ ✓ P7CHATEN1 ✓ ✓ ✓ ✓ ✓ P7CHATEN0 – – – – ✓ Seiko Epson Corporation 6-29 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 102: Pd Port Group

    – ✓ ✓ ✓ ✓ ✓ PDIN3 ✓ ✓ ✓ ✓ ✓ – – – – – – – PDIN1 ✓ ✓ ✓ ✓ ✓ PDIN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-30 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 103 – – ✓ ✓ ✓ ✓ ✓ – – – – OSC3 – – ✓ ✓ ✓ ✓ ✓ – – – – OSC4 – – ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-31 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 104: Common Registers Between Port Groups

    ✓ P4INT ✓ ✓ ✓ ✓ ✓ P3INT ✓ ✓ ✓ ✓ ✓ P2INT ✓ ✓ ✓ ✓ ✓ P1INT ✓ ✓ ✓ ✓ ✓ P0INT ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation 6-32 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 105: Universal Port Multiplexer (Upmux)

    4. Initialize the peripheral circuit. 5. Set the PxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 106: Control Registers

    Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 107: Watchdog Timer (Wdt2)

    CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDTCLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DE- BUG mode. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 108: Operations

    1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDTCTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 109: Operations In Halt And Sleep Modes

    IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 110: Wdt2 Control Register

    WDT2 should also be reset concurrently when running WDT2. WDT2 Counter Compare Match Register Register name Bit name Initial Reset Remarks WDTCMP 15–10 – 0x00 – – 9–0 CMP[9:0] 0x3ff R/WP Bits 15–10 Reserved Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 111 These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 112: Real-Time Clock (Rtca)

    * Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 113: Clock Settings

    · · · · · · · · · · · · · · · 0x3e 59.1 0x7e -1.9 0x3f 60.1 0x7f -1.0 Minimum resolution: 1 ppm, Correction rate range: -61.0 to 60.1 ppm Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 114: Operations

    3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 115: Real-Time Clock Counter Operations

    9.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 9.4.4.1. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 116: Interrupts

    1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 117: Control Registers

    Depending on these operation timings, the +1 second correction may be executed after the count-up operation resumes. For more information on the +1 second correction, refer to “Real-Time Clock Counter Operations.” Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 118: Rtc Second Alarm Register

    The RTCALM1.RTCSHA[2:0] bits and the RTCALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can be set in BCD code as shown in Table 9.6.1. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 119: Rtc Hour/Minute Alarm Register

    SWRUN Bits 15–12 BCD10[3:0] Bits 11–8 BCD100[3:0] The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a BCD code from the RTCSWCTL.BCD10[3:0] bits and the RTCSWCTL.BCD100[3:0] bits, respectively. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 120: Rtc Second/1Hz Register

    1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 121: Rtc Hour/Minute Register

    1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 9-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 122: Rtc Month/Day Register

    These bits are used to set and read day of the week. The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 9.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation 9-11 S1C17M30/M31/M32/M33/M34...
  • Page 123: Rtc Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: RTCINTF.RTCTRMIF bit: Theoretical regulation completion interrupt RTCINTF.SW1IF bit: Stopwatch 1 Hz interrupt RTCINTF.SW10IF bit: Stopwatch 10 Hz interrupt RTCINTF.SW100IF bit: Stopwatch 100 Hz interrupt Bits 11–9 Reserved Seiko Epson Corporation 9-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 124: Rtc Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: RTCINTE.RTCTRMIE bit: Theoretical regulation completion interrupt RTCINTE.SW1IE bit: Stopwatch 1 Hz interrupt RTCINTE.SW10IE bit: Stopwatch 10 Hz interrupt RTCINTE.SW100IE bit: Stopwatch 100 Hz interrupt Seiko Epson Corporation 9-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 125 RTCINTE.1DAYIE bit: 1-day interrupt RTCINTE.1HURIE bit: 1-hour interrupt RTCINTE.1MINIE bit: 1-minute interrupt RTCINTE.1SECIE bit: 1-second interrupt RTCINTE.1_2SECIE bit: 1/2-second interrupt RTCINTE.1_4SECIE bit: 1/4-second interrupt RTCINTE.1_8SECIE bit: 1/8-second interrupt RTCINTE.1_32SECIE bit: 1/32-second interrupt Seiko Epson Corporation 9-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 126: Supply Voltage Detector (Svd3)

    - Low power supply voltage detection count function to generate an inter- rupt/reset when low power supply voltage is successively detected the number of times specified. - Continuous operation is also possible. Figure 10.1.1 shows the configuration of SVD3. Table 10.1.1 SVD3 Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31 S1C17M32...
  • Page 127: Input Pins And External Connection

    If the CLGOSC.xxxxSLPC bit for the CLK_SVD3 clock source is 1, the CLK_SVD3 clock source is deactivated during SLEEP mode and SVD3 stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD3 is supplied and the SVD3 operation resumes. Seiko Epson Corporation 10-2 S1C17M30/M31/M32/M33/M34...
  • Page 128: Clock Supply In Debug Mode

    SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time SVD_EXT before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit re- sponse time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation 10-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 129: Svd3 Operations

    SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 10-4 S1C17M30/M31/M32/M33/M34...
  • Page 130: Svd3 Reset

    Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD3 operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD3. Seiko Epson Corporation 10-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 131: Svd3 Control Register

    0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 10-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 132: Svd3 Status And Interrupt Flag Register

    EXSVD0/1) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT 0 (R): Power supply voltage (V or EXSVD0/1) ≥ SVD detection voltage V or EXSVD detection voltage V SVD_EXT Seiko Epson Corporation 10-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 133: Svd3 Interrupt Enable Register

    • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 10-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 134: 16-Bit Timers (T16)

    • A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 11.1.1 shows the configuration of a T16 channel. Table 11.1.1 T16 Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
  • Page 135: Clock Settings

    (Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 11-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 136: Counter Underflow

    At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation 11-3 S1C17M30/M31/M32/M33/M34...
  • Page 137: Counter Value Read

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16 Ch.n operating clock (counter clock). Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of T16 Ch.n. Seiko Epson Corporation 11-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 138: T16 Ch.n Mode Register

    PRESET MODEN Bits 15–9 Reserved Bit 8 PRUN This bit starts/stops the timer. 1 (W): Start timer 0 (W): Stop timer 1 (R): Timer is running 0 (R): Timer is idle Seiko Epson Corporation 11-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 139: T16 Ch.n Reload Data Register

    This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 11-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 140: T16 Ch.n Interrupt Enable Register

    This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 141: Uart (Uart3)

    • Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. • Provides the carrier modulation output function. Figure 12.1.1 shows the UART3 configuration. Table 12.1.1 UART3 Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
  • Page 142: Input/Output Pins And External Connections

    - UAnCLK.CLKSRC[1:0] bits (Clock source selection) - UAnCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 12-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 143: Clock Supply In Sleep Mode

    (UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 12.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation 12-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 144: Operations

    - Set the interrupt enable bits in the UAnINTE register to 1. * (Enable interrupts) * The initial value of the UAnINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the UA- nINTE.TBEIE bit is set to 1. Seiko Epson Corporation 12-4 S1C17M30/M31/M32/M33/M34...
  • Page 145: Data Transmission

    Read the UAnINTF.TBEIF bit UAnINTF.TBEIF = 1 ? Write transmit data to the UAnTXD register Transmit data remained? Wait for an interrupt request (UAnINTF.TBEIF = 1) Figure 12.5.2.2 Data Transmission Flowchart Seiko Epson Corporation 12-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 146: Data Reception

    Read receive data (1 byte) from the UAnRXD register the UAnRXD register Read receive data (1 byte) from the UAnRXD register Receive data remained? Receive data remained? Figure 12.5.3.2 Data Reception Flowcharts Seiko Epson Corporation 12-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 147: Irda Interface

    Writing 1 to the UAnMOD.CAREN bit enables the carrier modulation function allowing carrier modulation wave- forms to be output according to the UAnMOD.PECAR bit setting. Data transmit control is identical to that for nor- mal interface even in this case. Seiko Epson Corporation 12-7 S1C17M30/M31/M32/M33/M34...
  • Page 148: Receive Errors

    The received data that encountered an error is still transferred to the receive data buffer and the UAnINTF.PEIF bit (parity error interrupt flag) is set to 1 when the data becomes ready to read from the UAnRXD register (see the Note on framing error). Seiko Epson Corporation 12-8 S1C17M30/M31/M32/M33/M34...
  • Page 149: Overrun Error

    1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bits 7–6 Reserved Bits 5–4 CLKDIV[1:0] These bits select the division ratio of the UART3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation 12-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 150: Uart3 Ch.n Mode Register

    0 (R/W): Disable input inverting function Bit 8 INVTX This bit enables the USOUTn output inverting function. 1 (R/W): Enable output inverting function 0 (R/W): Disable output inverting function Bit 7 Reserved Seiko Epson Corporation 12-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 151: Uart3 Ch.n Baud-Rate Register

    Notes: • The UAnBR register settings can be altered only when the UAnCTL.MODEN bit = 0. • Do not set the UAnBR.FMD[3:0] bits to a value other than 0 to 3 when the UAnMOD.BRDIV bit = 1. Seiko Epson Corporation 12-11 S1C17M30/M31/M32/M33/M34...
  • Page 152: Uart3 Ch.n Control Register

    Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte FIFO, and older received data is read first. Seiko Epson Corporation 12-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 153: Uart3 Ch.n Status And Interrupt Flag Register

    UAnINTF.PEIF bit: Parity error interrupt UAnINTF.OEIF bit: Overrun error interrupt UAnINTF.RB2FIF bit: Receive buffer two bytes full interrupt UAnINTF.RB1FIF bit: Receive buffer one byte full interrupt UAnINTF.TBEIF bit: Transmit buffer empty interrupt Seiko Epson Corporation 12-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 154: Uart3 Ch.n Interrupt Enable Register

    UAnCAWF 15–8 – 0x00 – – 7–0 CRPER[7:0] 0x00 Bits 15–8 Reserved Bits 7–0 CRPER[7:0] These bits set the carrier modulation output frequency. For more information, refer to “Carrier Modu- lation.” Seiko Epson Corporation 12-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 155: Synchronous Serial Interface (Spia)

    • Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 13.1.1 shows the SPIA configuration. Table 13.1.1 SPIA Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30...
  • Page 156: Input/Output Pins And External Connections

    SDIn #SPISS0 SPICLKn #SPISS1 #SPISS #SPISS2 External SPI master device External SPI slave devices SPICLK SPICLK #SPISS SPICLK Figure 13.2.2.2 Connections between SPIA in Slave Mode and External SPI Master Device Seiko Epson Corporation 13-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 157: Pin Functions In Master Mode And Slave Mode

    16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation 13-3 S1C17M30/M31/M32/M33/M34...
  • Page 158: Clock Supply In Debug Mode

    SDIn SDOn (Master mode) SDOn (Slave mode) SDOn (Slave mode) Writing data to the SPInTXD register Figure 13.3.3.1 SPI Clock Phase and Polarity (SPInMOD.LSBFST bit = 0, SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 159: Data Format

    1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation 13-5 S1C17M30/M31/M32/M33/M34...
  • Page 160 SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 13.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 13-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 161: Data Reception In Master Mode

    Software operations SPInRXD → Data (R) Data (W) → SPInTXD SPInRXD → Data (R) 1 (W) → SPInINTF.TENDIF Figure 13.5.3.1 Example of Data Receiving Operations in Master Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 162: Terminating Data Transfer In Master Mode

    SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 13-8 S1C17M30/M31/M32/M33/M34...
  • Page 163 Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 13.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 164: Terminating Data Transfer In Slave Mode

    “Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 13.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 13-10 S1C17M30/M31/M32/M33/M34...
  • Page 165: Control Registers

    Remarks SPInMOD 15–12 – – – 11–8 CHLN[3:0] 7–6 – – PUEN NOCLKDIV LSBFST CPHA CPOL Bits 15–12 Reserved Bits 11–8 CHLN[3:0] These bits set the bit length of transfer data. Seiko Epson Corporation 13-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 166: Spia Ch.n Control Register

    Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 13-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 167: Spia Ch.n Transmit Data Register

    0x00 – – 6–4 – – OEIF H0/S0 Cleared by writing 1. TENDIF H0/S0 RBFIF H0/S0 Cleared by reading the SPInRXD register. TBEIF H0/S0 Cleared by writing to the SPInTXD register. Seiko Epson Corporation 13-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 168: Spia Ch.n Interrupt Enable Register

    The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 169: C (I2C)

    • The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns. Figure 14.1.1 shows the I2C configuration. Table 14.1.1 I2C Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
  • Page 170: Input/Output Pins And External Connections

    • The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 14-2 S1C17M30/M31/M32/M33/M34...
  • Page 171: Clock Settings

    14.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation 14-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 172: Operations

    - Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 14-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 173: Data Transmission In Master Mode

    I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation 14-5 S1C17M30/M31/M32/M33/M34...
  • Page 174 Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 14-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 175: Data Reception In Master Mode

    This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation 14-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 176 Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 14-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 177: 10-Bit Addressing In Master Mode

    Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 14-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 178: Data Transmission In Slave Mode

    Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 14-10 S1C17M30/M31/M32/M33/M34...
  • Page 179 A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 14.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 14-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 180: Data Reception In Slave Mode

    I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 14-12 S1C17M30/M31/M32/M33/M34...
  • Page 181 Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 14.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 14-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 182: Slave Operations In 10-Bit Address Mode

    If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 14-14 S1C17M30/M31/M32/M33/M34...
  • Page 183: Error Detection

    4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation 14-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 184: Interrupts

    Master mode BRT + 3 CLK_I2Cn TXSTART = 1 TXSTART = 0 STARTIF = 1 Slave mode Address matching the I2CnOADR register BSY = 1 TR = 0/1 STARTIF = 1 Seiko Epson Corporation 14-16 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 185: Control Registers

    (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-17 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 186: I2C Ch.n Mode Register

    The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-18 S1C17M30/M31/M32/M33/M34...
  • Page 187: I2C Ch.n Control Register

    Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation 14-19 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 188: I2C Ch.n Transmit Data Register

    0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 14-20 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 189: I2C Ch.n Interrupt Enable Register

    Transmit buffer empty interrupt I2C Ch.n Interrupt Enable Register Register name Bit name Initial Reset Remarks I2CnINTE 15–8 – 0x00 – – BYTEENDIE GCIE NACKIE STOPIE STARTIE ERRIE RBFIE TBEIE Bits 15–8 Reserved Seiko Epson Corporation 14-21 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 190 I2CnINTE.NACKIE bit: NACK reception interrupt I2CnINTE.STOPIE bit: STOP condition interrupt I2CnINTE.STARTIE bit: START condition interrupt I2CnINTE.ERRIE bit: Error detection interrupt I2CnINTE.RBFIE bit: Receive buffer full interrupt I2CnINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 14-22 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 191: 16-Bit Pwm Timers (T16B)

    - The capture circuit captures counter values using external/software trigger signals and generates interrupts. (Can be used to measure external event periods/cycles.) Figure 15.1.1 shows the T16B configuration. Table 15.1.1 T16B Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31 S1C17M32...
  • Page 192: Input/Output Pins

    * Indicates the status when the pin is configured for T16B. If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 15-2 S1C17M30/M31/M32/M33/M34...
  • Page 193: Clock Settings

    Figure 15.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation 15-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 194: Operations

    - T16BnCTL.CNTMD[1:0] bits (Select count up/down operation) - T16BnCTL.ONEST bit (Select one-shot/repeat operation) - Set the T16BnCTL.PRESET bit to 1. (Reset counter) - Set the T16BnCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 15-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 195: Counter Block Operations

    MAX value. If the MAX value is altered to a value smaller than the current counter value, the counter is cleared to 0x0000 and continues counting up to the new MAX value. Seiko Epson Corporation 15-5 S1C17M30/M31/M32/M33/M34...
  • Page 196 MODEN = 1 PRESET = 1 RUN = 1 Software operation Data (W) → MC[15:0] RUN = 1 RUN = 0 Hardware operation 0xffff Count cycle MAX value Counter Time 0x0000 Seiko Epson Corporation 15-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 197 Data (W) → MC[15:0] RUN = 1 RUN = 1 0xffff MAX value Counter Time 0x0000 RUN = 0 Figure 15.4.2.3 Operations in Repeat Up/Down Count and One-shot Up/Down Count Modes Seiko Epson Corporation 15-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 198: Comparator/Capture Block Operations

    MAX value (T16BnMC register) Counter Comparison value (T16BnCCRm register) Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 199 (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 200 (T16BnMC register) Compare period Compare buffer Counter value Time 0x0000 CNTMAXIF = 1 CNTMAXIF = 1 CNTMAXIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 201 (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 202 (T16BnMC register) Counter Compare buffer value Compare period Time 0x0000 CNTZEROIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 203 Compare period during counting down Time 0x0000 CNTMAXIF = 1 CNTZEROIF = 1 CNTMAXIF = 1 CNTZEROIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 CMPCAPmIF = 1 Seiko Epson Corporation 15-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 204 If the captured data stored in the T16BnCCRm register is overwritten by the next trigger when the T16BnINTF. CMPCAPmIF bit is still set, an overwrite error occurs (the T16BnINTF.CAPOWmIF bit is set). Seiko Epson Corporation 15-14 S1C17M30/M31/M32/M33/M34...
  • Page 205 Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation (2) Asynchronous capture mode (When T16BnCCCTLm.CAPTRG[1:0] bits = 0x3) Count clock T16BnTC.TC[15:0] Capture trigger signal T16BnCCRm.CC[15:0] Capturing operation Figure 15.4.3.4 Synchronous Capture Mode/Asynchronous Capture Mode Seiko Epson Corporation 15-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 206: Tout Output Control

    The TOUT signal polarity (active level) can be set using the T16BnCCCTLm.TOUTINV bit. It is set to active high by setting the T16BnCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 15.4.4.2 and 15.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 15-16 S1C17M30/M31/M32/M33/M34...
  • Page 207 Software control mode (0x0) Set mode (0x1) Toggle/reset mode (0x2) Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 15-17 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 208 Set/reset mode (0x3) Toggle mode(0x4) Reset mode (0x5) Toggle/set mode (0x6) Reset/set mode (0x7) ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.2 TOUT Output Waveform (T16BnCCCTLm.TOUTMT bit = 0) Seiko Epson Corporation 15-18 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 209 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 15-19 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 210 Set/reset mode (0x3) TOUTn0 TOUTn1 Toggle mode(0x4) TOUTn0 TOUTn1 Reset mode (0x5) TOUTn0 TOUTn1 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Seiko Epson Corporation 15-20 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 211 Toggle/set mode (0x6) TOUTn0 TOUTn1 Reset/set mode (0x7) TOUTn0 TOUTn1 ∗ ( ) indicates the T16BnCCCTLm.TOUTMD[2:0] bit-setting value. Figure 15.4.4.3 TOUT Output Waveform (T16BnCCCTL0.TOUTMT bit = 1, T16BnCCCTL1.TOUTMT bit = 0) Seiko Epson Corporation 15-21 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 212: Interrupt

    Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16B Ch.n operating clock (counter clock). Bit 3 Reserved Bits 2–0 CLKSRC[2:0] These bits select the clock source of T16B Ch.n. Seiko Epson Corporation 15-22 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 213: T16B Ch.n Counter Control Register

    T16BnCTL.ONEST bit setting (see Table 15.6.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16BnCTL.CNTMD[1:0] bit settings (see Table 15.6.2). Seiko Epson Corporation 15-23 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 214: T16B Ch.n Max Counter Data Register

    T16BnCTL.MODEN bit to 1 until the T16BnCS.BSY bit is set to 0 from 1. • Do not set the T16BnMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16BnTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 15-24 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 215: T16B Ch.n Counter Status Register

    This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 15-25 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 216: T16B Ch.n Interrupt Flag Register

    Note: The configuration of the T16BnINTF.CAPOWmIF and T16BnINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 15-26 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 217: T16B Ch.n Interrupt Enable Register

    The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 15-27 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 218: T16B Ch.n Comparator/Capture M Control Register

    These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16BnCCRm register in capture mode (see Table 15.6.4). The T16BnCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 15-28 S1C17M30/M31/M32/M33/M34...
  • Page 219 The signal becomes inactive by the MATCH signal. All count modes TOUTnm The signal becomes inactive by the MATCHm or MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 15-29 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 220: T16B Ch.n Compare/Capture M Data Register

    In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 15-30 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 221: Sound Generator (Snda)

    Clock generator DBRUN MODEN SBSY Sound register MOSEL[1:0] Sound generation STIM[3:0] circuit BZOUT SINV Output control circuit SSTP #BZOUT Interrupt controller Interrupt control circuit EMIE EMIF EDIE EDIF Figure 16.1.1 SNDA Configuration Seiko Epson Corporation 16-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 222: Output Pins And External Connections

    Piezoelectric buzzer #BZOUT S1C17 SNDA Figure 16.2.2.1 Connection between SNDA and Piezoelectric Buzzer (Direct Drive) Piezoelectric buzzer BZOUT S1C17 SNDA Figure 16.2.2.2 Connection between SNDA and Piezoelectric Buzzer (Single Pin Drive) Seiko Epson Corporation 16-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 223: Clock Settings

    IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Normal buzzer output start/stop procedure 1. Set the SNDSEL.MOSEL[1:0] bits to 0x0. (Set normal buzzer mode) Seiko Epson Corporation 16-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 224 Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDDAT.SFRQ[7:0] bits ≤ SNDDAT.SLEN[5:0] bits • Settings as SNDDAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 16-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 225 – 71.9 35.9 0x15 – – – – 68.8 34.4 0x14 – – – – 65.6 32.8 0x13 – – – – 62.5 31.3 0x12 – – – – 59.4 29.7 Seiko Epson Corporation 16-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 226: Buzzer Output In One-Shot Buzzer Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SND- INTF.SBSY bit is cleared to 0. Figure 16.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 16-6 S1C17M30/M31/M32/M33/M34...
  • Page 227: Output In Melody Mode

    At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDINTF.SBSY bit is cleared to 0. Figure 16.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation 16-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 228 = 32,768 Hz) CLK_SNDA SNDDAT.SFRQ[7:0] bits Scale Frequency [Hz] 0xf8 131.60 0xea 139.44 0xdd 147.60 0xd1 156.04 0xc5 165.49 0xba 175.23 0xaf 186.18 0xa5 197.40 0x9c 208.71 0x93 221.41 0x8b 234.06 Seiko Epson Corporation 16-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 229: Interrupts

    This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not. 1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bit 7 Reserved Seiko Epson Corporation 16-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 230: Snda Select Register

    187.5 43.6 171.9 156.3 53.3 140.6 125.0 68.6 109.4 93.8 78.1 62.5 46.9 31.3 15.6 Note: Be sure to avoid altering these bits when SNDINTF.SBSY bit = 1. Bits 7–3 Reserved Seiko Epson Corporation 16-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 231: Snda Control Register

    This bit specifies a tie or slur (continuous play with the previous note) in melody mode. 1 (R/W): Enable tie/slur 0 (R/W): Disable tie/slur This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation 16-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 232: Snda Interrupt Flag Register

    No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: SNDINTF.EMIF bit: Sound buffer empty interrupt SNDINTF.EDIF bit: Sound output completion interrupt Seiko Epson Corporation 16-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 233: Snda Interrupt Enable Register

    These bits enable SNDA interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts The following shows the correspondence between the bit and interrupt: SNDINTE.EMIE bit: Sound buffer empty interrupt SNDINTE.EDIE bit: Sound output completion interrupt Seiko Epson Corporation 16-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 234: Ir Remote Controller (Remc3)

    • Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 17.1.1 shows the REMC3 configuration. Table 17.1.1 REMC3 Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
  • Page 235: External Connections

    1. Write 1 to the REMDBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMCLK.CLKSRC[1:0] and REMCLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 17-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 236: Data Transmission Procedures

    The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 17.4.3.1 shows an example of the output waveform. Seiko Epson Corporation 17-3 S1C17M30/M31/M32/M33/M34...
  • Page 237 The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REM- DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMAPLEN. APLEN[15:0] and REMDBLEN.DBLEN[15:0] bits. Figure 17.4.3.3 shows an example of the data signal gen- erated. Seiko Epson Corporation 17-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 238: Continuous Data Transmission And Compare Buffers

    (REMDBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMDBLEN.DBLEN[15:0] bit-setting value. 17.4.4 Continuous Data Transmission and Compare Buffers Figure 17.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation 17-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 239: Interrupts

    The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the in- terrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 17-6 S1C17M30/M31/M32/M33/M34...
  • Page 240: Application Example: Driving El Lamp

    1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the REMC3 operating clock. Bits 3–2 Reserved Seiko Epson Corporation 17-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 241: Remc3 Data Bit Counter Control Register

    This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 17-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 242: Remc3 Data Bit Counter Register

    0x0000 H0/S0 Cleared by writing 1 to the REMDBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation 17-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 243: Remc3 Data Bit Active Pulse Length Register

    Transfer to the REMAPLEN buffer has not completed. 0 (R): Transfer to the REMAPLEN buffer has completed. While this bit is set to 1, writing to the REMAPLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 17-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 244: Remc3 Interrupt Enable Register

    These bits set the carrier signal cycle. A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends when the counter exceeds the REMCARR.CRPER[7:0] bit-setting value. (See Figure 17.4.3.2.) Seiko Epson Corporation 17-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 245: Remc3 Carrier Modulation Control Register

    This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMDBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 17-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 246: Lcd Driver (Lcd8A)

    • Includes a power supply for 1/3 bias driving (allows external voltages to be applied). (Note: See the table below.) • Provides the frame signal monitoring output pin. • Can generate interrupts every frame. Figure 18.1.1 shows the LCD8A configuration. Table 18.1.1 LCD8A Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31 S1C17M32...
  • Page 247 COMx NLINE[2:0] Clock CLK_LCD8A control circuit SEGx CLKSRC[1:0] Clock generator CLKDIV[2:0] DBRUN LCDDIS MODEN DSPREV Drive SEGREV control circuit COMREV DSPC[1:0] Display data DSPAR COMxDEN EXVCSEL S1C17M30/M32 Figure 18.1.1 LCD8A Configuration Seiko Epson Corporation 18-2 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 248: Output Pins And External Connections

    0 may cause the LCD panel characteristics to fluctuate. Table 18.2.1.2 Segment Pin Configuration Model Available SEG pins Unavailable SEG pins S1C17M30 SEG0–3 (COM4–7), SEG13–24, SEG36–40, SEG45–49 SEG4–12, SEG25–35, SEG41–44 S1C17M31 SEG0–3 (COM4–7), SEG15–24, SEG34–40, SEG45–49 SEG4–14, SEG25–33, SEG41–44 S1C17M32 SEG0–3 (COM4–7), SEG7–26, SEG32–49 SEG4–6, SEG27–31...
  • Page 249: Clock Settings

    : LCD8A operating clock frequency [Hz] CLK_LCD8A FRMCNT: LCD8TIM1.FRMCNT[3:0] setting value (0 to 15) LDUTY: LCD8TIM1.LDUTY[2:0] setting value (0 to 7) Table 18.3.4.1 lists frame frequency settings when f = 32,768 Hz as an example. CLK_LCD8A Seiko Epson Corporation 18-4 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 250: Lcd Power Supply

    1, set the LCD8PWR.EXVCSEL bit to 1 and set both the LCD8PWR.VCEN and LCD- 8PWR.BSTEN bits to 0 to turn both the LCD voltage regulator and LCD voltage booster off. Figure 18.4.2.1 shows an external connection example for external voltage application mode 1. Seiko Epson Corporation 18-5 C17M30/M31/M32/M33/M34...
  • Page 251: External Voltage Application Mode

    The LCD panel contrast can be adjusted within 16 levels using the LCD8PWR.LC[3:0] bits. This function is real- ized by controlling the voltage output from the LCD voltage regulator. Therefore, the LCD8PWR.LC[3:0] bits can- not be used for contrast adjustment in external voltage application modes 1 and 2. Seiko Epson Corporation 18-6 C17M30/M31/M32/M33/M34...
  • Page 252: Operations

    RAM is not altered. The common pins are set to dynamic drive for “All on” and to static drive for “All off.” This function can be used to make the display flash on and off without altering the display memory. Seiko Epson Corporation 18-7 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev.
  • Page 253: Inverted Display

    SEG1 SEG1 SEG1 SEG1 COM6/SEG2 COM6 COM6 Unused Unused SEG2 SEG2 SEG2 SEG2 COM7/SEG3 COM7 Unused Unused Unused SEG3 SEG3 SEG3 SEG3 SEG4–49 SEG4–49 SEG4–49 SEG4–49 SEG4–49 SEG4–49 SEG4–49 SEG4–49 SEG4–49 Seiko Epson Corporation 18-8 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 254: Drive Waveforms

    1 frame LFRO display status COM0 COM0 COM1 COM2 COM3 COM1 COM4 COM5 COM6 COM7 COM2 SEGx COM3 COM4 COM5 COM6 COM7 SEGx Figure 18.5.5.1 1/8 Duty Drive Waveform (1/3 bias) Seiko Epson Corporation 18-9 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 255 COM2 COM3 COM1 SEGx COM2 COM3 SEGx Figure 18.5.5.2 1/4 Duty Drive Waveform (1/3 bias) 1 frame LFRO display status COM0 COM0 SEGx SEGx Figure 18.5.5.3 Static Drive Waveform (1/3 bias) Seiko Epson Corporation 18-10 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 256: Partial Common Output Drive

    In the display data RAM, two screen areas can be allocated and the LCD8DSP.DSPAR bit can be used to switch between the screens. Setting the LCD8DSP.DSPAR bit to 0 selects display area 0; setting to 1 selects display area 1. Seiko Epson Corporation 18-11 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev.
  • Page 257: Segment Pin Assignment

    COM2 COM4 COM1 COM5 COM0 Unused area (general-purpose RAM) LCD8DSP.SEGREV · · · bit = 1 LCD8DSP.SEGREV · · · bit = 0 Figure 18.6.3.2 Display Data RAM Map (1/6 duty) Seiko Epson Corporation 18-12 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 258 · · · bit = 0 Figure 18.6.3.4 Display Data RAM Map (static drive) * The S1C17M30/M31/M32/M34 does not have the segment pins listed below, so the corresponding addresses are configured as an unused area (general-purpose RAM). When LCD8DSP.SEGREV bit = 1 1/8 to 1/2 duty, static drive S1C17M30: SEG4–12 (0x7004–0x700c, 0x7044–0x704c), SEG25–35 (0x7019–0x7023, 0x7059–0x7063),...
  • Page 259: Interrupt

    18 LCD DRIVER (LCD8A) When LCD8DSP.SEGREV bit = 0 1/8 to 1/5 duty S1C17M30: SEG4–12 (0x7031–0x7029, 0x7071–0x7069), SEG25–35 (0x701c–0x7012, 0x705c–0x7052), SEG41–44 (0x700c–0x7009, 0x704c–0x7049) S1C17M31: SEG4–14 (0x7031–0x7027, 0x7071–0x7067), SEG25–33 (0x701c–0x7014, 0x705c–0x7054), SEG41–44 (0x700c–0x7009, 0x704c–0x7049) S1C17M32: SEG4–6 (0x7031–0x702f, 0x7071–0x706f), SEG27–31 (0x701a–0x7016, 0x705a–0x7056) S1C17M34: SEG4–6 (0x7031–0x702f, 0x7071–0x706f), SEG25–31 (0x701c–0x7016, 0x705c–0x7056),...
  • Page 260: Lcd8A Control Register

    Note: If the LCD8CTL.MODEN bit is altered from 1 to 0 while the LCD panel is displaying, the LCD display is automatically turned off and the LCD8DSP.DSPC[1:0] bits are also set to 0x0. Also the LCD voltage regulator is automatically turned off and the LCD8PWR.VCEN bit is set to 0. Seiko Epson Corporation 18-15 C17M30/M31/M32/M33/M34...
  • Page 261: Lcd8A Power Control Register

    Note: Do not alter the control bits in this register from the initial value when using a model that does not have an LCD power supply, except the LCD8PWR.EXVCSEL bit manipulation for V dis- charging. Seiko Epson Corporation 18-16 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 262 VCEN This bit turns the LCD voltage regulator on and off. 1 (R/W): LCD voltage regulator on 0 (R/W): LCD voltage regulator off For more information, refer to “LCD Power Supply.” Seiko Epson Corporation 18-17 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 263: Lcd8A Display Control Register

    “Display On/Off.” LCD8A COM Pin Control Register 0 Register name Bit name Initial Reset Remarks LCD8COMC0 15–8 – 0x00 – – COM7DEN COM6DEN COM5DEN COM4DEN COM3DEN COM2DEN COM1DEN COM0DEN Bits 15–8 Reserved Seiko Epson Corporation 18-18 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 264: Lcd8A Interrupt Flag Register

    LCD8INTE 15–8 – 0x00 – – 7–1 – 0x00 – FRMIE Bits 15–1 Reserved Bit 0 FRMIE This bit enables the frame interrupt. 1 (R/W): Enable interrupt 0 (R/W): Disable interrupt Seiko Epson Corporation 18-19 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 265: F Converter (Rfc)

    • Provides an output and continuous oscillation function for monitoring the oscillation frequency. • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 19.1.1 shows the RFC configuration. Table 19.1.1 RFC Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
  • Page 266: Input/Output Pins And External Connections

    Figure 19.2.2.1 Connection Example in Resistive Sensor DC Oscillation Mode SENBn SEN1 SENAn REFn RFINn : Reference resistor : Resistive sensor (AC bias) SEN1 S1C17 RFC : Reference capacitor Figure 19.2.2.2 Connection Example in Resistive Sensor AC Oscillation Mode Seiko Epson Corporation 19-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 267: Clock Settings

    (Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 19-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 268: Operating Modes

    To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 19-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 269: Converting Operations And Control Procedure

    The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation 19-5 S1C17M30/M31/M32/M33/M34...
  • Page 270: Forced Termination

    Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 19.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 19-6 S1C17M30/M31/M32/M33/M34...
  • Page 271: Cr Oscillation Frequency Monitoring Function

    The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the in- terrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 19-7 S1C17M30/M31/M32/M33/M34...
  • Page 272: Control Registers

    This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 19-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 273: Rfc Ch.n Oscillation Trigger Register

    This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation 19-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 274: Rfc Ch.n Measurement Counter Low And High Registers

    Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 19-10 S1C17M30/M31/M32/M33/M34...
  • Page 275: Rfc Ch.n Interrupt Flag Register

    RFCnINTE.OVTCIE bit: Time base counter overflow error interrupt RFCnINTE.OVMCIE bit: Measurement counter overflow error interrupt RFCnINTE.ESENBIE bit: Sensor B oscillation completion interrupt RFCnINTE.ESENAIE bit: Sensor A oscillation completion interrupt RFCnINTE.EREFIE bit: Reference oscillation completion interrupt Seiko Epson Corporation 19-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 276: 12-Bit A/D Converter (Adc12A)

    2. 16-bit timer underflow trigger 3. External trigger • Can convert multiple analog input signals sequentially. • Can generate conversion completion and overwrite error interrupts. Figure 20.1.1 shows the ADC12A configuration. Table 20.1.1 ADC12A Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31 S1C17M32...
  • Page 277: Input Pins And External Connections

    : acquisition time). Figure 20.3.2.1 shows an equivalent circuit of the analog input portion. ADINnm ADIN ADIN Source impedance : Analog input resistance ADIN : Analog input capacitance ADIN Figure 20.3.2.1 Equivalent Circuit of Analog Input Portion Seiko Epson Corporation 20-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 278: Operations

    A/D conversion is actually started in sync with CLK_T16_k after a trigger is accepted. Writing 0 to the ADC12_nCTL.ADST bit stops A/D conversion after the one currently being executed has com- pleted. Seiko Epson Corporation 20-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 279: Conversion Mode And Analog Input Pin Settings

    3. Read the A/D conversion result of the analog input m (ADC12_nADmD.ADmD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 20-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 280 ADINn4 ADINn4 ADC12_nAD3D.AD3D[15:0] ADINn3 conversion result (first) ADINn3 conversion result (second) ADC12_nAD4D.AD4D[15:0] ADINn4 conversion result (first) ADINn4 conversion result (second) Cleared Cleared ADC12_nINTF.AD3CIF Cleared Cleared ADC12_nINTF.AD4CIF Figure 20.4.4.1 A/D Conversion Operations Seiko Epson Corporation 20-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 281: Interrupts

    (ADC12_nTRG.CNVMD = 0). If A/D conversion is stopped after the maximum analog input pin number (different in each model) has been completed, these bits indicate ADINn0. Bit 11 Reserved Seiko Epson Corporation 20-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 282: Adc12A Ch.n Trigger/Analog Input Select Register

    ENDAIN[2:0] bits ≥ ADC12_nTRG.STAAIN[2:0] bits. Bits 10–8 STAAIN[2:0] These bits set the analog input pin to be A/D converted first. See Table 20.6.1 for the relationship between analog input pins and bit setting values. Seiko Epson Corporation 20-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 283: Adc12A Ch.n Configuration Register

    Note: Make sure that the ADC12_nCTL.BSYSTAT bit is set to 0 before altering the ADC12_nCFG register. Bits 15–2 Reserved Bits 1–0 VRANGE[1:0] These bits set the A/D converter operating voltage range. Seiko Epson Corporation 20-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 284: Adc12A Ch.n Interrupt Flag Register

    The following shows the correspondence between the bit and interrupt: ADC12_nINTF.ADmOVIF bit: Analog input signal m A/D conversion result overwrite error interrupt ADC12_nINTF.ADmCIF bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation 20-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 285: Adc12A Ch.n Interrupt Enable Register

    ADC12A Ch.n Result Register m Register name Bit name Initial Reset Remarks ADC12_nADmD 15–0 ADmD[15:0] 0x0000 – Bits 15–0 ADmD[15:0] These bits are the A/D conversion results of the analog input signal m. Seiko Epson Corporation 20-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 286: Temperature Sensor/Reference Voltage Generator (Tsrvr)

    A/D converter. • Can supply the reference voltage generated in this circuit to external devices if this IC has the VREFA exclusive pin. Figure 21.1.1 shows the TSRVR configuration. Table 21.1.1 TSRVR Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
  • Page 287: External Connections

    ADD: A/D conversion result at temperature T or T (decimal) : A/D converter reference voltage [V] REFA For details of the internal A/D converter, refer to the “12-bit A/D Converter” chapter. Seiko Epson Corporation 21-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 288: Control Registers

    TSRVRnVCTL.VREFAMD[1:0] VREFA bits are set to 0x2 or 0x3. • When the TSRVRnVCTL.VREFAMD[1:0] bits are not set to 0x0, do not apply an external volt- age to the VREFAm pin. Seiko Epson Corporation 21-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 289: Multiplier/Divider (Copro2)

    %rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 22.2.1 Mode Setting Register Seiko Epson Corporation 22-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 290: Multiplication

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output (16 bits) Flag output Figure 22.3.1 Data Path in Multiplication Mode Seiko Epson Corporation 22-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 291: Division

    16 bits Argument 1 32 bits Operation result S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 22.4.1 Data Path in Initialize Mode 2 Seiko Epson Corporation 22-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 292 %rd ← res1[31:16] (Remainder) (ext res0[31:0] ÷ {%rd, imm7/16} imm9) ld.ca %rd,imm7 res0[31:0] ← Quotient res1[31:0] ← Remainder %rd ← res1[31:16] (Remainder) res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation 22-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 293: Mac

    COPRO2 Argument 2 16 bits Argument 1 32 bits S1C17 Core Operation result Operation result register 1 register 0 Selector Coprocessor output Flag output Figure 22.5.1 Data Path in Initialize Mode Seiko Epson Corporation 22-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 294 %r0. ld.cw %r0,0x13 ; Sets the mode (operation result read mode and 16 high-order bits output mode 0). ; Loads the 16 high-order bits of the result to %r1. ld.ca %r1,%r0 Seiko Epson Corporation 22-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 295: Reading Operation Results

    %rd,%rs 0x23 %rd ← res1[15:0] ld.ca %rd,imm7 %rd ← res1[15:0] ld.ca %rd,%rs 0x33 %rd ← res1[31:16] ld.ca %rd,imm7 %rd ← res1[31:16] res0: operation result register 0, res1: operation result register 1 Seiko Epson Corporation 22-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 296: Electrical Characteristics

    *5 R is not required when using the DSIO pin as a general-purpose I/O port. *6 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation 23-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 297: Current Consumption

    *1 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 0, CLGOSC1.INV1N[1:0] bits = 0x0, CLGOSC1.CGI1[2:0] bits = 0x0, CLGOSC1. OSDEN bit = 0, C = 0 pF, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), = 7 pF) *2 OSC1 oscillator: CLGOSC1.OSC1SELCR bit = 1...
  • Page 298 IOSC = OFF, OSC1 = 32.768 kHz (crystal oscillator), OSC3 = ON (internal oscillator), Ta = 25 °C, Typ. value 2,400 16 MHz (0x2) 2,000 12 MHz (0x1) 1,600 1,200 ( ) Value of the FLASHCWAIT.RDWAIT[1:0] bits Ta [°C] Seiko Epson Corporation 23-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 299: System Reset Controller (Src) Characteristics

    = 0 V, Ta = -40 to 85 °C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time – – µs Oscillation frequency 25 °C IOSC -40 to 85 °C Seiko Epson Corporation 23-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 300 Internal oscillator CLGOSC1.OSC1SELCR bit = 1 31.04 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) Seiko Epson Corporation 23-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 301 CLGOSC3.OSC3INV[1:0] bits = 0x3 *2 Ceramic resonator = CSBLA_J (manufactured by Murata Manufacturing Co., Ltd., 1 MHz), C = 100 pF OSC3 internal oscillation frequency-temperature characteristic Typ. value 16 MHz 12 MHz Ta [°C] Seiko Epson Corporation 23-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 302: Flash Memory Characteristics

    Pin capacitance P00–07, P10–17, P20–27, P30–37, P40–47, P50–55, P60–67, – – P70–76, PD0–D1, PD3–D4 High level Low level 7.0 V* Input voltage [V] (∗ For over voltage tolerant fail-safe type port) Seiko Epson Corporation 23-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 303: Supply Voltage Detector (Svd3) Characteristics

    1.85 SVDCTL.SVDC[4:0] bits = 0x05 1.95 2.05 SVDCTL.SVDC[4:0] bits = 0x06 2.05 2.15 SVDCTL.SVDC[4:0] bits = 0x07 2.15 2.26 SVDCTL.SVDC[4:0] bits = 0x08 2.24 2.36 SVDCTL.SVDC[4:0] bits = 0x09 2.34 2.46 Seiko Epson Corporation 23-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 304 CLK_SVD3 = 32 kHz, Ta = 25 °C *1 If CLK_SVD3 is configured in the neighborhood of 32 kHz, the SVDINTF.SVDDT bit is masked during the t period and it re- SVDEN tains the previous value. Seiko Epson Corporation 23-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 305: Uart (Uart3) Characteristics

    – – #SPISSn High pulse width – – SDOn output start time – – = 30 pF SDOn output stop time – – = 30 pF *1 C = Pin load Seiko Epson Corporation 23-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 306: I 2 C (I2C) Characteristics

    * After this period, the first clock pulse is generated. SU:DAT SDAn HD:DAT SU:STA SU:STO HIGH HD:STA SCLn HD:STA S: START condition Sr: Repeated START condition 1st clock cycle 9th clock cycle P: STOP condition Seiko Epson Corporation 23-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 307: Lcd Driver (Lcd8A) Characteristics

    *1 Other LCD driver settings: LCD8PWR.LC[3:0] bits = 0xf, CLK_LCD8A = 32 kHz, LCD8TIM1.FRMCNT[4:0] bits = 0x03 (frame fre- quency = 64 Hz) *2 The value is added to the current consumption in HALT/RUN mode. Current consumption increases according to the display contents and panel load. Seiko Epson Corporation 23-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 308 LCD circuit current-load characteristic Ta = 25 °C, Typ. value, LCD8PWR.LC[3:0] bits = 0xf, when a load is connected to the V pin only LCD8PWR.VCSEL bit = 0 LCD8PWR.VCSEL bit = 1 [µA] Seiko Epson Corporation 23-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 309: R/F Converter (Rfc) Characteristics

    = 100 kW, Ta = 25 °C, Typ. value 10,000 10,000 1,000 1,000 5.5 V 5.5 V 3.6 V 3.6 V 1.8 V 1.8 V ∆f ∆f /∆IC /∆IC RFCLK RFCLK 1,000 10,000 1,000 10,000 100,000 [kΩ] [pF] Seiko Epson Corporation 23-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 310: 12-Bit A/D Converter (Adc12A) Characteristics

    *1 The Max. value is the value when the A/D conversion clock frequency f = 2,000 kHz. CLK_ADC12A *2 Integral nonlinearity is measured at the end point line. *3 The error will be increased according to the potential difference between V and VREFAn. Seiko Epson Corporation 23-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 311: Temperature Sensor/Reference Voltage Generator (Tsrvr) Characteristics

    – – µs TEMP 0x1–0x3 TSRVRnVCTL.VREFAMD[1:0] Invalid Valid VREFAn VREFA TSRVRnTCTL.TEMPEN Invalid Valid Temperature sensor output TEMP Temperature sensor output voltage-temperature characteristic = 2.2 to 5.5 V, Typ. value Ta [°C] Seiko Epson Corporation 23-16 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 312: Basic External Connection Diagram

    VREFA *1: For Flash programming *2: When the internal LCD power supply is used (S1C17M31/M33/M34) *3: When OSC1 crystal oscillator is selected (S1C17M30/M32/M33/M34) *4: When OSC3 crystal/ceramic oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation...
  • Page 313 Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
  • Page 314: Package

    25 PACKAGE 25 Package TQFP12-48PIN (P-TQFP048-0707-0.50) [S1C17M30/M31] (Unit: mm) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.7 Figure 25.1 QFP12-48PIN Package Dimensions Seiko Epson Corporation 25-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 315 25 PACKAGE TQFP13-64PIN (P-TQFP064-1010-0.50) [S1C17M32/M34] (Unit: mm) INDEX 0.17 /0.27 0.09 /0.2 0° /10° /0.75 Figure 25.2 QFP13-64PIN Package Dimensions Seiko Epson Corporation 25-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 316 25 PACKAGE QFP14-80PIN (P-LQFP080-1212-0.50) [S1C17M33] (Unit: mm) INDEX 0.13 /0.27 0.09 /0.2 0° /10° /0.75 Figure 25.3 QFP14-80PIN Package Dimensions Seiko Epson Corporation 25-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 317: Appendix A List Of Peripheral Circuit Control Registers

    – 5–4 CLKDIV[1:0] R/WP 3–2 – – 1–0 CLKSRC[1:0] R/WP 0x4042 CLGOSC 15–12 – – – (CLG Oscillation EXOSCSLPC Control Register) OSC3SLPC OSC1SLPC IOSCSLPC 7–4 – – EXOSCEN OSC3EN OSC1EN IOSCEN Seiko Epson Corporation AP-A-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 318 5–0 IOSCAJ[5:0] R/WP * Determined by factory adjustment. 0x4054 CLGTRIM2 15–8 – 0x00 – – (CLG Oscillation 7–6 – – Frequency Trimming 5–0 OSC1AJ[5:0] R/WP * Determined by factory Register 2) adjustment. Seiko Epson Corporation AP-A-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 319 15–11 – 0x00 – – (ITC Interrupt Level 10–8 ILV19[2:0] Synchronous serial interface Setup Register 9) Ch.1 interrupt (ILVSPIA_1) 7–3 – 0x00 – – 2–0 ILV18[2:0] 16-bit timer Ch.2 interrupt (ILVT16_2) Seiko Epson Corporation AP-A-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 320 (RTC Second Alarm 14–12 RTCSHA[2:0] Register) 11–8 RTCSLA[3:0] 7–0 – 0x00 – 0x40c4 RTCALM2 – – – (RTC Hour/Minute RTCAPA Alarm Register) 13–12 RTCHHA[1:0] 11–8 RTCHLA[3:0] – – 6–4 RTCMIHA[2:0] 3–0 RTCMILA[3:0] Seiko Epson Corporation AP-A-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 321 0x40d0 RTCINTF RTCTRMIF Cleared by writing 1. (RTC Interrupt Flag SW1IF Register) SW10IF SW100IF 11–9 – – – ALARMIF Cleared by writing 1. 1DAYIF 1HURIF 1MINIF 1SECIF 1_2SECIF 1_4SECIF 1_8SECIF 1_32SECIF Seiko Epson Corporation AP-A-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 322 15–8 – 0x00 – – (T16 Ch.0 Mode 7–1 – 0x00 – Register) TRMD 0x4164 T16_0CTL 15–9 – 0x00 – – (T16 Ch.0 Control PRUN Register) 7–2 – 0x00 – PRESET MODEN Seiko Epson Corporation AP-A-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 323: Flash Controller (Flashc)

    ✓ P0OEN4 ✓ ✓ ✓ ✓ ✓ P0OEN3 ✓ ✓ ✓ ✓ ✓ P0OEN2 ✓ ✓ ✓ ✓ ✓ P0OEN1 ✓ ✓ ✓ ✓ ✓ P0OEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 324 ✓ P0CHATEN4 ✓ ✓ ✓ ✓ ✓ P0CHATEN3 ✓ ✓ ✓ ✓ ✓ P0CHATEN2 ✓ ✓ ✓ ✓ ✓ P0CHATEN1 ✓ ✓ ✓ ✓ ✓ P0CHATEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 325 ✓ P1OEN4 – – ✓ ✓ ✓ P1OEN3 – ✓ ✓ ✓ ✓ P1OEN2 – ✓ ✓ ✓ ✓ P1OEN1 ✓ ✓ ✓ ✓ ✓ P1OEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 326 ✓ P1CHATEN4 – – ✓ ✓ ✓ P1CHATEN3 – ✓ ✓ ✓ ✓ P1CHATEN2 – ✓ ✓ ✓ ✓ P1CHATEN1 ✓ ✓ ✓ ✓ ✓ P1CHATEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 327 ✓ P2OEN4 – – ✓ ✓ ✓ P2OEN3 ✓ ✓ ✓ ✓ ✓ P2OEN2 ✓ ✓ ✓ ✓ ✓ P2OEN1 ✓ ✓ ✓ ✓ ✓ P2OEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 328 ✓ P2CHATEN4 – – ✓ ✓ ✓ P2CHATEN3 ✓ ✓ ✓ ✓ ✓ P2CHATEN2 ✓ ✓ ✓ ✓ ✓ P2CHATEN1 ✓ ✓ ✓ ✓ ✓ P2CHATEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 329 ✓ P3OEN4 ✓ ✓ ✓ ✓ ✓ P3OEN3 ✓ ✓ ✓ ✓ ✓ P3OEN2 ✓ ✓ ✓ ✓ ✓ P3OEN1 ✓ ✓ ✓ ✓ ✓ P3OEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 330 ✓ P3CHATEN4 ✓ ✓ ✓ ✓ ✓ P3CHATEN3 ✓ ✓ ✓ ✓ ✓ P3CHATEN2 ✓ ✓ ✓ ✓ ✓ P3CHATEN1 ✓ ✓ ✓ ✓ ✓ P3CHATEN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 331 ✓ P4OEN4 – – – – ✓ P4OEN3 – – – – ✓ P4OEN2 – – – – ✓ P4OEN1 – – ✓ ✓ ✓ P4OEN0 – – ✓ ✓ ✓ Seiko Epson Corporation AP-A-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 332 ✓ P4CHATEN4 – – – – ✓ P4CHATEN3 – – – – ✓ P4CHATEN2 – – – – ✓ P4CHATEN1 – – ✓ ✓ ✓ P4CHATEN0 – – ✓ ✓ ✓ Seiko Epson Corporation AP-A-16 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 333 ✓ P5OEN4 – – – ✓ ✓ P5OEN3 – – – – ✓ P5OEN2 – – – – ✓ P5OEN1 – – – – ✓ P5OEN0 – – – – ✓ Seiko Epson Corporation AP-A-17 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 334 ✓ P5SEL4 – – – ✓ ✓ P5SEL3 – – – – ✓ P5SEL2 – – – – ✓ P5SEL1 – – – – ✓ P5SEL0 – – – – ✓ Seiko Epson Corporation AP-A-18 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 335 ✓ P6REN4 ✓ ✓ ✓ ✓ ✓ P6REN3 ✓ ✓ ✓ ✓ ✓ P6REN2 ✓ ✓ ✓ ✓ ✓ P6REN1 ✓ ✓ ✓ ✓ ✓ P6REN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-19 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 336 ✓ ✓ ✓ 7–6 P63MUX[1:0] ✓ ✓ ✓ ✓ ✓ 5–4 P62MUX[1:0] ✓ ✓ ✓ ✓ ✓ 3–2 P61MUX[1:0] ✓ ✓ ✓ ✓ ✓ 1–0 P60MUX[1:0] ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-20 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 337 1. P7IF4 – – – ✓ ✓ P7IF3 ✓ ✓ ✓ ✓ ✓ P7IF2 ✓ ✓ ✓ ✓ ✓ P7IF1 ✓ ✓ ✓ ✓ ✓ P7IF0 – – – – ✓ Seiko Epson Corporation AP-A-21 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 338 – ✓ ✓ ✓ ✓ ✓ PDIN3 ✓ ✓ ✓ ✓ ✓ – – – – – – – PDIN1 ✓ ✓ ✓ ✓ ✓ PDIN0 ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-22 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 339 ✓ P4INT ✓ ✓ ✓ ✓ ✓ P3INT ✓ ✓ ✓ ✓ ✓ P2INT ✓ ✓ ✓ ✓ ✓ P1INT ✓ ✓ ✓ ✓ ✓ P0INT ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-23 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 340 Port Multiplexer 10–8 P21PERISEL[2:0] ✓ ✓ ✓ ✓ ✓ Setting Register) 7–5 P20PPFNC[2:0] ✓ ✓ ✓ ✓ ✓ 4–3 P20PERICH[1:0] ✓ ✓ ✓ ✓ ✓ 2–0 P20PERISEL[2:0] ✓ ✓ ✓ ✓ ✓ Seiko Epson Corporation AP-A-24 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 341 Address Register name Bit name Initial Reset Remarks 0x4380 UA0CLK 15–9 – 0x00 – – (UART3 Ch.0 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-25 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 342 – (UART3 Ch.0 Inter- – – rupt Enable Register) TENDIE FEIE PEIE OEIE RB2FIE RB1FIE TBEIE 0x4390 UA0CAWF 15–8 – 0x00 – – (UART3 Ch.0 Carrier 7–0 CRPER[7:0] 0x00 Waveform Register) Seiko Epson Corporation AP-A-26 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 343 (SPIA Ch.0 Control 7–2 – 0x00 – Register) SFTRST MODEN 0x43b4 SPI0TXD 15–0 TXD[15:0] 0x0000 – (SPIA Ch.0 Transmit Data Register) 0x43b6 SPI0RXD 15–0 RXD[15:0] 0x0000 – (SPIA Ch.0 Receive Data Register) Seiko Epson Corporation AP-A-27 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 344 MODEN 0x43cc I2C0TXD 15–8 – 0x00 – – (I2C Ch.0 Transmit 7–0 TXD[7:0] 0x00 Data Register) 0x43ce I2C0RXD 15–8 – 0x00 – – (I2C Ch.0 Receive 7–0 RXD[7:0] 0x00 Data Register) Seiko Epson Corporation AP-A-28 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 345 Counter Data Register) 0x5006 T16B0TC 15–0 TC[15:0] 0x0000 – (T16B Ch.0 Timer Counter Data Register) 0x5008 T16B0CS 15–8 – 0x00 – – (T16B Ch.0 Counter 7–4 – – Status Register) CAPI1 CAPI0 UP_DOWN Seiko Epson Corporation AP-A-29 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 346 16-bit PWM Timer (T16B) Ch.1 Address Register name Bit name Initial Reset Remarks 0x5040 T16B1CLK 15–9 – 0x00 – – (T16B Ch.1 Clock DBRUN Control Register) 7–4 CLKDIV[3:0] – – 2–0 CLKSRC[2:0] Seiko Epson Corporation AP-A-30 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 347 14–12 CBUFMD[2:0] Capture 0 Control 11–10 CAPIS[1:0] Register) 9–8 CAPTRG[1:0] – – TOUTMT TOUTO 4–2 TOUTMD[2:0] TOUTINV CCMD 0x5052 T16B1CCR0 15–0 CC[15:0] 0x0000 – (T16B Ch.1 Compare/ Capture 0 Data Register) Seiko Epson Corporation AP-A-31 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 348 – Status Register) CAPI1 CAPI0 UP_DOWN 0x508a T16B2INTF 15–8 – 0x00 – – (T16B Ch.2 Interrupt 7–6 – – Flag Register) CAPOW1IF Cleared by writing 1. CMPCAP1IF CAPOW0IF CMPCAP0IF CNTMAXIF CNTZEROIF Seiko Epson Corporation AP-A-32 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 349 Address Register name Bit name Initial Reset Remarks 0x5200 UA1CLK 15–9 – 0x00 – – (UART3 Ch.1 Clock DBRUN Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-33 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 350 – (UART3 Ch.1 Inter- – – rupt Enable Register) TENDIE FEIE PEIE OEIE RB2FIE RB1FIE TBEIE 0x5210 UA1CAWF 15–8 – 0x00 – – (UART3 Ch.1 Carrier 7–0 CRPER[7:0] 0x00 Waveform Register) Seiko Epson Corporation AP-A-34 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 351 (SPIA Ch.1 Control 7–2 – 0x00 – Register) SFTRST MODEN 0x5274 SPI1TXD 15–0 TXD[15:0] 0x0000 – (SPIA Ch.1 Transmit Data Register) 0x5276 SPI1RXD 15–0 RXD[15:0] 0x0000 – (SPIA Ch.1 Receive Data Register) Seiko Epson Corporation AP-A-35 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 352 IR Remote Controller (REMC3) Address Register name Bit name Initial Reset Remarks 0x5320 REMCLK 15–9 – 0x00 – – (REMC3 Clock Con- DBRUN trol Register) 7–4 CLKDIV[3:0] 3–2 – – 1–0 CLKSRC[1:0] Seiko Epson Corporation AP-A-36 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 353 0x00 – – (LCD8A Control 7–2 – 0x00 – Register) LCDDIS MODEN 0x5404 LCD8TIM1 15–12 – – – (LCD8A Timing 11–8 FRMCNT[3:0] Control Register 1) 7–3 – 0x00 – 2–0 LDUTY[2:0] Seiko Epson Corporation AP-A-37 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 354 Control Register) 7–6 – – 5–4 CLKDIV[1:0] 3–2 – – 1–0 CLKSRC[1:0] 0x5442 RFC0CTL 15–9 – 0x00 – – (RFC Ch.0 Control RFCLKMD Register) CONEN EVTEN 5–4 SMODE[1:0] 3–1 – – MODEN Seiko Epson Corporation AP-A-38 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 355 5–4 SMODE[1:0] Setting to 0x1 is invalid. 3–1 – – – MODEN 0x5464 RFC1TRG 15–8 – 0x00 – – (RFC Ch.1 Oscillation 7–3 – 0x00 – Trigger Register) SSENB SSENA SREF Seiko Epson Corporation AP-A-39 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 356 (T16 Ch.3 Interrupt 7–1 – 0x00 – Flag Register) UFIF Cleared by writing 1. 0x548c T16_3INTE 15–8 – 0x00 – – (T16 Ch.3 Interrupt 7–1 – 0x00 – Enable Register) UFIE Seiko Epson Corporation AP-A-40 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 357 S1C17M33 only Register) AD3OVIE AD2OVIE AD1OVIE – AD0OVIE 7–6 – – AD5CIE AD4CIE S1C17M33 only AD3CIE AD2CIE AD1CIE – AD0CIE 0x54ac ADC12_0AD0D 15–0 AD0D[15:0] 0x0000 – (ADC12A Ch.0 Result Register 0) Seiko Epson Corporation AP-A-41 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 358: Debugger (Dbg)

    Generator Control 1–0 VREFAMD[1:0] Register) 0xffff90 Debugger (DBG) Address Register name Bit name Initial Reset Remarks 0xffff90 DBRAM 31–24 – 0x00 – – (Debug RAM Base 23–0 DBRAM[23:0] 0x00 Register) 07c0 Seiko Epson Corporation AP-A-42 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 359: Appendix B Power Saving

    • Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation AP-B-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 360: Other Power Saving Methods

    Note, however, that the load characteristic becomes worse. • Setting the LCD voltage regulator into heavy load protection mode (LCD8PWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C17M30/M31/M32/M33/M34...
  • Page 361: Appendix C Mounting Precautions

    ± 1 V. The C should be placed as close to the V pin as possible and use a sufficiently thick wiring pattern that allows current of several tens of mA to flow. Seiko Epson Corporation AP-C-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 362: Power Supply Circuit

    (display off). The unused SEGx and COMx pins that are not required to connect with the LCD panel should be configured as a general-purpose/peripheral circuit I/O port even if the LCD driver is used. Seiko Epson Corporation AP-C-2 S1C17M30/M31/M32/M33/M34...
  • Page 363 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 364: Appendix D Measures Against Noise

    • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation AP-D-1 S1C17M30/M31/M32/M33/M34...
  • Page 365 The resistance value should be determined by evaluating it on the mounting board. When connecting a power supply directly to the VREFA pin, insert a 100 W resistor in series. This resistance does not affect the A/D converter characteristics. Seiko Epson Corporation AP-D-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 366: Appendix E Initialization Routine

    %r1, 0x41b0 ; FLASHC register address ; Flash read wait cycle Xld.a %r0, 0x00 ; 0x00 = No wait ...(5) ld.b [%r1], %r0 ; [0x41b0] <= 0x00 ; ===== Main routine ========================================= Seiko Epson Corporation AP-E-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 367: Interrupt Handler

    “intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
  • Page 368: Appendix F Eeprom Function

    APPENDIX F EEPROM FUNCTION Appendix F EEPROM Function The S1C17M30/M31/M32/M33/M34 allows use of a part of the Flash area or a dedicated area as an EEPROM by implementing the “S1C17M30/M31/M32/M33/M34 EEPROM Emulation Library.” S1C17M30 S1C17M31 S1C17M32 S1C17M33 S1C17M34 EEPROM Fixed...
  • Page 369: Revision History

    REVISION HISTORY Revision History Code No. Page Contents 413495600 New establishment 413495601 P1-1, Descriptions on the EEPROM emulation were added. PAP-F-1 P6-6 Reading input data from a GPIO port Deleted the note. Note: The PxDAT.PxINy bit retains the input port status at 1 clock before being read from the CPU. 413495602 1-2 to 3 1.1 Features...
  • Page 370 REVISION HISTORY Code No. Page Contents 413495602 24-1 24 Basic External Connection Diagram for Flash programming → 2.4 V to 5.5 V 25-1 to 3 25 Package A JEITA name was added to the package name. AP-A-23 Appendix A List of Peripheral Circuit Control Registers PDIOEN (Pd Port Enable Register) Modified the register table.
  • Page 371 Phone: +86-755-3299-0588 Fax: +86-755-3299-0560 Epson Europe Electronics GmbH Riesstrasse 15, 80992 Munich, Germany Epson Taiwan Technology & Trading Ltd. Phone: +49-89-14005-0 Fax: +49-89-14005-110 15F, No. 100, Songren Rd, Sinyi Dist, Taipei City 110, Taiwan Phone: +886-2-8786-6688 Epson Singapore Pte., Ltd.

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