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Epson evaluation board/kit or development tool is intended for use by an electronic engineer and is not a consumer product. The user should use it properly and in a safe manner. Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed by the use of it.
PREFACE Preface This is a technical manual for designers and programmers who develop a product using the S1C17M30/M31/ M32/M33/M34. This document describes the functions of the IC, embedded peripheral circuit operations, and their control methods. For the CPU functions and instructions, refer to the “S1C17 Family S1C17 Core Manual.” For the functions and operations of the debugging tools, refer to the respective tool manuals.
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B.2 Other Power Saving Methods ..................AP-B-2 Appendix C Mounting Precautions ................AP-C-1 Appendix D Measures Against Noise ................ AP-D-1 Appendix E Initialization Routine ................AP-E-1 Appendix F EEPROM Function ................... AP-F-1 Revision History Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
16-bit CPU. It is suitable for battery-driven applications that require an LCD display and a temperature measurement function. The S1C17M30/M31/M32/M33/M34 allows use of a part of the Flash area or a dedicated area as an EEPROM by implementing a specific library. For more information, refer to “Appendix F EEPROM Function.”...
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Flash 2.4 to 5.5 V (When V (7.5 V) is supplied externally) programming 2.4 to 5.5 V (When V is generated internally) Operating temperature Operating temperature range -40 to 85 °C Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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✓ ✓ ✓ ✓ ✓ OSC4 OSC3 oscillator circuit output ✓ ✓ ✓ ✓ ✓ Note: In the peripheral circuit descriptions, the assigned signal name is used as the pin name. Seiko Epson Corporation 1-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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16-bit PWM timer (T16B) TOUTn0/CAPn0 n = 0, 1, 2 T16B Ch.n PWM output/capture input 0 TOUTn1/CAPn1 T16B Ch.n PWM output/capture input 1 Note: Do not assign a function to two or more pins simultaneously. Seiko Epson Corporation 1-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Use the V regulator in automatic mode when no spe- cial control is required. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
#RESET pin, so the pin can be left open. For the #RESET pin characteris- tics, refer to “#RESET pin characteristics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Table 2.2.4.1 lists the reset groups. For the reset group to initialize the registers and con- trol bits, refer to the “CPU and Debugger” chapter or “Control Registers” in each peripheral circuit chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34...
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation. • Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state. Figure 2.3.1.1 shows the CLG configuration. Table 2.3.1.1 CLG Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30...
2.3.3 Clock Sources IOSC oscillator circuit The IOSC oscillator circuit features a fast startup and no external parts are required for oscillating. Figure 2.3.3.1 shows the configuration of the IOSC oscillator circuit. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Figure 2.3.3.2 OSC1 Oscillator Circuit Configuration For the recommended parts and the oscillation characteristics, refer to the “Basic External Connection Dia- gram” chapter and “OSC1 oscillator circuit characteristics” in the “Electrical Characteristics” chapter, respec- tively. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
EXOSC has no oscillation stabilization waiting circuit included, therefore, it must be enabled when a stabilized clock is being supplied. For the input clock characteristics, refer to “EXOSC external clock input characteris- tics” in the “Electrical Characteristics” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Figure 2.3.4.2 shows an operation example when the oscillation startup control circuit is used. (1) CLGOSC1.OSC1BUP bit = 0 (startup boosting operation disabled) Oscillator circuit enable (CLGOSC.OSC1EN) Oscillation inverter INV1N[1:0] setting gain Oscillation waveform Normal operation Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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In addition to the above, configure the following bits when using the crystal/ceramic oscillator: - CLGOSC3.OSC3INV[1:0] bits (Set oscillation inverter gain) Configure the following bits when using the internal oscillator: - CLGOSC3.OSC3FQ bit (Select oscillation frequency) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This allows flexible clock control according to the wake-up process. Configure the clock using the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit to enable this function. Seiko Epson Corporation 2-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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10 ms is required. When OSC3CLK is be- ing used as the system clock or a peripheral circuit clock, do not use the auto-trimming function. Seiko Epson Corporation 2-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev.
RUN mode. HALT mode is classified into “IOSC HALT,” “OSC1 HALT,” “OSC3 HALT,” and “EXOSC HALT” by the SYSCLK clock source. Seiko Epson Corporation 2-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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CLGSCLK.CLKSRC[1:0] = 0x3 EXOSC HALT OSC3 OSC3 ∗ In RUN and HALT modes, the clock sources not used HALT as SYSCLK can be all disabled. Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram Seiko Epson Corporation 2-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
These bits set the division ratio of the clock source to determine the SYSCLK frequency. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the SYSCLK clock source. When a currently stopped clock source is selected, it will automatically start oscillating or clock input. Seiko Epson Corporation 2-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
” in the “Electrical Characteristics” chapter. GI1C Bits 7–6 INV1B[1:0] These bits set the oscillation inverter gain that will be applied at boost startup of the OSC1 crystal os- cillator circuit. Seiko Epson Corporation 2-17 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
These bits set the frequency trimming value for the OSC3 internal oscillator circuit. This setting does not affect the OSC3 crystal/ceramic oscillation frequency. Table 2.6.11 Oscillation Frequency Trimming Setting of OSC3 Internal Oscillator Circuit CLGTRIM1.OSC3AJ[6:0] bits OSC3 internal oscillator frequency 0x7f High 0x00 Seiko Epson Corporation 2-21 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
“Electrical Characteristics” chapter can be guaranteed. Be aware that the frequency characteristic may not be satisfied when this setting is altered. When altering this setting, always make sure that the OSC1 oscillator circuit is inactive. Seiko Epson Corporation 2-22 S1C17M30/M31/M32/M33/M34...
3 CPU AND DEBUGGER 3 CPU and Debugger 3.1 Overview This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the CPU core are listed below. • Seiko Epson original 16-bit RISC processor...
DBRUN bit, refer to “Clock Supply in DEBUG Mode” in each peripheral circuit chapter. DE- BUG mode continues until a cancel command is sent from the personal computer or the CPU executes the retd in- struction. Neither hardware interrupts nor NMI are accepted during DEBUG mode. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
For the recommended pull-up resistor value, refer to “Recommended Operating Conditions, DSIO pull-up resis- tor R ” in the “Electrical Characteristics” chapter. R is not required when using the DSIO pin as a general- purpose I/O port pin. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit. Bit 0 PSRN The value (0 or 1) of the PSR N (negative) flag can be read out with this bit. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
– 23–0 DBRAM[23:0] *1 Debugging work area start address Bits 31–24 Reserved Bits 23–0 DBRAM[23:0] The start address of the debugging work area (64 bytes) can be read out with these bits. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Access size designated by the CPU instructions (e.g., ld %rd, [%rb] → 16-bit data transfer) Table 4.2.1 lists numbers of bus access cycles by different device size and access size. The peripheral circuits can be accessed with an 8-bit, 16-bit, or 32-bit instruction. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The number of bus access cycles for reading can be configured using the FLASHCWAIT.RDWAIT[1:0] bits. Select a setting for higher frequency than the system clock. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The embedded display data RAM is used to store display data for the LCD driver. Areas unused for display data in the display data RAM can be used as a general-purpose RAM. For specific information on the display data RAM, refer to “Display Data RAM” in the “LCD Driver” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
0x54c2 TSRVR0VCTL TSRVR Ch.0 Reference Voltage Generator Control Register *1 Cannot be used in the S1C17M30. *2 Cannot be used in the S1C17M31. *3 Cannot be used in the S1C17M32. *4 Cannot be used in the S1C17M34. 4.6.1 System-Protect Function The system-protect function protects control registers and bits from writings.
FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles System clock frequency 17.12 MHz (max.) 17.12 MHz (max.) 12.6 MHz (max.) 6.3 MHz (max.) Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
ITC if the status is changed to interrupt enabled when the interrupt flag is 1. For specific information on causes of interrupts, interrupt flags, and interrupt enable bits, refer to the respective pe- ripheral circuit descriptions. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
(0–7) to be set to the IL[2:0] bits in the PSR. The software inter- rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation as that of the hardware interrupt. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Note: ‘x’, which is used in the port names Pxy, register names, and bit names, refers to a port group (x = 0, 1, 2, ··· , d) and ‘y’ refers to a port number (y = 0, 1, 2, ··· , 7). Figure 6.1.1 shows the configuration of PPORT. Table 6.1.1 Port Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30...
Figure 6.2.1 I/O Cell Configuration Refer to “Pin Descriptions” in the “Overview” chapter for the cell type, either the over voltage tolerant fail-safe type I/O cell or the standard I/O cell, included in each port. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
(Clock division ratio selection = Clock frequency setting) 4. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Settings in Step 3 determine the input sampling time of the chattering filter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
When using the Pxy port pin as a general-purpose output pin, perform the following software initial settings: 1. Set the PxIOEN.PxOENy bit to 1. (Enable output) 2. Set the PxMODSEL.PxSELy bit to 0. (Enable GPIO function) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
6.4.2 Port Input/Output Control Peripheral I/O function control The port for which a peripheral I/O function is selected is controlled by the peripheral circuit. For more infor- mation, refer to the respective peripheral circuit chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Clearing PxINTF.PxIFy Interrupt edge selection Port input interrupts will occur at the falling edge of the input signal when setting the PxINTCTL.PxEDGEy bit to 1, or the rising edge when setting to 0. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
*2: The bit configuration differs depending on the port group. Bits 15–8 PxIEN[7:0] These bits enable/disable the GPIO port input. 1 (R/W): Enable (The port pin status is input.) 0 (R/W): Disable (Input data is fixed at 0.) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Initial Reset Remarks PxINTCTL 15–8 PxEDGE[7:0] 0x00 – 7–0 PxIE[7:0] 0x00 *1: This register is effective when the GPIO function is selected. *2: The bit configuration differs depending on the port group. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
*1: The bit configuration differs depending on the port group. *2: The initial value may be changed by the port. Bits 15–14 Px7MUX[1:0] Bits 1–0 Px0MUX[1:0] These bits select the peripheral I/O function to be assigned to each port pin. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The PPORT operating clock should be configured by selecting the clock source using the PCLK. CLKSRC[1:0] bits and the clock division ratio using the PCLK.CLKDIV[3:0] bits as shown in Table 6.6.3. These settings determine the input sampling time of the chattering filter. Seiko Epson Corporation 6-10 S1C17M30/M31/M32/M33/M34...
A port generated an interrupt 0 (R): No port generated an interrupt The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt is cleared. Seiko Epson Corporation 6-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
4. Initialize the peripheral circuit. 5. Set the PxFNCSEL.PxyMUX[1:0] bits of the I/O port to 0x1. (Select peripheral I/O function 1) 6. Set the PxMODSEL.PxSELy bit of the I/O port to 1. (Enable peripheral I/O function) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Note: Do not assign a peripheral input function to two or more I/O ports. Although the I/O ports output the same waveforms when an output function is assigned to two or more I/O port, a skew oc- curs due to the internal delay. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
CLK_WDT2 supply is suspended, the register retains the status before DEBUG mode was entered. If the WDTCLK.DBRUN bit = 1, the CLK_WDT2 supply is not suspended and WDT2 will keep operating in DE- BUG mode. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
1. Write 0x0096 to the MSCPROT.PROT[15:0] bits. (Remove system protection) 2. Write 0xa to the WDTCTL.WDTRUN[3:0] bits. (Stop WDT2) 3. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection) Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
IOSC OSC1 OSC3 EXOSC 1/65,536 1/128 1/65,536 1/32,768 1/32,768 1/16,384 1/16,384 1/8,192 1/8,192 (Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
WDT2 should also be reset concurrently when running WDT2. WDT2 Counter Compare Match Register Register name Bit name Initial Reset Remarks WDTCMP 15–10 – 0x00 – – 9–0 CMP[9:0] 0x3ff R/WP Bits 15–10 Reserved Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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These bits set the NMI/reset generation cycle. The value set in this register is compared with the 10-bit counter value while WDT2 is running, and an NMI or reset is generated when they are matched. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
* Indicates the status when the pin is configured for RTCA. If the port is shared with the RTCA output function and other functions, the RTCA function must be assigned to the port. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
3. Write 1 to the RTCINTF.ALARMIF bit to clear the alarm interrupt flag. 4. Write 1 to the RTCINTE.ALARMIE bit to enable alarm interrupts. When the real-time clock counter reaches the alarm time set in Step 2, an alarm interrupt occurs. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
9.4.4 Stopwatch Count-up Pattern The stopwatch consists of 1/100-second and 1/10-second counters and these counters perform counting up in incre- ments of approximate 1/100 and 1/10 seconds with the count-up patterns shown in Figure 9.4.4.1. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
1 Hz counter value. • An alarm interrupt occurs after a lapse of 1/256 second from matching between the AM/PM (in 12H mode), hour, minute, and second counter value and the alarm setting value. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Depending on these operation timings, the +1 second correction may be executed after the count-up operation resumes. For more information on the +1 second correction, refer to “Real-Time Clock Counter Operations.” Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The RTCALM1.RTCSHA[2:0] bits and the RTCALM1.RTCSLA[3:0] bits set the 10-second digit and 1-second digit of the alarm time, respectively. A value within 0 to 59 seconds can be set in BCD code as shown in Table 9.6.1. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
SWRUN Bits 15–12 BCD10[3:0] Bits 11–8 BCD100[3:0] The 1/10-second and 1/100-second digits of the stopwatch counter can be read as a BCD code from the RTCSWCTL.BCD10[3:0] bits and the RTCSWCTL.BCD100[3:0] bits, respectively. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
1-second digit of the second counter, respectively. The setting/read values are a BCD code within the range from 0 to 59. Note: Be sure to avoid writing to the RTCSEC.RTCSH[2:0]/RTCSL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Seiko Epson Corporation S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
1 to 12 in 12H mode or 0 to 23 in 24H mode. Note: Be sure to avoid writing to the RTCHUR.RTCHH[1:0]/RTCHL[3:0] bits while the RTCCTL. RTCBSY bit = 1. Bit 7 Reserved Seiko Epson Corporation 9-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
These bits are used to set and read day of the week. The day of the week counter is a base-7 counter and the setting/read values are 0x0 to 0x6. Table 9.6.2 lists the correspondence between the count value and day of the week. Seiko Epson Corporation 9-11 S1C17M30/M31/M32/M33/M34...
- Low power supply voltage detection count function to generate an inter- rupt/reset when low power supply voltage is successively detected the number of times specified. - Continuous operation is also possible. Figure 10.1.1 shows the configuration of SVD3. Table 10.1.1 SVD3 Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31 S1C17M32...
If the CLGOSC.xxxxSLPC bit for the CLK_SVD3 clock source is 1, the CLK_SVD3 clock source is deactivated during SLEEP mode and SVD3 stops with the register settings maintained at those before entering SLEEP mode. After the CPU returns to normal mode, CLK_SVD3 is supplied and the SVD3 operation resumes. Seiko Epson Corporation 10-2 S1C17M30/M31/M32/M33/M34...
SVDCTL.MODEN bit = 1, wait for at least SVD circuit response time SVD_EXT before reading the SVDINTF.SVDDT bit (refer to “Supply Voltage Detector Characteristics, SVD circuit re- sponse time t ” in the “Electrical Characteristics” chapter). Seiko Epson Corporation 10-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
SVDIF bit). An interrupt request is sent to the interrupt controller only when the SVDINTF.SVDIF bit is set while the interrupt is enabled by the SVDINTE.SVDIE bit. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 10-4 S1C17M30/M31/M32/M33/M34...
Bit 7 Reserved Bits 6–4 CLKDIV[2:0] These bits select the division ratio of the SVD3 operating clock. Bits 3–2 Reserved Bits 1–0 CLKSRC[1:0] These bits select the clock source of SVD3. Seiko Epson Corporation 10-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
0x01 ↓ 0x00 For the configurable range and voltage values, refer to “Supply Voltage Detector Characteristics, SVD detection voltage V /EXSVD detection voltage V ” in the “Electrical Characteristics” chapter. SVD_EXT Seiko Epson Corporation 10-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
EXSVD0/1) < SVD detection voltage V or EXSVD detection voltage V SVD_EXT 0 (R): Power supply voltage (V or EXSVD0/1) ≥ SVD detection voltage V or EXSVD detection voltage V SVD_EXT Seiko Epson Corporation 10-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 10-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• A clock source and clock division ratio for generating the count clock are selectable. • Repeat mode or one-shot mode is selectable. • Can generate counter underflow interrupts. Figure 11.1.1 shows the configuration of a T16 channel. Table 11.1.1 T16 Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
(Set reload data (counter preset data)) 5. Set the following bits when using the interrupt: - Write 1 to the T16_nINTF.UFIF bit. (Clear interrupt flag) - Set the T16_nINTE.UFIE bit to 1. (Enable underflow interrupt) Seiko Epson Corporation 11-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
At the same time the counter stops, the T16_ nCTL.PRUN bit is cleared automatically. Select this mode to stop the counter after an interrupt has occurred once, such as for checking a specific lapse of time. Seiko Epson Corporation 11-3 S1C17M30/M31/M32/M33/M34...
This bit indicates the T16 Ch.n underflow interrupt cause occurrence status. 1 (R): Cause of interrupt occurred 0 (R): No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective Seiko Epson Corporation 11-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This bit enables T16 Ch.n underflow interrupts. 1 (R/W): Enable interrupts 0 (R/W): Disable interrupts Note: To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 11-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• Input pin can be pulled up with an internal resistor. • The output pin is configurable as an open-drain output. • Provides the carrier modulation output function. Figure 12.1.1 shows the UART3 configuration. Table 12.1.1 UART3 Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
- UAnCLK.CLKSRC[1:0] bits (Clock source selection) - UAnCLK.CLKDIV[1:0] bits (Clock division ratio selection = Clock frequency setting) The UART3 operating clock should be selected so that the baud rate generator will be configured easily. Seiko Epson Corporation 12-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
(UAnMOD.STPB bit = 1). Parity function The parity function is configured using the UAnMOD.PREN and UAnMOD.PRMD bits. Table 12.4.1 Parity Function Setting UAnMOD.PREN bit UAnMOD.PRMD bit Parity function Odd parity Even parity Non parity Seiko Epson Corporation 12-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
- Set the interrupt enable bits in the UAnINTE register to 1. * (Enable interrupts) * The initial value of the UAnINTF.TBEIF bit is 1, therefore, an interrupt will occur immediately after the UA- nINTE.TBEIE bit is set to 1. Seiko Epson Corporation 12-4 S1C17M30/M31/M32/M33/M34...
Read the UAnINTF.TBEIF bit UAnINTF.TBEIF = 1 ? Write transmit data to the UAnTXD register Transmit data remained? Wait for an interrupt request (UAnINTF.TBEIF = 1) Figure 12.5.2.2 Data Transmission Flowchart Seiko Epson Corporation 12-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Read receive data (1 byte) from the UAnRXD register the UAnRXD register Read receive data (1 byte) from the UAnRXD register Receive data remained? Receive data remained? Figure 12.5.3.2 Data Reception Flowcharts Seiko Epson Corporation 12-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Writing 1 to the UAnMOD.CAREN bit enables the carrier modulation function allowing carrier modulation wave- forms to be output according to the UAnMOD.PECAR bit setting. Data transmit control is identical to that for nor- mal interface even in this case. Seiko Epson Corporation 12-7 S1C17M30/M31/M32/M33/M34...
The received data that encountered an error is still transferred to the receive data buffer and the UAnINTF.PEIF bit (parity error interrupt flag) is set to 1 when the data becomes ready to read from the UAnRXD register (see the Note on framing error). Seiko Epson Corporation 12-8 S1C17M30/M31/M32/M33/M34...
Notes: • The UAnBR register settings can be altered only when the UAnCTL.MODEN bit = 0. • Do not set the UAnBR.FMD[3:0] bits to a value other than 0 to 3 when the UAnMOD.BRDIV bit = 1. Seiko Epson Corporation 12-11 S1C17M30/M31/M32/M33/M34...
Bits 15–8 Reserved Bits 7–0 RXD[7:0] The receive data buffer can be read through these bits. The receive data buffer consists of a 2-byte FIFO, and older received data is read first. Seiko Epson Corporation 12-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt. • Input pins can be pulled up/down with an internal resistor. Figure 13.1.1 shows the SPIA configuration. Table 13.1.1 SPIA Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30...
16-bit timer channel and converts it to the SPICLKn. The 16-bit timer must be run with an appro- priate reload data set. The SPICLKn frequency (baud rate) and the 16-bit timer reload data are calculated by the equations shown below. Seiko Epson Corporation 13-3 S1C17M30/M31/M32/M33/M34...
1. Assert the slave select signal by controlling the general-purpose output port (if necessary). 2. Check to see if the SPInINTF.TBEIF bit is set to 1 (transmit buffer empty). 3. Write transmit data to the SPInTXD register. Seiko Epson Corporation 13-5 S1C17M30/M31/M32/M33/M34...
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SPInTXD register Transmit data remained? Wait for an interrupt request (SPInINTF.TBEIF = 1) Negate the slave select signal output from a general-purpose port Figure 13.5.2.2 Data Transmission Flowchart in Master Mode Seiko Epson Corporation 13-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
SPInTXD register data written is completed. If no transmit data is written during this period, the data bits input from the SDIn pin are shifted and output from the SDOn pin without being modified. Seiko Epson Corporation 13-8 S1C17M30/M31/M32/M33/M34...
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Data (W) → SPInTXD Data (W) → SPInTXD Software operations SPInRXD → Data (R) SPInRXD → Data (R) Figure 13.5.5.1 Example of Data Transfer Operations in Slave Mode (SPInMOD.CHLN[3:0] bits = 0x7) Seiko Epson Corporation 13-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
“Interrupt Controller” chapter. The SPInINTF register also contains the BSY bit that indicates the SPIA operating status. Figure 13.6.1 shows the SPInINTF.BSY and SPInINTF.TENDIF bit set timings. Seiko Epson Corporation 13-10 S1C17M30/M31/M32/M33/M34...
Note: The SPInMOD register settings can be altered only when the SPInCTL.MODEN bit = 0. SPIA Ch.n Control Register Register name Bit name Initial Reset Remarks SPInCTL 15–8 – 0x00 – – 7–2 – 0x00 – SFTRST MODEN Bits 15–2 Reserved Seiko Epson Corporation 13-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The following shows the correspondence between the bit and interrupt: SPInINTE.OEIE bit: Overrun error interrupt SPInINTE.TENDIE bit: End-of-transmission interrupt SPInINTE.RBFIE bit: Receive buffer full interrupt SPInINTE.TBEIE bit: Transmit buffer empty interrupt Seiko Epson Corporation 13-14 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• The input filter for the SDA and SCL inputs does not comply with the standard for removing noise spikes less than 50 ns. Figure 14.1.1 shows the I2C configuration. Table 14.1.1 I2C Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
• The internal pull-up resistors for the I/O ports cannot be used for pulling up SDA and SCL. • When the I2C is set into master mode, no other master device can be connected to the I bus. Seiko Epson Corporation 14-2 S1C17M30/M31/M32/M33/M34...
14.3.3.1). Note: The I C bus transfer rate is limited to 100 kbit/s in standard mode or 400 kbit/s in fast mode. Do not set a transfer rate exceeding the limit. Seiko Epson Corporation 14-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
- Set the I2CnCTL.MST bit to 0. (Set slave mode) - Set the I2CnCTL.SFTRST bit to 1. (Execute software reset) - Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations) Seiko Epson Corporation 14-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition. When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF bits are both set to 1 same as when a START condition has been generated. Seiko Epson Corporation 14-5 S1C17M30/M31/M32/M33/M34...
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Last data sent? Retry? Write 1 to the I2CnCTL.TXSTOP bit Write data to the I2CnTXD register Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.2.2 Master Mode Data Transmission Flowchart Seiko Epson Corporation 14-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This reading triggers the I2C Ch.n to start subsequent data reception. Generating a STOP or repeated START condition It is the same as the data transmission in master mode. Seiko Epson Corporation 14-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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Read receive data from the I2CnRXD register Write 1 to the I2CnCTL.TXSTOP bit Write 1 to the I2CnCTL.TXSTOP bit Wait for an interrupt request (I2CnINTF.STOPIF = 1) Figure 14.4.3.2 Master Mode Data Reception Flowchart Seiko Epson Corporation 14-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred. 9. Write the first address to the I2CnTXD.TXD[7:1] bits and 1 that represents READ as the data transfer direc- tion to the I2CnTXD.TXD0 bit. 10. Perform data reception. Seiko Epson Corporation 14-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Go to Step 6 when a STOP condition interrupt has occurred. ii. Go to Step 2 when a START condition interrupt has occurred. 6. Clear the I2CnINTF.STOPIF bit and then terminate data sending operations. Seiko Epson Corporation 14-10 S1C17M30/M31/M32/M33/M34...
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A: ACK, A: NACK, Saddr/R: Slave address + R(1), Saddr/W: Slave address + W(0), STARTIF = 1 Data n: 8-bit data Figure 14.4.5.1 Example of Data Sending Operations in Slave Mode Seiko Epson Corporation 14-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
I2C Ch.n sends an ACK and pulls down SCL to low. The received data in the shift register is transferred to the receive data buffer and the I2CnINTF.RBFIF and I2CnINTF.BYTEENDIF bits are both set to 1. Af- ter that, the received data can be read out from the I2CnRXD register. Seiko Epson Corporation 14-12 S1C17M30/M31/M32/M33/M34...
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Wait for an interrupt request (I2CnINTF.RBFIF = 1) Last data received next? Write 1 to the I2CnCTL.TXNACK bit Read receive data from the I2CnRXD register Last data received? Figure 14.4.6.2 Slave Mode Data Reception Flowchart Seiko Epson Corporation 14-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF and I2CnINTF.STARTIF bits to 1. Seiko Epson Corporation 14-14 S1C17M30/M31/M32/M33/M34...
4 <Master mode only> When 1 is written to the I2CnCTL.TX- I2CnINTF.ERRIF = 1 START bit while the I2CnINTF.BSY bit = 0 (Refer to “Automatic Automatic bus clearing I2CnCTL.TXSTART = 0 Bus Clearing Operation.”) failure I2CnINTF.STARTIF = 1 Seiko Epson Corporation 14-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
(Note) The oscillation circuits/external input that are not supported in this IC cannot be selected as the clock source. Note: The I2CnCLK register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-17 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The I2CnOADR.OADR[9:0] bits are effective in 10-bit address mode (I2CnMOD.OADR10 bit = 1), or the I2CnOADR.OADR[6:0] bits are effective in 7-bit address mode (I2CnMOD.OADR10 bit = 0). Note: The I2CnOADR register settings can be altered only when the I2CnCTL.MODEN bit = 0. Seiko Epson Corporation 14-18 S1C17M30/M31/M32/M33/M34...
Bit 0 MODEN This bit enables the I2C operations. 1 (R/W): Enable I2C operations (The operating clock is supplied.) 0 (R/W): Disable I2C operations (The operating clock is stopped.) Seiko Epson Corporation 14-19 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
0 (R): SDA = High level Bit 11 SCLLOW This bit indicates that SCL is set to low level. 1 (R): SCL = Low level 0 (R): SCL = High level Seiko Epson Corporation 14-20 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
- The capture circuit captures counter values using external/software trigger signals and generates interrupts. (Can be used to measure external event periods/cycles.) Figure 15.1.1 shows the T16B configuration. Table 15.1.1 T16B Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31 S1C17M32...
* Indicates the status when the pin is configured for T16B. If the port is shared with the T16B pin and other functions, the T16B input/output function must be assigned to the port before activating T16B. For more information, refer to the “I/O Ports” chapter. Seiko Epson Corporation 15-2 S1C17M30/M31/M32/M33/M34...
Figure 15.3.4.1 Count Timing (During Count Up Operation) Note: When running the counter using the event counter clock, two dummy clocks must be input be- fore the first counting up/down can be performed. Seiko Epson Corporation 15-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
- T16BnCTL.CNTMD[1:0] bits (Select count up/down operation) - T16BnCTL.ONEST bit (Select one-shot/repeat operation) - Set the T16BnCTL.PRESET bit to 1. (Reset counter) - Set the T16BnCTL.RUN bit to 1. (Start counting) Seiko Epson Corporation 15-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
MAX value. If the MAX value is altered to a value smaller than the current counter value, the counter is cleared to 0x0000 and continues counting up to the new MAX value. Seiko Epson Corporation 15-5 S1C17M30/M31/M32/M33/M34...
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MODEN = 1 PRESET = 1 RUN = 1 Software operation Data (W) → MC[15:0] RUN = 1 RUN = 0 Hardware operation 0xffff Count cycle MAX value Counter Time 0x0000 Seiko Epson Corporation 15-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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Data (W) → MC[15:0] RUN = 1 RUN = 1 0xffff MAX value Counter Time 0x0000 RUN = 0 Figure 15.4.2.3 Operations in Repeat Up/Down Count and One-shot Up/Down Count Modes Seiko Epson Corporation 15-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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If the captured data stored in the T16BnCCRm register is overwritten by the next trigger when the T16BnINTF. CMPCAPmIF bit is still set, an overwrite error occurs (the T16BnINTF.CAPOWmIF bit is set). Seiko Epson Corporation 15-14 S1C17M30/M31/M32/M33/M34...
The TOUT signal polarity (active level) can be set using the T16BnCCCTLm.TOUTINV bit. It is set to active high by setting the T16BnCCCTLm.TOUTINV bit to 0 and active low by setting to 1. Figures 15.4.4.2 and 15.4.4.3 show the TOUT output waveforms. Seiko Epson Corporation 15-16 S1C17M30/M31/M32/M33/M34...
Bits 7–4 CLKDIV[3:0] These bits select the division ratio of the T16B Ch.n operating clock (counter clock). Bit 3 Reserved Bits 2–0 CLKSRC[2:0] These bits select the clock source of T16B Ch.n. Seiko Epson Corporation 15-22 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
T16BnCTL.ONEST bit setting (see Table 15.6.2). Bit 3 ONEST This bit selects the counter repeat/one-shot mode. The count mode is configured with this selection and the T16BnCTL.CNTMD[1:0] bit settings (see Table 15.6.2). Seiko Epson Corporation 15-23 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
T16BnCTL.MODEN bit to 1 until the T16BnCS.BSY bit is set to 0 from 1. • Do not set the T16BnMC.MC[15:0] bits to 0x0000. T16B Ch.n Timer Counter Data Register Register name Bit name Initial Reset Remarks T16BnTC 15–0 TC[15:0] 0x0000 – Seiko Epson Corporation 15-24 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This bit indicates the currently set count direction. 1 (R): Count up 0 (R): Count down Bit 0 This bit indicates the counter operating status. 1 (R): Running 0 (R): Idle Seiko Epson Corporation 15-25 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Note: The configuration of the T16BnINTF.CAPOWmIF and T16BnINTF.CMPCAPmIF bits depends on the model. The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. Seiko Epson Corporation 15-26 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The bits corresponding to the comparator/capture circuits that do not exist are read-only bits and are always fixed at 0. • To prevent generating unnecessary interrupts, the corresponding interrupt flag should be cleared before enabling interrupts. Seiko Epson Corporation 15-27 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
These bits select the trigger edge(s) of the trigger signal at which the counter value is captured in the T16BnCCRm register in capture mode (see Table 15.6.4). The T16BnCCCTLm.CAPTRG[1:0] bits are control bits for capture mode and are ineffective in comparator mode. Seiko Epson Corporation 15-28 S1C17M30/M31/M32/M33/M34...
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The signal becomes inactive by the MATCH signal. All count modes TOUTnm The signal becomes inactive by the MATCHm or MATCHm+1 signal. TOUTnm+1 The signal becomes inactive by the MATCHm+1 or MATCHm signal. Seiko Epson Corporation 15-29 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
In capture mode, this register is configured as the capture register and the counter value captured by the capture trigger signal is loaded. Seiko Epson Corporation 15-30 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
IC. The buzzer output duration can also be controlled via software. An output start/stop procedure and the SNDA operations are shown below. Normal buzzer output start/stop procedure 1. Set the SNDSEL.MOSEL[1:0] bits to 0x0. (Set normal buzzer mode) Seiko Epson Corporation 16-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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Buzzer signal frequency [Hz] BZOUT DUTY: Buzzer signal duty ratio [%] However, the following settings are prohibited: • Settings as SNDDAT.SFRQ[7:0] bits ≤ SNDDAT.SLEN[5:0] bits • Settings as SNDDAT.SFRQ[7:0] bits = 0x00 Seiko Epson Corporation 16-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SND- INTF.SBSY bit is cleared to 0. Figure 16.4.3.1 shows a buzzer output timing chart in one-shot buzzer mode. Seiko Epson Corporation 16-6 S1C17M30/M31/M32/M33/M34...
At the same time, the SNDINTF.EDIF bit (sound output completion interrupt flag) is set to 1 and the SNDINTF.SBSY bit is cleared to 0. Figure 16.4.4.1 shows a melody mode operation timing chart. Seiko Epson Corporation 16-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This bit sets whether the SNDA operating clock is supplied in DEBUG mode or not. 1 (R/W): Clock supplied in DEBUG mode 0 (R/W): No clock supplied in DEBUG mode Bit 7 Reserved Seiko Epson Corporation 16-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This bit specifies a tie or slur (continuous play with the previous note) in melody mode. 1 (R/W): Enable tie/slur 0 (R/W): Disable tie/slur This bit is ignored in normal buzzer mode/one-shot buzzer mode. Seiko Epson Corporation 16-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
No cause of interrupt occurred 1 (W): Clear flag 0 (W): Ineffective The following shows the correspondence between the bit and interrupt: SNDINTF.EMIF bit: Sound buffer empty interrupt SNDINTF.EDIF bit: Sound output completion interrupt Seiko Epson Corporation 16-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• Automatic data setting function for continuous data transmission. • Output signal inverting function supporting various formats. • EL lamp drive waveform can be generated for an application example. Figure 17.1.1 shows the REMC3 configuration. Table 17.1.1 REMC3 Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
1. Write 1 to the REMDBCTL.REMCRST bit. (Reset REMC3) 2. Configure the REMCLK.CLKSRC[1:0] and REMCLK.CLKDIV[3:0] bits. (Configure operating clock) 3. Assign the REMC3 output function to the port. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 17-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The REMC3 outputs the logical AND between the carrier signal output from the carrier generator and the data sig- nal output from the data signal generator. Figure 17.4.3.1 shows an example of the output waveform. Seiko Epson Corporation 17-3 S1C17M30/M31/M32/M33/M34...
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The data signal is generated by comparing the values of the 16-bit counter for data signal generation (REM- DBCNT.DBCNT[15:0] bits) that runs with CLK_REMC3 and the setting values of the REMAPLEN. APLEN[15:0] and REMDBLEN.DBLEN[15:0] bits. Figure 17.4.3.3 shows an example of the data signal gen- erated. Seiko Epson Corporation 17-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
(REMDBCTL.TRMD bit = 1), the counter stops automatically when the counter value is matched with the REMDBLEN.DBLEN[15:0] bit-setting value. 17.4.4 Continuous Data Transmission and Compare Buffers Figure 17.4.4.1 shows an operation example of continuous data transmission with the compare buffer enabled. Seiko Epson Corporation 17-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the in- terrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 17-6 S1C17M30/M31/M32/M33/M34...
This bit starts/stops counting by the internal counters (16-bit counter for data signal generation and 8-bit counter for carrier generation). 1 (W): Start counting 0 (W): Stop counting 1 (R): Counting 0 (R): Idle Seiko Epson Corporation 17-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
0x0000 H0/S0 Cleared by writing 1 to the REMDBCTL.REMCRST bit. Bits 15–0 DBCNT[15:0] The current value of the 16-bit counter for data signal generation can be read out through these bits. Seiko Epson Corporation 17-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Transfer to the REMAPLEN buffer has not completed. 0 (R): Transfer to the REMAPLEN buffer has completed. While this bit is set to 1, writing to the REMAPLEN.APLEN[15:0] bits is ineffective. Seiko Epson Corporation 17-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
These bits set the carrier signal cycle. A carrier signal cycle begins with the 8-bit counter for carrier generation = 0x00 and ends when the counter exceeds the REMCARR.CRPER[7:0] bit-setting value. (See Figure 17.4.3.2.) Seiko Epson Corporation 17-11 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This bit enables carrier modulation. 1 (R/W): Enable carrier modulation 0 (R/W): Disable carrier modulation (output data signal only) Note: When carrier modulation is disabled, the REMDBCTL.REMOINV bit should be set to 0. Seiko Epson Corporation 17-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• Includes a power supply for 1/3 bias driving (allows external voltages to be applied). (Note: See the table below.) • Provides the frame signal monitoring output pin. • Can generate interrupts every frame. Figure 18.1.1 shows the LCD8A configuration. Table 18.1.1 LCD8A Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31 S1C17M32...
: LCD8A operating clock frequency [Hz] CLK_LCD8A FRMCNT: LCD8TIM1.FRMCNT[3:0] setting value (0 to 15) LDUTY: LCD8TIM1.LDUTY[2:0] setting value (0 to 7) Table 18.3.4.1 lists frame frequency settings when f = 32,768 Hz as an example. CLK_LCD8A Seiko Epson Corporation 18-4 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
1, set the LCD8PWR.EXVCSEL bit to 1 and set both the LCD8PWR.VCEN and LCD- 8PWR.BSTEN bits to 0 to turn both the LCD voltage regulator and LCD voltage booster off. Figure 18.4.2.1 shows an external connection example for external voltage application mode 1. Seiko Epson Corporation 18-5 C17M30/M31/M32/M33/M34...
The LCD panel contrast can be adjusted within 16 levels using the LCD8PWR.LC[3:0] bits. This function is real- ized by controlling the voltage output from the LCD voltage regulator. Therefore, the LCD8PWR.LC[3:0] bits can- not be used for contrast adjustment in external voltage application modes 1 and 2. Seiko Epson Corporation 18-6 C17M30/M31/M32/M33/M34...
RAM is not altered. The common pins are set to dynamic drive for “All on” and to static drive for “All off.” This function can be used to make the display flash on and off without altering the display memory. Seiko Epson Corporation 18-7 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev.
In the display data RAM, two screen areas can be allocated and the LCD8DSP.DSPAR bit can be used to switch between the screens. Setting the LCD8DSP.DSPAR bit to 0 selects display area 0; setting to 1 selects display area 1. Seiko Epson Corporation 18-11 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev.
COM2 COM4 COM1 COM5 COM0 Unused area (general-purpose RAM) LCD8DSP.SEGREV · · · bit = 1 LCD8DSP.SEGREV · · · bit = 0 Figure 18.6.3.2 Display Data RAM Map (1/6 duty) Seiko Epson Corporation 18-12 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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· · · bit = 0 Figure 18.6.3.4 Display Data RAM Map (static drive) * The S1C17M30/M31/M32/M34 does not have the segment pins listed below, so the corresponding addresses are configured as an unused area (general-purpose RAM). When LCD8DSP.SEGREV bit = 1 1/8 to 1/2 duty, static drive S1C17M30: SEG4–12 (0x7004–0x700c, 0x7044–0x704c), SEG25–35 (0x7019–0x7023, 0x7059–0x7063),...
Note: If the LCD8CTL.MODEN bit is altered from 1 to 0 while the LCD panel is displaying, the LCD display is automatically turned off and the LCD8DSP.DSPC[1:0] bits are also set to 0x0. Also the LCD voltage regulator is automatically turned off and the LCD8PWR.VCEN bit is set to 0. Seiko Epson Corporation 18-15 C17M30/M31/M32/M33/M34...
Note: Do not alter the control bits in this register from the initial value when using a model that does not have an LCD power supply, except the LCD8PWR.EXVCSEL bit manipulation for V dis- charging. Seiko Epson Corporation 18-16 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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VCEN This bit turns the LCD voltage regulator on and off. 1 (R/W): LCD voltage regulator on 0 (R/W): LCD voltage regulator off For more information, refer to “LCD Power Supply.” Seiko Epson Corporation 18-17 C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• Provides an output and continuous oscillation function for monitoring the oscillation frequency. • Can generate reference oscillation completion, sensor (A and B) oscillation completion, measurement counter overflow error, and time base counter overflow error interrupts. Figure 19.1.1 shows the RFC configuration. Table 19.1.1 RFC Channel Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
(Clear interrupt flags) - Set the interrupt enable bits in the RFCnINTE register to 1. (Enable interrupts) 3. Assign the RFC input/output function to the ports. (Refer to the “I/O Ports” chapter.) Seiko Epson Corporation 19-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
To obtain the difference between the reference oscillation and sensor oscillation clock count values from the measurement counter simply, appropriate initial values must be set to the measurement counter before starting reference oscillation. Seiko Epson Corporation 19-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The measurement counter overflow sets the RFCnINTF.EREFIF bit to 1 indicating that the reference oscil- lation has been terminated normally. If the RFCnINTE.EREFIE bit = 1, a reference oscillation completion interrupt request occurs at this point. Seiko Epson Corporation 19-5 S1C17M30/M31/M32/M33/M34...
Performing reference oscillation and sensor oscillation with the same resistor and capacitor results n ≈ m. The difference between n and m is a conversion error. Table 19.4.4.1 lists the error factors. (n: measurement counter initial value, m: measurement counter value at the end of sensor oscillation) Seiko Epson Corporation 19-6 S1C17M30/M31/M32/M33/M34...
The RFC provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the in- terrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For more information on interrupt control, refer to the “Interrupt Controller” chapter. Seiko Epson Corporation 19-7 S1C17M30/M31/M32/M33/M34...
This bit sets the RFCLKOn pin to output the divided-by-two oscillation clock. 1 (R/W): Divided-by-two clock output 0 (R/W): Oscillation clock output For more information, refer to “CR Oscillation Frequency Monitoring Function.” Seiko Epson Corporation 19-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
This bit controls CR oscillation for sensor A. This bit also indicates the CR oscillation status. 1 (W): Start oscillation 0 (W): Stop oscillation 1 (R): Being oscillated 0 (R): Stopped Seiko Epson Corporation 19-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Note: The time base counter must be set from the low-order value (RFCnTCL.TC[15:0] bits) first when data is set using a 16-bit access instruction. The counter may not be set to the correct value if the high-order value (RFCnTCH.TC[23:16] bits) is written first. Seiko Epson Corporation 19-10 S1C17M30/M31/M32/M33/M34...
A/D conversion is actually started in sync with CLK_T16_k after a trigger is accepted. Writing 0 to the ADC12_nCTL.ADST bit stops A/D conversion after the one currently being executed has com- pleted. Seiko Epson Corporation 20-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
3. Read the A/D conversion result of the analog input m (ADC12_nADmD.ADmD[15:0] bits). 4. Repeat Steps 2 and 3 until terminating A/D conversion. 5. Write 0 to the ADC12_nCTL.ADST bit. The ADC12A stops operating after the A/D conversion currently being executed has completed. Seiko Epson Corporation 20-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
(ADC12_nTRG.CNVMD = 0). If A/D conversion is stopped after the maximum analog input pin number (different in each model) has been completed, these bits indicate ADINn0. Bit 11 Reserved Seiko Epson Corporation 20-6 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
ENDAIN[2:0] bits ≥ ADC12_nTRG.STAAIN[2:0] bits. Bits 10–8 STAAIN[2:0] These bits set the analog input pin to be A/D converted first. See Table 20.6.1 for the relationship between analog input pins and bit setting values. Seiko Epson Corporation 20-7 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Note: Make sure that the ADC12_nCTL.BSYSTAT bit is set to 0 before altering the ADC12_nCFG register. Bits 15–2 Reserved Bits 1–0 VRANGE[1:0] These bits set the A/D converter operating voltage range. Seiko Epson Corporation 20-8 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
The following shows the correspondence between the bit and interrupt: ADC12_nINTF.ADmOVIF bit: Analog input signal m A/D conversion result overwrite error interrupt ADC12_nINTF.ADmCIF bit: Analog input signal m A/D conversion completion interrupt Seiko Epson Corporation 20-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
ADC12A Ch.n Result Register m Register name Bit name Initial Reset Remarks ADC12_nADmD 15–0 ADmD[15:0] 0x0000 – Bits 15–0 ADmD[15:0] These bits are the A/D conversion results of the analog input signal m. Seiko Epson Corporation 20-10 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
A/D converter. • Can supply the reference voltage generated in this circuit to external devices if this IC has the VREFA exclusive pin. Figure 21.1.1 shows the TSRVR configuration. Table 21.1.1 TSRVR Configuration of S1C17M30/M31/M32/M33/M34 Item S1C17M30 S1C17M31...
ADD: A/D conversion result at temperature T or T (decimal) : A/D converter reference voltage [V] REFA For details of the internal A/D converter, refer to the “12-bit A/D Converter” chapter. Seiko Epson Corporation 21-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
TSRVRnVCTL.VREFAMD[1:0] VREFA bits are set to 0x2 or 0x3. • When the TSRVRnVCTL.VREFAMD[1:0] bits are not set to 0x0, do not apply an external volt- age to the VREFAm pin. Seiko Epson Corporation 21-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
%rs[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,%rs imm7[6:0] is written to the mode setting register. (%rd: not used) ld.cw %rd,imm7 Output mode setting value Operation mode setting value Figure 22.2.1 Mode Setting Register Seiko Epson Corporation 22-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
*5 R is not required when using the DSIO pin as a general-purpose I/O port. *6 The component values should be determined after evaluating operations using an actual mounting board. Seiko Epson Corporation 23-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
= 0 V, Ta = -40 to 85 °C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time – – µs Oscillation frequency 25 °C IOSC -40 to 85 °C Seiko Epson Corporation 23-4 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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Internal oscillator CLGOSC1.OSC1SELCR bit = 1 31.04 32.96 OSC1I oscillation frequency *1 CLGOSC1.CGI1[2:0] bits = 0x0, Crystal resonator = C-002RX (manufactured by Seiko Epson Corporation, R = 50 kW (Max.), C = 7 pF) Seiko Epson Corporation 23-5 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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CLK_SVD3 = 32 kHz, Ta = 25 °C *1 If CLK_SVD3 is configured in the neighborhood of 32 kHz, the SVDINTF.SVDDT bit is masked during the t period and it re- SVDEN tains the previous value. Seiko Epson Corporation 23-9 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
*1 Other LCD driver settings: LCD8PWR.LC[3:0] bits = 0xf, CLK_LCD8A = 32 kHz, LCD8TIM1.FRMCNT[4:0] bits = 0x03 (frame fre- quency = 64 Hz) *2 The value is added to the current consumption in HALT/RUN mode. Current consumption increases according to the display contents and panel load. Seiko Epson Corporation 23-12 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
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LCD circuit current-load characteristic Ta = 25 °C, Typ. value, LCD8PWR.LC[3:0] bits = 0xf, when a load is connected to the V pin only LCD8PWR.VCSEL bit = 0 LCD8PWR.VCSEL bit = 1 [µA] Seiko Epson Corporation 23-13 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
*1 The Max. value is the value when the A/D conversion clock frequency f = 2,000 kHz. CLK_ADC12A *2 Integral nonlinearity is measured at the end point line. *3 The error will be increased according to the potential difference between V and VREFAn. Seiko Epson Corporation 23-15 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
VREFA *1: For Flash programming *2: When the internal LCD power supply is used (S1C17M31/M33/M34) *3: When OSC1 crystal oscillator is selected (S1C17M30/M32/M33/M34) *4: When OSC3 crystal/ceramic oscillator is selected ( ): Do not mount components if unnecessary. Seiko Epson Corporation...
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Symbol Name Recommended components X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by Seiko Epson Corporation OSC1 gate capacitor Trimmer capacitor or ceramic capacitor OSC1 drain capacitor Ceramic capacitor X’tal3 Crystal resonator...
• Using a crystal resonator with lower C value decreases current consumption. However, these configurations may reduce the oscillation margin and increase the frequency error, therefore, be sure to perform matching evaluation using the actual printed circuit board. Seiko Epson Corporation AP-B-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
Note, however, that the load characteristic becomes worse. • Setting the LCD voltage regulator into heavy load protection mode (LCD8PWR.HVLD bit = 1) increases current consumption. Heavy load protection mode should be set only when the display becomes unstable. Seiko Epson Corporation AP-B-2 S1C17M30/M31/M32/M33/M34...
± 1 V. The C should be placed as close to the V pin as possible and use a sufficiently thick wiring pattern that allows current of several tens of mA to flow. Seiko Epson Corporation AP-C-1 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
(display off). The unused SEGx and COMx pins that are not required to connect with the LCD panel should be configured as a general-purpose/peripheral circuit I/O port even if the LCD driver is used. Seiko Epson Corporation AP-C-2 S1C17M30/M31/M32/M33/M34...
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(2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko Epson Corporation AP-C-3 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
• Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports” chapter. For the UART con- trol and details of receive errors, see the “UART” chapter. Seiko Epson Corporation AP-D-1 S1C17M30/M31/M32/M33/M34...
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The resistance value should be determined by evaluating it on the mounting board. When connecting a power supply directly to the VREFA pin, insert a 100 W resistor in series. This resistance does not affect the A/D converter characteristics. Seiko Epson Corporation AP-D-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
“intXX_handler” can be used for software interrupts. (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of Flash memory read cycles. (See the “Memory and Bus” chapter.) Seiko Epson Corporation AP-E-2 S1C17M30/M31/M32/M33/M34 TECHNICAL MANUAL (Rev. 1.3)
APPENDIX F EEPROM FUNCTION Appendix F EEPROM Function The S1C17M30/M31/M32/M33/M34 allows use of a part of the Flash area or a dedicated area as an EEPROM by implementing the “S1C17M30/M31/M32/M33/M34 EEPROM Emulation Library.” S1C17M30 S1C17M31 S1C17M32 S1C17M33 S1C17M34 EEPROM Fixed...
REVISION HISTORY Revision History Code No. Page Contents 413495600 New establishment 413495601 P1-1, Descriptions on the EEPROM emulation were added. PAP-F-1 P6-6 Reading input data from a GPIO port Deleted the note. Note: The PxDAT.PxINy bit retains the input port status at 1 clock before being read from the CPU. 413495602 1-2 to 3 1.1 Features...
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REVISION HISTORY Code No. Page Contents 413495602 24-1 24 Basic External Connection Diagram for Flash programming → 2.4 V to 5.5 V 25-1 to 3 25 Package A JEITA name was added to the package name. AP-A-23 Appendix A List of Peripheral Circuit Control Registers PDIOEN (Pd Port Enable Register) Modified the register table.
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