TYAN TIGERCUB ATX Manual page 55

Video RAM Cacheable
Selecting Enabled allows caching of the video memory, resulting in
better video performance.
8/16 Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles between PCI-
originated I/O cycles to the ISA bus. This delay takes place because
the PCI bus is so much faster than the ISA bus. These two fields let
you add recovery time (in bus clock cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for ISA adapter ROM.
When this area is reserved, it cannot be cached. The user information
of peripherals that need to use this area of system memory usually
discusses their memory requirements.
Passive Release
When Enabled, CPU to PCI bus accesses are allowed during passive
release. Otherwise, the arbiter only accepts another PCI master access
to local DRAM.
Delayed Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with
PCI specification version 2.1.
AGP Aperture Size (MB)
Select the size of the Accelerated Graphics Port (AGP) aperture. The
aperture is a portion of the PCI memory address range dedicated for
graphics memory address space. Host cycles that hit the aperture
range are forwarded to the AGP without any translation. See
www.agpforum.org for APG information.
SDRAM RAS to CAS Delay
This field lets you insert a timing delay between the CAS and RAS
strobe signals, used when DRAM is written to, read from, or refreshed.
Fast gives faster performance; and Slow gives more stable perfor-
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