TYAN TIGERCUB ATX Manual page 54

Chapter 4
BIOS Configuration
DRAM ECC/Parity Select
Select Parity, ECC (error-correcting code), or Disabled, depending on
the type of DRAM installed in your system.
CPU-To-PCI IDE Posting
Select Enabled to post write cycles from the CPU to the PCI IDE
interface. IDE accesses are posted in the CPU to PCI buffers, for
cycle optimization.
DRAM Read-Around-Write
DRAM optimization feature: If a memory read is addressed to a
location whose latest write is being held in a buffer before being written
to memory, the read is satisfied through the buffer contents, and the
read is not sent to the DRAM.
Burst Write Combining
When this option is Enabled, the chipset assembles long PCI bursts
from the data held in these buffers.
PCI-To-DRAM Pipeline
DRAM optimization feature: If Enabled, full PCI-to-DRAM write
pipelining is enabled. Buffers in the chipset store data written from the
PCI bus to memory. When Disabled, PCI writes to DRAM are limited
to a single transfer per write cycle.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However, if
any program writes to this memory area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS ROM at C0000h
to C7FFFh, resulting in better video performance. However, if any
program writes to this memory area, a memory access error may
result.
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