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32
Rev.2.00
2003.9.19
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
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be checked by referring to the relevant text.
Renesas 32-Bit RISC Microcomputer
SuperH
™
SH7705
RISC engine Family/SH7700 Series
Group
Hardware Manual
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Chapters
Table of Contents
Related Manuals for Renesas SuperH RISC engine Series
Summarization of Contents
Cautions
Notes regarding these materials
Information regarding the materials provided for customer assistance in product selection and application.
General Precautions on Handling of Product
Handling of Pins and Addresses
Guidance on NC pins, unused input pins, pre-initialization processing, and reserved addresses.
Section 2 CPU
Processing States and Processing Modes
Details the four CPU processing states and two processing modes (user/privileged).
Memory Map
Describes the 4-Gbyte logical address space and its division into areas P0-P4.
Register Descriptions
Lists and describes the general, system, program counter, and control registers.
Data Formats
Explains register and memory data formats, including endianness.
Features of CPU Core Instructions
Covers instruction length, load/store architecture, delayed branching, and T bit usage.
Instruction Set
Details the 68 basic instruction types categorized into six functional groups.
Section 3 Memory Management Unit (MMU)
Role of MMU
Explains the MMU's function in efficient physical memory usage and virtual memory systems.
Register Descriptions
Details the PTEH, PTEL, TTB, and MMUCR registers for MMU processing.
TLB Functions
Covers TLB caching, indexing, address comparison, and page management information.
MMU Functions
Explains hardware and software management aspects of the MMU.
MMU Exceptions
Details TLB miss, protection violation, TLB invalid, and initial page write exceptions.
Section 4 Cache
Features
Describes cache capacity, structure, locking, line size, and write system.
Register Descriptions
Lists cache control registers (CCR1, CCR2, CCR3) for managing cache operations.
Operation
Explains cache search, read, prefetch, write access, and buffer operations.
Memory-Mapped Cache
Details address array and data array access for software cache management.
Usage Note
Provides guidance on using the cache, including avoiding synonym problems and specific operations.
Section 5 Exception Handling
Register Descriptions
Lists registers for exception handling: TRA, EXPEVT, INTEVT, INTEVT2, TEA.
Exception Handling Function
Explains the exception handling flow, vector addresses, codes, and request/BL bit settings.
Individual Exception Operations
Details conditions and operations for resets and general exceptions like CPU address errors.
Usage Notes
Provides notes on RTE instruction, MMU register modification, and CPU processing modes.
Section 6 Interrupt Controller (INTC)
Features
Highlights interrupt priority levels, NMI noise canceller, and IRQ interrupt settings.
Input/Output Pins
Lists INTC pin configuration for NMI, IRQ, and PINT interrupts.
Register Descriptions
Details registers for interrupt control, priority levels, and request status.
Interrupt Sources
Categorizes interrupt sources into NMI, IRQ, IRL, PINT, and on-chip peripheral modules.
Interrupt Exception Handling and Priority
Explains priority determination for resets, general exceptions, and interrupts.
Usage Note
Provides notes on interrupt accept timing and clearing interrupt flags.
Section 7 Bus State Controller (BSC)
Overview
Describes BSC's role in outputting control signals for memory and external devices.
Pin Configuration
Lists BSC pins and their functions for address, data, and control signals.
Area Overview
Explains the logical and physical address spaces divided into eight areas managed by BSC.
Register Descriptions
Lists common control, bus control, and wait control registers for BSC.
Endian/Access Size and Data Alignment
Details support for big endian, little endian, and data alignment for various bus widths.
Normal Space Interface
Covers basic timings for accessing normal space, including read/write cycles.
Address/Data Multiplex I/O Interface
Explains the interface for peripheral LSIs requiring address/data multiplexing.
SDRAM Interface
Covers SDRAM direct connection, address multiplexing, burst read/write, and refresh.
Burst ROM Interface
Describes high-speed access to ROMs with page mode function.
Section 8 Direct Memory Access Controller (DMAC)
Features
Outlines DMAC capabilities: channels, address space, transfer unit, count, address mode, requests, bus modes, and priority.
Input/Output Pins
Describes the external pins for the DMAC, including DREQ, DACK, and TEND signals.
Register Descriptions
Lists SAR, DAR, DMATCR, CHCR, DMAOR, and DMARS registers for DMAC configuration.
Operation
Explains the DMA transfer flow, including request handling and completion.
Precautions
Provides precautions for mixing cycle-steal and burst mode channels.
Section 9 Clock Pulse Generator (CPG)
Features
Details clock modes, generated clocks, frequency change function, and power-down control.
Input/Output Pins
Lists CPG pins and their functions: mode control, crystal oscillator, clock I/O, and USB clock.
Clock Operating Modes
Shows the relationship between mode control pins and clock operating modes.
Register Descriptions
Describes frequency control (FRQCR) and USB clock control (UCLKCR) registers.
Changing Frequency
Explains how to change internal and peripheral clock frequencies via software.
Usage Notes
Provides notes on using the USB module and clock settings.
Section 10 Watchdog Timer (WDT)
Features
Highlights WDT usage for clock settling, standby modes, resets, interrupts, and clock selection.
Register Descriptions
Details the watchdog timer counter (WTCNT) and control/status register (WTCSR).
Operation
Explains how to cancel software standbys, change frequency, and use watchdog/interval timer modes.
Section 11 Power-Down Modes
Features
Lists power-down modes: Sleep, Software Standby, Module Standby, and Hardware Standby.
Input/Output Pins
Lists pins used for power-down modes: STATUS, RESET, and CA.
Register Descriptions
Details standby control registers (STBCR, STBCR2, STBCR3) for module power control.
Sleep Mode
Explains transition to and cancellation of sleep mode.
Software Standby Mode
Details transition to and cancellation of software standby mode.
Module Standby Function
Describes how to transition to and cancel module standby mode.
Hardware Standby Mode
Explains transition to and canceling hardware standby mode via CA pin.
Timing of STATUS Pin Changes
Shows timing diagrams for STATUS pin changes during resets and mode transitions.
Section 12 Timer Unit (TMU)
Features
Describes TMU features: auto-reload counter, registers, interrupts, and input capture.
Input/Output Pin
Lists TMU pin configuration for clock input and input capture.
Register Descriptions
Details registers for TMU channels: TSTR, TCOR, TCNT, TCR, TIOR, TIER, TSR.
Operation
Explains TMU operation: counter, input capture, and interrupts.
Interrupts
Describes TMU interrupt sources: underflow (TUNI) and input capture (TICPI2).
Usage Notes
Provides notes on writing to and reading TMU registers.
Section 13 Compare Match Timer (CMT)
Features
Highlights CMT features: selectable input clocks, DMA transfer request, and power consumption reduction.
Register Descriptions
Details CMT registers: CMSTR, CMCSR, CMCNT, and CMCOR.
Operation
Explains CMT operation: period count, count timing, and compare match flag set.
Section 14 16-Bit Timer Pulse Unit (TPU)
Features
Describes TPU features: 4-pulse output, clock selection, waveform output, counter clear, PWM modes, and buffer operation.
Input/Output Pins
Lists TPU pin configuration for output compare/PWM pins (TO0-TO3).
Register Descriptions
Details TPU registers for channels 0-3: TCR, TMDR, TIOR, TIER, TSR, TCNT, TGRA-TGRD.
Operation
Explains TPU operation: counter, buffer, and PWM modes.
Section 15 Realtime Clock (RTC)
Features
Lists RTC features: clock/calendar functions, 1-Hz timer, start/stop, alarm, periodic/carry interrupts, and leap year adjustment.
Input/Output Pins
Lists RTC pin configuration for crystal oscillator and power supply.
Register Descriptions
Details RTC registers: counters R64CNT to RYRCNT, alarm registers RSECAR to RYRAR, and control registers RCR1-RCR3.
Operation
Explains RTC operation: initial settings, setting time, reading time, and alarm function.
Notes for Usage
Provides notes on register writing during RTC count, periodic interrupts, and standby mode.
Section 16 Serial Communication Interface with FIFO (SCIF)
Features
Details SCIF features: asynchronous and clock synchronous modes, FIFO buffers, baud rate generator, clock source, and interrupts.
Input/Output Pins
Lists SCIF pin configuration for serial clock, data, and modem control.
Register Descriptions
Details SCIF registers for channel 0 and 2: SCSMR, SCBRR, SCSCR, SCTDSR, SCFER, SCSSR, SCFCR, SCFDR, SCFTDR, SCFRDR.
Operation
Explains SCIF operation: overview, asynchronous mode, and clock synchronous mode.
SCIF Interrupt Sources and DMAC
Lists SCIF interrupt sources and DMAC activation for transmit/receive operations.
Notes on Usage
Provides notes on SCIF usage: SCFTDR writing, TDFE/RDF flag handling, break detection.
Section 17 Infrared Data Association Module (IrDA)
Features
Details IrDA features: IrDA 1.0 compliance, asynchronous communication, FIFO buffers, baud rate generator, guard functions, clock halt.
Input/Output Pins
Lists IrDA pin configuration for receive and transmit data pins.
Register Description
Describes the IrDA mode register (SCSMR_Ir).
Operation
Explains IrDA operation: overview, transmitting, receiving, and data format specification.
Section 18 USB Function Module
Features
Covers UDC features: USB 2.0 compliance, automatic processing, transfer speed, endpoint configuration, interrupts, clock, and power-down mode.
Input/Output Pins
Lists USB pin configuration for data, control, power supply, and clock signals.
Register Descriptions
Lists USB registers: IFR0, IFR1, ISR0, ISR1, IER0, IER1, EPDR0i-EPDR3, EPSZ0o, EPSZ1, TRG, DASTS, FCLR, EPSTL, XVERCR.
Operation
Explains USB operation: cable connection, disconnection, control transfer, bulk transfers, and interrupt transfers.
Processing of USB Standard Commands and Class/Vendor Commands
Details processing of commands transmitted by control transfer, indicating required decoding.
Stall Operations
Describes stall operations: overview and forcible stall by application.
DMA Transfer
Explains DMA transfer for endpoints 1 and 2, including overview and transfer details.
Example of USB External Circuitry
Shows examples of USB external circuitry for transceiver, D+ pull-up, and cable detection.
Usage Notes
Provides notes on USB usage: receiving setup data, clearing FIFO, and overreading/overwriting registers.
Section 19 Pin Function Controller
Overview
Explains the PFC's role in selecting pin functions and I/O directions of multiplex pins.
Register Descriptions
Lists port control registers (PACR, PBCR, PCCR, PDCR, PECR, PECR2, PFCR, PFCR2, PGCR, PHCR, PJCR, PKCR, PLCR, PMCR, PNCR, PNCR2).
Section 20 I/O Ports
Port A
Describes Port A as an 8-bit input/output port and its data register (PADR).
Port B
Describes Port B as an 8-bit input/output port and its data register (PBDR).
Port C
Describes Port C as an 8-bit input/output port and its data register (PCDR).
Port D
Describes Port D as an 8-bit input/output port and its data register (PDDR).
Port E
Describes Port E as an 8-bit input/output port and its data register (PEDR).
Port F
Describes Port F as an 8-bit input port and its data register (PFDR).
Port G
Describes Port G as an 8-bit input port and its data register (PGDR).
Port H
Describes Port H as a 7-bit input/output port and its data register (PHDR).
Port J
Describes Port J as an 8-bit output port and its data register (PJDR).
Port K
Describes Port K as an 8-bit input/output port and its data register (PKDR).
Port L
Describes Port L as a 4-bit input port and its data register (PLDR).
Port M
Describes Port M as a 6-bit input/output port and its data register (PMDR).
Port N
Describes Port N as an 8-bit input/output port and its data register (PNDR).
SC Port
Describes the SC port as an 8-bit input/output port and its data register (SCPDR).
Section 21 A/D Converter
Features
Details A/D converter features: resolution, channels, conversion time, modes, data registers, sample-hold, interrupts, and module standby.
Input/Output Pins
Summarizes A/D converter pins: power supply, ground, and analog inputs.
Register Descriptions
Lists A/D converter registers: data registers ADDRA-ADDRD and control/status register ADCSR.
Operation
Explains A/D converter operation: single, multi, and scan modes, and input sampling time.
Interrupts and DMAC Transfer Request
Describes ADI interrupt and DMAC activation via ADIE and DMASL bits.
Definitions of A/D Conversion Accuracy
Defines resolution, quantization error, offset error, full-scale error, nonlinearity error, and absolute accuracy.
Section 22 User Break Controller
Features
Lists UBC features: break channels, comparison conditions (address, data, bus cycle, operand size), user break generation, pre/post instruction break, repeat times, and branch buffers.
Register Descriptions
Lists UBC registers: BARA, BAMRA, BBRA, BARB, BAMRB, BBRB, BDRB, BDMRB, BRCR, BETR, BRSR, BRDR, BASRA, BASRB.
Operation
Explains the flow of user break operation, including break conditions and CPU actions.
Section 23 User Debugging Interface (UDI)
Features
Describes UDI features: serial I/O interface, JTAG support, boundary scan mode, emulator connection.
Input/Output Pins
Lists UDI pin configuration for TCK, TMS, TRST, TDI, TDO, ASEMD0.
Register Descriptions
Lists UDI registers: SDBPR, SDIR, SDBSR, SDID.
Operation
Explains UDI operation: TAP controller, reset configuration, TDO timing, UDI reset, and UDI interrupt.
Boundary Scan
Details boundary scan mode and supported JTAG instructions: BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE, CLAMP, HIGHZ.
Usage Notes
Provides notes on UDI usage: command setting, standby mode, and emulator connection.
Section 25 Electrical Characteristics
Absolute Maximum Ratings
Lists absolute maximum ratings for power supply, input, and output voltages, temperature.
DC Characteristics (Common Items)
Provides DC characteristics for common items like power supply, current consumption, and input leak.
DC Characteristics (USB-Related Pins*)
Lists DC characteristics for USB-related pins, including power supply and input/output voltages.
Permitted Output Current Values
Specifies permitted output current values for various pins under different conditions.
Maximum Operating Frequencies
Lists maximum operating frequencies for CPU, cache, external bus, and peripheral modules.
Clock Timing
Provides detailed timing specifications for clock signals like EXTAL, CKIO, and RESET.
Control Signal Timing
Details timing for control signals like RESET, NMI, IRQ, and CKE.
Bus Timing (1)
Shows basic bus timings for read/write, address, and data signals.
AC Characteristics Measurement Conditions
Specifies measurement conditions for AC characteristics like I/O signal reference and input pulse levels.
A/D Converter Characteristics
Lists A/D converter characteristics including resolution, conversion time, and accuracy.
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