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EVM User's Guide: LMX1860SEPEVM
LMX1860-SEP Evaluation Module
Description
The LMX1860-SEP evaluation module (EVM) is
designed to evaluate the performance of the
LMX1860-SEP, which is a four-output, ultra-low
additive jitter radio-frequency (RF) buffer, divider and
multiplier. The device can buffer RF frequencies up to
18GHz, multiply RF outputs up to 6.4GHz, and divide
outputs by up to 6.4GHz. This board consists of an
LMX1860-SEP device and an integrated USB2ANY
programmer.
Features
300MHz to 18GHz output frequency
4 high-frequency clocks with corresponding
SYSREF outputs
– Shared divide by 2, 3, 4, 5, 6, 7 and 8
– Shared programmable multiplier ×2, ×3, and ×4
SNAU293 – MAY 2024
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3.3V supply voltage (with onboard 2.5V LDOs) or
2.5V supply voltage (with LDOs bypassed)
–55ºC to +125ºC operating temperature (with
onboard MCU bypassed)
Optional pin mode control without register
programming
Applications
General purpose:
– Data converter clocking
– Clock distribution/multiplication/division
Aerospace and defense:
– Phased array antenna/beam forming
Copyright © 2024 Texas Instruments Incorporated
Radar
Electronic warfare
Seeker front end
LMX1860-SEP Evaluation Module
Description
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Summary of Contents for Texas Instruments LMX1860SEPEVM

  • Page 1 – Phased array antenna/beam forming – Shared divide by 2, 3, 4, 5, 6, 7 and 8 – Shared programmable multiplier ×2, ×3, and ×4 SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 2: Kit Contents

    SYSREF signals required. With low jitter and noise floor, this device combined with an ultra-low noise reference clock source is an exemplary design for clocking data converters, especially when sampling above 3GHz. LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 3: Connection Diagram

    2-CH Arbitrary Function Generator Balun 1.3V ± 0.2V High-Quality Signal Generator PC with TICSPro & Signal Analyzer device profile installed Figure 2-1. EVM Connection Diagram SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 4 LOGICH) J37-J38 (Pulled LOW) When LOGICEN is set to low, all FPGA/LOGIC circuits and the SYSREF sub-system are deactivated and SPI cannot re-enable. LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 5 Make sure the input voltage to U7 is larger than 0.7 * VCCIN and that output voltage of U7 is greater than 2.31V. SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 6 2. Only divider values of 2/3/4 are available in pin mode. Divider values of 5 , 6 , 7 & 8 are valid divider values only when in SPI mode. LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 7: Output Connections

    IO expander. LOGICLK is also enabled in this mode with a fixed divider value of 128. SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 8 1. Set CLK_MUX (R25[2:0] = Divider (0x2). 2. Set CLK_DIV (R25[5:3]) to appropriate divider value for respective CLKIN frequency. Figure 2-4. Divider Mode Configuration LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 9 LOW or HIGH directly without the need of a physical short. • Output Enable and Device mode options. Figure 2-6. Pin Mode Options • RF output power settings for all CLKOUTx. SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 10 Hardware www.ti.com Figure 2-7. pinPWRSEL • Chooses the corresponding divider value when in divider mode or multiplier value in multiplier mode. Figure 2-8. pinDIVSEL LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 11: Software Description

    3.1 Software Installation Download and install TICS Pro software from www.ti.com/tool/ticspro-sw. 3.2 Software Description Texas Instruments Clocks and Synthesizers (TICS) Pro software is used to program this evaluation module (EVM) through the on-board USB2ANY interface. 3.3 USB2ANY Interface The on-board USB2ANY interface provides a bridge between TICS Pro software and the LMX1860-SEP device.
  • Page 12 9. Click the Identify button, the LED in the USB2ANY interface flashes. Figure 3-6. Identify USB2ANY Controller 10. Now, the USB2ANY is ready to use. Click the Close button to close the window. LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 13 In all of the following plots, the blue trace is the 3.2GHz reference clock from SMA100B and the black trace is the output clock from the device. Figure 4-2. Buffer Mode Signal Analyzer Plot SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 14 CLK_DIV and CLK_MULT fields to specify the frequency scaling factor. Figure 4-3. Divide-by-2 Mode Signal Analyzer Plot Figure 4-4. Multiplier x4 Mode Signal Analyzer Plot LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 15 LOW→HIGH transition must be seen on SYSREFREQ pins to trigger the pulser. For repeater mode, the output follows the input state. Figure 4-5. Buffer Mode With 10MHz SYSREF SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 16 GUI calculates the correct step values to achieve the requested delay as closely as possible. Alternately, the register-based delay fields can be stepped through or programmed to achieve the same result. Figure 4-6. SYSREF Delay in 5-Code Steps LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 17 Hardware Design Files 5 Hardware Design Files 5.1 Schematic Figure 5-1. Power Supply SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 18 Hardware Design Files www.ti.com Figure 5-2. Power Supply LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 19 Hardware Design Files Figure 5-3. LMX1860-SEP SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 20 Hardware Design Files www.ti.com Figure 5-4. Clock Input, Clock Output Interface LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 21 Hardware Design Files Figure 5-5. IO Interface SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 22 Hardware Design Files www.ti.com Figure 5-6. USB2ANY Interface LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 23: Pcb Layout

    Hardware Design Files 5.2 PCB Layout Figure 5-7. Top Layer Figure 5-8. Layer 2 (RF GND) SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 24 Hardware Design Files www.ti.com Figure 5-9. Layer 3 (Power) Figure 5-10. Layer 4 (Power) LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 25 Hardware Design Files Figure 5-11. Layer 5 (GND) Figure 5-12. Bottom Layer SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 26: Pcb Layer Stack-Up

    FR4 (Er = 4.27) Signal GND layer 2 FR4 (Er = 3.88) GND layer FR4 (Er = 4.21) o m layer ¡ Figure 5-13. PCB Layer Stack-Up LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 27 J14, J28, J29, J40 Header, 100mil, 3x1, Gold, TSW-103-07-G-S Samtec J15, J17, J19, J21, J23, CONN SMA JACK STR CON-SMA-EDGE-S EDGE MNT RF Solutions Ltd. J25, J30 SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 28 SH-J1, SH-J2, SH-J3, SH- Shunt, 2.54mm, Gold, Black 60900213421 2.54mm Wurth Elektronik TP1, TP4, TP5, TP6, TP9, Test Point, Miniature, White 5002 Keystone TP10, TP11 LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 29 Texas Instruments Single Schmitt-Trigger Buffer SN74LVC1G17DBVR DBV0005A Texas Instruments Low-Power I/O Expander TCA9535RTWR RTW0024B Texas Instruments Crystal, 24.000MHz, 20pF ECS-240-20-5PX-TR 11.4×4.3×3.8 mm ECS Inc. SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 30 Try toggling the RESET bit on the User Controls page before loading all registers again (Ctrl+L). • Refer to the data sheet to make sure a valid multiplier value is being used for the corresponding input frequency. LMX1860-SEP Evaluation Module SNAU293 – MAY 2024 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 31 100Ω impedance. An arbitrary function generator is recommended if possible. 6.2 Trademarks All trademarks are the property of their respective owners. SNAU293 – MAY 2024 LMX1860-SEP Evaluation Module Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated...
  • Page 32 STANDARD TERMS FOR EVALUATION MODULES Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein.
  • Page 33 www.ti.com Regulatory Notices: 3.1 United States 3.1.1 Notice applicable to EVMs not FCC-Approved: FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product.
  • Page 34 www.ti.com Concernant les EVMs avec antennes détachables Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à...
  • Page 35 www.ti.com EVM Use Restrictions and Warnings: 4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS. 4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices.
  • Page 36 Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2023, Texas Instruments Incorporated...
  • Page 37 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2024, Texas Instruments Incorporated...

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