Renesas R5F21321ADSP Manuals

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Renesas R5F21321ADSP Hardware Manual

Renesas R5F21321ADSP Hardware Manual (603 pages)

M16C FAMILY / R8C/Tiny SERIES MCU

Brand: Renesas | Category: Microcontrollers | Size: 6 MB

Table of Contents

General Precautions in the Handling of MPU/MCU Products
3
How to Use this Manual
4
Purpose and Target Readers
4
Notation of Numbers and Symbols
5
List of Abbreviations and Acronyms
7
Table of Contents
8
Overview
29
Features
29
Applications
29
Specifications
30
Product List
32
Block Diagram
33
Pin Assignment
34
Pin Assignment (Top View)
34
Pin Functions
36
Central Processing Unit (CPU)
38
Data Registers (R0, R1, R2, and R3)
39
Address Registers (A0 and A1)
39
Frame Base Register (FB)
39
Interrupt Table Register (INTB)
39
Program Counter (PC)
39
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
39
Static Base Register (SB)
39
Flag Register (FLG)
39
Carry Flag (C)
39
Debug Flag (D)
39
Interrupt Enable Flag (I)
40
Stack Pointer Select Flag (U)
40
Processor Interrupt Priority Level (IPL)
40
Reserved Bit
40
Memory
41
R8C/32A Group
41
Special Function Registers (Sfrs)
42
Resets
54
Pin Function
55
Reset Sequence
55
Registers
56
Processor Mode Register 0 (PM0)
56
Reset Source Determination Register (RSTFR)
56
Option Function Select Register (OFS)
57
Option Function Select Register 2 (OFS2)
58
Hardware Reset
59
When Power Supply Is Stable
59
Power on
59
Power-On Reset Function
61
Voltage Monitor 0 Reset
62
Watchdog Timer Reset
63
Software Reset
63
Cold Start-Up/Warm Start-Up Determination Function
64
Reset Source Determination Function
64
Voltage Detection Circuit
65
Overview
65
Registers
69
Voltage Monitor Circuit/Comparator a Control Register (CMPA)
69
Voltage Monitor Circuit Edge Select Register (VCAC)
70
Voltage Detect Register (VCA1)
70
Voltage Detect Register 2 (VCA2)
71
Voltage Detection 1 Level Select Register (VD1LS)
72
Voltage Monitor 0 Circuit Control Register (VW0C)
73
Voltage Monitor 1 Circuit Control Register (VW1C)
74
Voltage Monitor 2 Circuit Control Register (VW2C)
75
Option Function Select Register (OFS)
76
VCC Input Voltage
77
Monitoring Vdet0
77
Monitoring Vdet1
77
Monitoring Vdet2
77
Voltage Monitor 0 Reset
78
Voltage Monitor 1 Interrupt
79
Voltage Monitor 2 Interrupt
81
I/O Ports
83
Functions of I/O Ports
83
Effect on Peripheral Functions
84
Pins Other than I/O Ports
84
Configuration of I/O Ports
85
Registers
93
Port Pi Direction Register (Pdi) (I = 1, 3, 4)
93
Port Pi Register (Pi) (I = 1, 3, 4)
94
Timer RA Pin Select Register (TRASR)
95
Timer RC Pin Select Register (TRBRCSR)
95
Timer RC Pin Select Register 0 (TRCPSR0)
96
Timer RC Pin Select Register 1 (TRCPSR1)
96
UART0 Pin Select Register (U0SR)
97
UART2 Pin Select Register 0 (U2SR0)
98
UART2 Pin Select Register 1 (U2SR1)
98
SSU/IIC Pin Select Register (SSUIICSR)
99
INT Interrupt Input Pin Select Register (INTSR)
99
Pull-Up Control Register 0 (PUR0)
100
Pull-Up Control Register 1 (PUR1)
100
Port P1 Drive Capacity Control Register (P1DRR)
101
Drive Capacity Control Register 0 (DRR0)
102
Drive Capacity Control Register 1 (DRR1)
103
Input Threshold Control Register 0 (VLT0)
104
Input Threshold Control Register 1 (VLT1)
104
Port Settings
105
Unassigned Pin Handling
114
Bus
115
Clock Generation Circuit
117
Overview
117
Registers
120
System Clock Control Register 0 (CM0)
120
System Clock Control Register 1 (CM1)
121
System Clock Control Register 3 (CM3)
122
Oscillation Stop Detection Register (OCD)
123
High-Speed On-Chip Oscillator Control Register 7 (FRA7)
123
High-Speed On-Chip Oscillator Control Register 0 (FRA0)
124
High-Speed On-Chip Oscillator Control Register 1 (FRA1)
124
High-Speed On-Chip Oscillator Control Register 2 (FRA2)
125
Clock Prescaler Reset Flag (CPSRF)
125
High-Speed On-Chip Oscillator Control Register 4 (FRA4)
126
High-Speed On-Chip Oscillator Control Register 5 (FRA5)
126
High-Speed On-Chip Oscillator Control Register 6 (FRA6)
126
High-Speed On-Chip Oscillator Control Register 3 (FRA3)
126
Voltage Detect Register 2 (VCA2)
127
XIN Clock
129
External Clock Input Circuit
129
On-Chip Oscillator Clock
130
Low-Speed On-Chip Oscillator Clock
130
High-Speed On-Chip Oscillator Clock
130
XCIN Clock
131
CPU Clock and Peripheral Function Clock
132
System Clock
132
CPU Clock
132
Peripheral Function Clock (F1, F2, F4, F8, and F32)
132
Foco
132
Foco40M
132
Foco-F
132
Foco-S
133
Foco128
133
Fc, Fc2, Fc4, and Fc32
133
Foco-WDT
133
Power Control
134
Standard Operating Mode
134
Wait Mode
136
Stop Mode
140
Entering Stop Mode
140
Exiting Stop Mode
141
Oscillation Stop Detection Function
143
How to Use Oscillation Stop Detection Function
144
Notes on Clock Generation Circuit
147
Stop Mode
147
Wait Mode
147
Oscillation Stop Detection Function
147
Oscillation Circuit Constants
147
10. Protection
148
Register
148
Protect Register (PRCR)
148
11. Interrupts
149
Overview
149
Types of Interrupts
149
Software Interrupts
150
Special Interrupts
151
Peripheral Function Interrupts
151
Interrupts and Interrupt Vectors
152
Registers
154
Interrupt Control Register
154
(Treic, S2Tic, S2Ric, Kupic, Adic, S0Tic, S0Ric, Traic, Trbic, U2Bcnic, Vcmp1Ic, Vcmp2Ic)
154
Interrupt Control Register (FMRDYIC TRCIC, SSUIC/IICIC)
155
Inti Interrupt Control Register (Intiic) (I = 0, 1, 3)
156
Interrupt Control
157
I Flag
157
IR Bit
157
Bits ILVL2 to ILVL0, IPL
157
Interrupt Sequence
158
Interrupt Response Time
159
IPL Change When Interrupt Request Is Acknowledged
159
Saving Registers
160
Returning from Interrupt Routine
162
Interrupt Priority
162
11.3.10 Interrupt Priority Level Selection Circuit
163
INT Interrupt
164
Inti Interrupt (I = 0, 1, 3)
164
INT Interrupt Input Pin Select Register (INTSR)
164
External Input Enable Register 0 (INTEN)
165
INT Input Filter Select Register 0 (INTF)
165
Inti Input Filter (I = 0, 1, 3)
166
Key Input Interrupt
167
Key Input Enable Register 0 (KIEN)
168
Address Match Interrupt
169
Address Match Interrupt Enable Register I (Aieri) (I = 0 or 1)
170
Address Match Interrupt Register I (Rmadi) (I = 0 or 1)
170
Timer RC Interrupt, Synchronous Serial Communication Unit Interrupt, I 2 C Bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple Interrupt Request Sources)
171
Notes on Interrupts
173
Reading Address 00000H
173
SP Setting
173
External Interrupt and Key Input Interrupt
173
Changing Interrupt Sources
174
Rewriting Interrupt Control Register
175
12. ID Code Areas
176
Overview
176
Functions
177
Forced Erase Function
178
Standard Serial II/O Mode Disabled Function
178
Notes on ID Code Areas
179
Setting Example of ID Code Areas
179
13. Option Function Select Area
180
Overview
180
Registers
181
Option Function Select Register (OFS)
181
Option Function Select Register 2 (OFS2)
182
Notes on Option Function Select Area
183
Setting Example of Option Function Select Area
183
14. Watchdog Timer
184
Overview
184
Watchdog Timer Block Diagram
185
Registers
186
Processor Mode Register 1 (PM1)
186
Watchdog Timer Reset Register (WDTR)
186
Watchdog Timer Start Register (WDTS)
186
Watchdog Timer Control Register (WDTC)
187
Count Source Protection Mode Register (CSPR)
187
Option Function Select Register (OFS)
188
Option Function Select Register 2 (OFS2)
189
Functional Description
190
Common Items for Multiple Modes
190
Count Source Protection Mode Disabled
191
Count Source Protection Mode Enabled
192
15. Dtc
193
Overview
193
Registers
194
DTC Control Register (DTCCR)
195
DTC Block Size Register (DTBLS)
195
DTC Transfer Count Register (DTCCT)
196
DTC Transfer Count Reload Register (DTRLD)
196
DTC Source Address Register (DTSAR)
196
DTC Destination Register (DTDAR)
196
DTC Activation Enable Registers (Dtceni) (I = 0 to 3, 5, 6)
197
DTC Activation Control Register (DTCTL)
198
Function Description
199
Overview
199
Activation Sources
199
Control Data Allocation and DTC Vector Table
201
Normal Mode
204
Repeat Mode
205
Chain Transfers
206
Interrupt Sources
206
Operation Timings
207
Number of DTC Execution Cycles
208
Notes on DTC
209
DTC Activation Source
209
Dtceni Registers (I = 0 to 3, 5, 6)
209
Peripheral Modules
209
16. General Overview of Timers
210
17. Timer RA
212
Overview
212
Registers
213
Timer RA Control Register (TRACR)
213
Timer RA I/O Control Register (TRAIOC)
213
Timer RA Mode Register (TRAMR)
214
Timer RA Prescaler Register (TRAPRE)
214
Timer RA Register (TRA)
215
Timer RA Pin Select Register (TRASR)
215
Timer Mode
216
Timer RA I/O Control Register (TRAIOC) in Timer Mode
216
Timer Write Control During Count Operation
217
Pulse Output Mode
218
Timer RA I/O Control Register (TRAIOC) in Pulse Output Mode
219
Event Counter Mode
220
Timer RA I/O Control Register (TRAIOC) in Event Counter Mode
221
Pulse Width Measurement Mode
222
Timer RA I/O Control Register (TRAIOC) in Pulse Width Measurement Mode
223
Operating Example
224
Pulse Period Measurement Mode
225
Timer RA I/O Control Register (TRAIOC) in Pulse Period Measurement Mode
226
Operating Example
227
Notes on Timer RA
228
18. Timer RB
229
Overview
229
Registers
230
Timer RB Control Register (TRBCR)
230
Timer RB One-Shot Control Register (TRBOCR)
230
Timer RB I/O Control Register (TRBIOC)
231
Timer RB Mode Register (TRBMR)
231
Timer RB Prescaler Register (TRBPRE)
232
Timer RB Secondary Register (TRBSC)
232
Timer RB Primary Register (TRBPR)
233
Timer Mode
234
Timer RB I/O Control Register (TRBIOC) in Timer Mode
234
Timer Write Control During Count Operation
235
Programmable Waveform Generation Mode
237
Timer RB I/O Control Register (TRBIOC) in Programmable Waveform Generation Mode
238
Operating Example
239
Programmable One-Shot Generation Mode
240
Timer RB I/O Control Register (TRBIOC) in Programmable One-Shot Generation Mode
241
Operating Example
242
One-Shot Trigger Selection
243
Programmable Wait One-Shot Generation Mode
244
Timer RB I/O Control Register (TRBIOC) in Programmable Wait One-Shot Generation Mode
245
Operating Example
246
Notes on Timer RB
247
Timer Mode
247
Programmable Waveform Generation Mode
247
Programmable One-Shot Generation Mode
248
Programmable Wait One-Shot Generation Mode
248
19. Timer RC
249
Overview
249
Registers
251
Module Standby Control Register (MSTCR)
252
Timer RC Mode Register (TRCMR)
252
Timer RC Control Register 1 (TRCCR1)
253
Timer RC Interrupt Enable Register (TRCIER)
253
Timer RC Status Register (TRCSR)
254
Timer RC I/O Control Register 0 (TRCIOR0)
255
Timer RC I/O Control Register 1 (TRCIOR1)
255
Timer RC Counter (TRC)
256
Timer RC General Registers A, B, C, and D (TRCGRA, TRCGRB, TRCGRC, TRCGRD)
256
Timer RC Control Register 2 (TRCCR2)
257
Timer RC Digital Filter Function Select Register (TRCDF)
257
Timer RC Output Master Enable Register (TRCOER)
258
Timer RC Trigger Control Register (TRCADCR)
258
Timer RC Pin Select Register (TRBRCSR)
259
Timer RC Pin Select Register 0 (TRCPSR0)
260
Timer RC Pin Select Register 1 (TRCPSR1)
260
Common Items for Multiple Modes
261
Count Source
261
Buffer Operation
262
Digital Filter
264
Forced Cutoff of Pulse Output
265
Timer Mode (Input Capture Function)
267
Timer RC I/O Control Register 0 (TRCIOR0) for Input Capture Function
269
Timer RC I/O Control Register 1 (TRCIOR1) for Input Capture Function
270
Operating Example
271
Timer Mode (Output Compare Function)
272
Timer RC Control Register 1 (TRCCR1) for Output Compare Function
274
Timer RC I/O Control Register 0 (TRCIOR0) for Output Compare Function
275
Timer RC I/O Control Register 1 (TRCIOR1) for Output Compare Function
276
Operating Example
277
Changing Output Pins in Registers TRCGRC and TRCGRD
278
PWM Mode
280
Timer RC Control Register 1 (TRCCR1) in PWM Mode
282
Timer RC Control Register 2 (TRCCR2)
282
Operating Example
284
PWM2 Mode
286
Timer RC Control Register 1 (TRCCR1) in PWM2 Mode
288
Timer RC Control Register 2 (TRCCR2) in PWM2 Mode
289
Timer RC Digital Filter Function Select Register (TRCDF) in PWM2 Mode
289
Operating Example
291
Timer RC Interrupt
294
Notes on Timer RC
295
TRC Register
295
TRCSR Register
295
TRCCR1 Register
295
Count Source Switching
295
Input Capture Function
296
TRCMR Register in PWM2 Mode
296
Count Source Foco40M
296
20. Timer RE
297
Overview
297
Real-Time Clock Mode
298
Timer RE Second Data Register (TRESEC) in Real-Time Clock Mode
300
Timer RE Minute Data Register (TREMIN) in Real-Time Clock Mode
300
Timer RE Hour Data Register (TREHR) in Real-Time Clock Mode
301
Timer RE Day of Week Data Register (TREWK) in Real-Time Clock Mode
301
Timer RE Control Register 1 (TRECR1) in Real-Time Clock Mode
302
Timer RE Control Register 2 (TRECR2) in Real-Time Clock Mode
303
Timer RE Count Source Select Register (TRECSR) in Real-Time Clock Mode
304
Operating Example
305
Output Compare Mode
306
Timer RE Counter Data Register (TRESEC) in Output Compare Mode
308
Timer RE Compare Data Register (TREMIN) in Output Compare Mode
308
Timer RE Control Register 1 (TRECR1) in Output Compare Mode
309
Timer RE Control Register 2 (TRECR2) in Output Compare Mode
309
Timer RE Count Source Select Register (TRECSR) in Output Compare Mode
310
Operating Example
311
Notes on Timer RE
312
Starting and Stopping Count
312
Register Setting
312
Time Reading Procedure of Real-Time Clock Mode
314
Serial Interface (UART0)
315
Overview
315
UART0 Block Diagram
315
Registers
317
UART0 Transmit/Receive Mode Register (U0MR)
317
UART0 Bit Rate Register (U0BRG)
317
UART0 Transmit Buffer Register (U0TB)
318
UART0 Transmit/Receive Control Register 0 (U0C0)
319
UART0 Transmit/Receive Control Register 1 (U0C1)
319
UART0 Receive Buffer Register (U0RB)
320
UART0 Pin Select Register (U0SR)
321
Clock Synchronous Serial I/O Mode
322
Polarity Select Function
326
LSB First/Msb First Select Function
326
Transfer Format
326
Continuous Receive Mode
327
Clock Asynchronous Serial I/O (UART) Mode
328
Bit Rate
333
UART Mode
333
Notes on Serial Interface (UART0)
334
Serial Interface (UART2)
335
Overview
335
UART2 Block Diagram
335
Registers
337
UART2 Transmit/Receive Mode Register (U2MR)
337
UART2 Bit Rate Register (U2BRG)
337
UART2 Transmit Buffer Register (U2TB)
338
UART2 Transmit/Receive Control Register 0 (U2C0)
339
UART2 Transmit/Receive Control Register 1 (U2C1)
340
UART2 Receive Buffer Register (U2RB)
341
UART2 Digital Filter Function Select Register (URXDF)
342
UART2 Special Mode Register 5 (U2SMR5)
342
UART2 Special Mode Register 4 (U2SMR4)
343
UART2 Special Mode Register 3 (U2SMR3)
343
UART2 Special Mode Register 2 (U2SMR2)
344
UART2 Special Mode Register (U2SMR)
344
UART2 Pin Select Register 0 (U2SR0)
345
UART2 Pin Select Register 1 (U2SR1)
345
Clock Synchronous Serial I/O Mode
346
Measure for Dealing with Communication Errors
350
CLK Polarity Select Function
350
LSB First/Msb First Select Function
351
Continuous Receive Mode
351
Serial Data Logic Switching Function
352
CTS/RTS Function
352
Clock Asynchronous Serial I/O (UART) Mode
353
Bit Rate
357
Measure for Dealing with Communication Errors
358
LSB First/Msb First Select Function
358
Serial Data Logic Switching Function
359
TXD and RXD I/O Polarity Inverse Function
359
CTS/RTS Function
360
RXD2 Digital Filter Select Function
360
Special Mode 1 (I 2 C Mode)
361
Detection of Start and Stop Conditions
367
Output of Start and Stop Conditions
368
Arbitration
369
Transfer Clock
369
SDA Output
369
SDA Input
370
ACK and NACK
370
Initialization of Transmission/Reception
370
Multiprocessor Communication Function
371
Multiprocessor Transmission
374
Multiprocessor Reception
375
RXD2 Digital Filter Select Function
377
Notes on Serial Interface (UART2)
378
Clock Synchronous Serial I/O Mode
378
Clock Asynchronous Serial I/O (UART) Mode
379
Special Mode 1 (I 2 C Mode)
379
23. Clock Synchronous Serial Interface
380
Mode Selection
380
Synchronous Serial Communication Unit (SSU)
381
Overview
381
Registers
383
Module Standby Control Register (MSTCR)
383
SSU/IIC Pin Select Register (SSUIICSR)
383
SS Bit Counter Register (SSBR)
384
SS Transmit Data Register (SSTDR)
384
SS Receive Data Register (SSRDR)
385
SS Control Register H (SSCRH)
385
SS Control Register L (SSCRL)
386
SS Mode Register (SSMR)
387
SS Enable Register (SSER)
388
SS Status Register (SSSR)
389
SS Mode Register 2 (SSMR2)
390
Common Items for Multiple Modes
391
Transfer Clock
391
SS Shift Register (SSTRSR)
393
Interrupt Requests
394
Communication Modes and Pin Functions
395
Clock Synchronous Communication Mode
396
Initialization in Clock Synchronous Communication Mode
396
Data Transmission
397
Data Reception
399
Data Transmission/Reception
401
Operation in 4-Wire Bus Communication Mode
403
Initialization in 4-Wire Bus Communication Mode
404
Data Transmission
405
Data Reception
407
SCS Pin Control and Arbitration
409
Notes on Synchronous Serial Communication Unit
410
I 2 C Bus Interface
411
Overview
411
Registers
414
Module Standby Control Register (MSTCR)
414
SSU/IIC Pin Select Register (SSUIICSR)
414
IIC Bus Transmit Data Register (ICDRT)
415
IIC Bus Receive Data Register (ICDRR)
415
IIC Bus Control Register 1 (ICCR1)
416
IIC Bus Control Register 2 (ICCR2)
417
IIC Bus Mode Register (ICMR)
418
IIC Bus Interrupt Enable Register (ICIER)
419
IIC Bus Status Register (ICSR)
420
Slave Address Register (SAR)
421
IIC Bus Shift Register (ICDRS)
421
Common Items for Multiple Modes
422
Transfer Clock
422
Interrupt Requests
423
I 2 C Bus Interface Mode
424
I2C Bus Format
424
Master Transmit Operation
425
Master Receive Operation
427
Slave Transmit Operation
430
Slave Receive Operation
433
Clock Synchronous Serial Mode
435
Clock Synchronous Serial Format
435
Transmit Operation
436
Receive Operation
437
Examples of Register Setting
438
Noise Canceller
442
Bit Synchronization Circuit
443
Notes on I 2 C Bus Interface
444
26. Hardware LIN
445
Overview
445
Input/Output Pins
446
Registers
447
LIN Control Register 2 (LINCR2)
447
LIN Control Register (LINCR)
448
LIN Status Register (LINST)
448
Function Description
449
Master Mode
449
Slave Mode
452
Bus Collision Detection Function
456
Hardware LIN End Processing
457
Interrupt Requests
458
Notes on Hardware LIN
459
27. A/D Converter
460
Overview
460
Block Diagram of A/D Converter
461
Registers
462
On-Chip Reference Voltage Control Register (OCVREFCR)
462
A/D Register I (Adi) (I = 0 to 7)
463
A/D Mode Register (ADMOD)
464
A/D Input Select Register (ADINSEL)
465
A/D Control Register 0 (ADCON0)
466
A/D Control Register 1 (ADCON1)
467
Common Items for Multiple Modes
468
Input/Output Pins
468
A/D Conversion Cycles
468
A/D Conversion Start Condition
470
Software Trigger
470
External Trigger
470
A/D Conversion Result
471
Low Current Consumption Function
471
Extended Analog Input Pins
471
A/D Open-Circuit Detection Assist Function
471
One-Shot Mode
473
Repeat Mode 0
474
Repeat Mode 1
475
Single Sweep Mode
477
Repeat Sweep Mode
479
Internal Equivalent Circuit of Analog Input
481
27.10 Output Impedance of Sensor under A/D Conversion
482
27.11 Notes on A/D Converter
483
28. Comparator a
484
Overview
484
Registers
486
Voltage Monitor Circuit/Comparator a Control Register (CMPA)
486
Voltage Monitor Circuit Edge Select Register (VCAC)
486
Voltage Detect Register (VCA1)
487
Voltage Detect Register 2 (VCA2)
488
Voltage Monitor 1 Circuit Control Register (VW1C)
489
Voltage Monitor 2 Circuit Control Register (VW2C)
490
Monitoring Comparison Results
491
Monitoring Comparator A1
491
Monitoring Comparator A2
491
Functional Description
492
Comparator A1
492
Comparator A2
495
Comparator A1 and Comparator A2 Interrupts
498
Non-Maskable Interrupts
498
Maskable Interrupts
498
29. Comparator B
499
Overview
499
Specification
499
Registers
501
Comparator B Control Register (INTCMP)
501
External Input Enable Register 0 (INTEN)
501
INT Input Filter Select Register 0 (INTF)
502
Functional Description
503
Comparator Bi Digital Filter (I = 1 or 3)
504
Comparator B1 and Comparator B3 Interrupts
505
30. Flash Memory
506
Overview
506
Memory Map
507
Functions to Prevent Flash Memory from Being Rewritten
508
ID Code Check Function
508
ROM Code Protect Function
509
Option Function Select Register (OFS)
509
CPU Rewrite Mode
510
Flash Memory Status Register (FST)
511
Flash Memory Control Register 0 (FMR0)
513
Flash Memory Control Register 1 (FMR1)
515
Flash Memory Control Register 2 (FMR2)
517
EW0 Mode
518
EW1 Mode
518
Suspend Operation
518
How to Set and Exit each Mode
519
BGO (Background Operation) Function
520
30.4.10 Data Protect Function
521
30.4.11 Software Commands
522
Read Array Command
522
Read Status Register Command
522
Program Command
523
30.4.12 Status Register
532
30.4.13 Sequence Status
532
30.4.14 Erase Status
532
30.4.15 Program Status
532
30.4.16 Suspend Status
532
30.4.17 Full Status Check
533
Standard Serial I/O Mode
535
ID Code Check Function
535
Parallel I/O Mode
538
ROM Code Protect Function
538
Notes on Flash Memory
539
CPU Rewrite Mode
539
Non-Maskable Interrupts
539
How to Access
541
31. Reducing Power Consumption
542
Overview
542
Key Points and Processing Methods for Reducing Power Consumption
542
Voltage Detection Circuit
542
Ports
542
Clocks
542
Wait Mode, Stop Mode
542
Stopping Peripheral Function Clocks
542
Timers
542
A/D Converter
542
Reducing Internal Power Consumption
543
31.2.10 Stopping Flash Memory
544
31.2.11 Low-Current-Consumption Read Mode
545
Others
545
32. Electrical Characteristics
546
33. Usage Notes
573
Notes on Clock Generation Circuit
573
Stop Mode
573
Wait Mode
573
Oscillation Stop Detection Function
573
Oscillation Circuit Constants
573
Notes on Interrupts
574
Reading Address 00000H
574
SP Setting
574
External Interrupt and Key Input Interrupt
574
Changing Interrupt Sources
575
Rewriting Interrupt Control Register
576
Notes on ID Code Areas
577
Setting Example of ID Code Areas
577
Notes on Option Function Select Area
577
Setting Example of Option Function Select Area
577
Notes on DTC
578
DTC Activation Source
578
Dtceni Registers (I = 0 to 3, 5, 6)
578
Peripheral Modules
578
Notes on Timer RA
579
Notes on Timer RB
580
Timer Mode
580
Programmable Waveform Generation Mode
580
Programmable One-Shot Generation Mode
580
Programmable Wait One-Shot Generation Mode
581
Notes on Timer RC
582
TRC Register
582
TRCSR Register
582
TRCCR1 Register
582
Count Source Switching
582
Input Capture Function
583
TRCMR Register in PWM2 Mode
583
Count Source Foco40M
583
Notes on Timer RE
584
Starting and Stopping Count
584
Register Setting
584
Time Reading Procedure of Real-Time Clock Mode
586
Notes on Serial Interface (UART0)
587
Notes on Serial Interface (UART2)
588
33.11.1 Clock Synchronous Serial I/O Mode
588
33.11.2 Clock Asynchronous Serial I/O (UART) Mode
589
Special Mode
589
Mode)
589
33.12 Notes on Synchronous Serial Communication Unit
590
Notes on I C Bus Interface
590
33.14 Notes on Hardware LIN
590
33.15 Notes on A/D Converter
590
Usage Notes
591
33.16 Notes on Flash Memory
591
33.16.1 CPU Rewrite Mode
591
33.17 Notes on Noise
594
Inserting a Bypass Capacitor between VCC and VSS Pins as a Countermeasure against Noise and Latch-Up
594
Notes on On-Chip Debugger
595
Appendix 1. Package Dimensions
596
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator
597
Appendix 3. Example of Oscillation Evaluation Circuit
598
Revision History Revision History
601

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