4-3 FREQUENCY SYNTHESIZER (MAIN UNIT)
• VCO
The VCO (Q3, Q4, and D1–D3) generates both 1st LO signal
for MAIN channels and the TX signal.
The output of buffer (Q7) is used as the TX or RX LO signal.
While receiving, the LO signal is applied to the 1st IF mixer
for MAIN channels (Q202), through the LO SW (D8) and LPF
(L206 and L207).
While transmitting, the LO signal is applied to the TX AMP
circuits, through the LO SW (D7).
• FREQUENCY SYNTHESIZER CIRCUITS
IC201
IF IC
IC101
21.25MHz
X101
PLL
MAIN UNIT
LOOP
FILTER
Q2,Q8
D1,D2
MOD
SHIFT
From the TX AF circuits
4-4 VOLTAGE BLOCK DIAGRAM
Voltage from the power supply is routed throughout the transceiver, through regulators and switches.
Q511,Q512
HV
Power
PWR
supply
CTRL
MAIN UNIT
LOGIC UNIT
IC4
3.3 V
REG
Q6
Q7
BUFF
BUFF
VCO UNIT
Q3,Q4
Q5
D3
VCO
BUFF
IC512
Q10,Q11
VCC
+5 V
5V
REG
IC511
Q21,Q22
Receive
R8
R8V
circuits
REG
L3V
CPU
• PLL
A portion of VCO output signal is passed through two buffers
(Q5 and Q6), and then fed back to the PLL IC (IC101, pin
16).
The PLL IC (IC101) phase-compares the outputs of the refer-
ence frequency oscillator (TCXO; X101) and VCO, and the
phase-difference is output as the charge pump current.
The current is passed though the loop fi lter (R1–R3, C1–C3,
and C10) to be converted into the lock voltage, which controls
the oscillating frequency of VCO.
When the oscillation frequency drifts, its phase changes from
that of the reference frequency, causing a lock voltage change
to compensate for the drift in the VCO oscillating frequency.
Q202
1st mixer
(MAIN CH)
D7,D8
To the TX AMP circuits
TX/RX
SW
T5
T5V
CTRL
Q12,Q23,Q24
3V
+3 V
R3
REG
CTRL
IC903
+1.1 V
REG
4 - 4
Transmit circuits
R3V
Receive circuits
Noise canceller
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