Icom IC-551D Instruction Manual page 45

fed through D4 and 05 to the K1 М and K2 ® terminals of the CPU. At the same time, an UP or
DOWN signal (UD) is fed through D3 to the K8 © terminal. The output of D3 becomes H-level at
the UP count and L-level at the DOWN count. K1 and K2 data are added to or subtracted from
the preset frequency (50.1MHz) according to the UP/DOWN signal.
-In other words, addition or subtraction functions are made according to the data read from the
pulse interval of R2 and this operation is repeated after each clearance made by the pulse signals
from R7.
CPU CONTROL CIRCUIT
The CPU in the unit is a4-bit CPU and the input terminals are K1, K2, K4 and K8 only.
Since the CPU can not make many functions with the small number of K input signals, to increase
the functions of the CPU, scanning R output signals (RO ~ R6) are fed to K input terminals through
the matrix circuit as shown in the figure below. The CPU reads the relationship of R output and
_ K input signals to decide the function as follows: |
CPU output
|
CPU input
Simulated Matrix Circuit Schematic Diagram
(D 81— К1 (VFO A)
This flow occurs when the VFO select switch is set at "А", and the unit operates at the
frequency set by "А" VFO.
(2) 81— К2 (МЕО В) | |
This. flow occurs when the VFO select switch is set at "B", and the unit operates at the
frequency set by "B" VFO.
(8 R1 КА (MS)
This flow occurs when the VFO select switch is set at "MS". In this setting, when the flow of
(2 occurs, the three memory channels are scanned in the order of 1, 2, 3, 1, 2, 3, . . . with the
flow of (9 as a clock.
(4 R1 к (А > B)
This flow occurs when the VFO select switch is set at "А — В". The data in the "А" VFO is
input to the "B" VFO and the "B" VFO frequency becomes equal to that of the "A" VFO.
R2- K1 (COUNT 1)
22 > K2 (COUNT 2) |
The signals of © апа © express the data between 0 and 3 to add ог substract.
© ©
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