Icom IC-551D Instruction Manual page 42

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steps is set by the 100Hz-step variation of the local oscillator (VXO) frequency.
PHASE DETECTOR AND LOOP FILTER CIRCUIT
Digital phase detector ІС2 detects the phase difference of the pulse signals at Pin 7, the 10KHz
reference frequency, signal and Pin 8, the output signal of the programmable divider, and propor-
tionately puts out positive/negative pulse signals at Pin 3, which become high impedance when the
PLL is locked. Pin 4 is for detecting the lock failures and changes to ground level according to the
phase difference of the two pulse signals.
INPUT/OUTPUT WAVE FORMS OF PHASE DETECTOR 1С2
PIN | |
7
3 || | | High Impedance
A part of the output voltage of the loop filter is fed to noninverting amplifier ІС6/1 and amplified.
The output signal is fed to D2 of the VCO unit to preset the VCO frequency near the desired
frequency.
BUFFER AMPLIFIER CIRCUIT
The VCO output signals аге fed to buffer amplifier O8. They are then fed to Pin 11 of mixer 1C5,
and to buffer amplifiers Q6 and Q7, of which the output signals are fed through the low pass filter,
consisting of L2, C51, C52 and C53, to the transmit and receive mixers in the Main Unit.
LOCK FAILURE DETECTOR AND MUTE CONTROL CIRCUIT
When the lock fails, the pulse signal from Pin 4 is integrated by R18 and C18. When the integrated
signal level exceeds the junction voltage of 01% base, O1 is turned ON and then Q2 is turned ON.
The collector of Q2 is connected to the base of O6, so the base voltage of Q6 becomes ground
level, and Q6 and Q7 are shut OFF to prevent transmitting unwanted signals.
POWER CIRCUIT
The PLL Unit has *8V and —8V regulated power circuits. When the power is turned ON, a current
flow charges C61 through the emitter and the base of Q9. This turns 09 ON, and regulator ІС?
puts out a regulated 8V, which is then divided by R52 and R53 and fed to the base of Q10 to turn