Toshiba TX TMPM471F10FG Reference Manual
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Toshiba TX TMPM471F10FG Reference Manual

Toshiba TX TMPM471F10FG Reference Manual

32-bit risc microcontroller
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TX Family
TMPM471F10FG
Exception
32-Bit RISC Microcontroller
TX Family
TMPM471F10FG
Reference Manual
Exception
(EXCEPT-TMPM471F10FG)
Revision 1.0
2024-08
© 2024
1 / 66
2024-08-30
Toshiba Electronic Devices & Storage Corporation
Rev. 1.0

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Summary of Contents for Toshiba TX TMPM471F10FG

  • Page 1 TX Family TMPM471F10FG Exception 32-Bit RISC Microcontroller TX Family TMPM471F10FG Reference Manual Exception (EXCEPT-TMPM471F10FG) Revision 1.0 2024-08 © 2024 1 / 66 2024-08-30 Toshiba Electronic Devices & Storage Corporation Rev. 1.0...

  • Page 2: Table Of Contents

    TX Family TMPM471F10FG Exception Contents Preface ................................. 5 Related document ..............................5 Conventions ................................6 Terms and Abbreviations ............................8 Outlines ................................. 9 1.1. Exception Types ..............................9 1.2. Exception Handling Flowchart ......................... 10 1.2.1. Exception Request and Detection ..........................11 1.2.2.
  • Page 3 TX Family TMPM471F10FG Exception 5.4.1. [RLMRSTFLG0] (Reset Flag Register 0) ........................40 5.4.2. [RLMRSTFLG1] (Reset Flag Register 1) ........................41 5.5. Interrupt Monitor Registers ..........................42 5.5.1. [IMNFLGNMI] (Non-Maskable Interrupt Monitor Flag Register).................. 42 5.5.2. [IMNFLG3] (Interrupt Monitor Flag Register 3) ......................43 5.5.3.
  • Page 4 TX Family TMPM471F10FG Exception List of Figures Figure 4.1 Interrupt Transfer Route Diagram ................... 19 List of Tables Table 1.1 Exception Types and Priority ....................11 Table 1.2 Priority Grouping Setting ......................12 Table 4.1 Explanation of Each Interrupt Transfer Route ................. 20 Table 4.2 List of Interrupt Factors (Non-Maskable Interrupt)..............

  • Page 5: Preface

    TX Family TMPM471F10FG Exception Preface Related document Document name Oscillation Frequency Detector Clock Selective Watchdog Timer Voltage Detection Circuit Clock Control and Operation Mode ® ® Cortex -M4 Processor Technical Reference Manual 5 / 66 2024-08-30 Rev. 1.0...

  • Page 6: Conventions

    TX Family TMPM471F10FG Exception Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 - It is possible to omit the "0b" when the number of bits can be distinctly understood from a sentence.
  • Page 7 TX Family TMPM471F10FG Exception *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.

  • Page 8: Terms And Abbreviations

    TX Family TMPM471F10FG Exception Terms and Abbreviations Some of abbreviations used in this document are as follows: Analog to Digital Converter A-ENC32 Advanced Encoder Input Circuit (32-bit) A-PMD Advanced Programmable Motor Control Circuit DMAC Direct Memory Access Controller EI2C C Interface Version A Interrupt Control Register A Interrupt Control Register B IMCxx...

  • Page 9: Outlines

    TX Family TMPM471F10FG Exception Exceptions have close relation to the CPU core. Refer to "Arm Cortex-M4 Processor Technical Reference Manual" if needed. 1. Outlines Exceptions require CPU to suspend the currently executing process, and to start another process. There are two types of exceptions: those that are generated when some error condition occurs or when an instruction to generate an exception is executed;...

  • Page 10: Exception Handling Flowchart

    TX Family TMPM471F10FG Exception 1.2. Exception Handling Flowchart The following shows how an exception/interrupt is handled. In the following descriptions, exception handling by hardware and that by software are explained. Each step is described later in this reference manual. Process Description Refer to Detection by...

  • Page 11: Exception Request And Detection

    TX Family TMPM471F10FG Exception 1.2.1. Exception Request and Detection Exception occurrence Exception factors include instruction execution by the CPU, memory accesses, and interrupt requests from external interrupt pins or peripheral functions. An exception by the instruction execution occurs when the CPU executes an instruction that causes an exception or when an error condition occurs during instruction execution.

  • Page 12: Table 1.2 Priority Grouping Setting

    TX Family TMPM471F10FG Exception Priority setting ● Priority Level The external interrupt priority is set to the Interrupt Priority Register and other exceptions are set to <PRI_n> bit in the System Handler Priority Register. The configuration <PRI_n> can be changed, and the number of bits required for setting the priority varies from 3 bits to 8 bits depending on products.

  • Page 13: Exception Handling And Branch To Interrupt Service Routine (Pre-Emption)

    TX Family TMPM471F10FG Exception 1.2.2. Exception Handling and Branch to Interrupt Service Routine (Pre-emption) When an exception occurs, the CPU suspends the currently executing process and branches to the interrupt service routine. This is called "pre-emption". Stacking When the CPU detects an exception, it pushes the contents of the following eight registers to the stack in the following order: (a) Program Counter (PC) (b) Program Status Register (xPSR)

  • Page 14: Executing Isr

    TX Family TMPM471F10FG Exception Vector table The vector table is configured as shown below. You must always set the first four words (stack top address, reset ISR address, NMI ISR address, and Hard Fault ISR address). Set ISR addresses for other exceptions if necessary. For other exceptions, you should prepare the ISR addresses if necessary.

  • Page 15: Exception Exit

    TX Family TMPM471F10FG Exception 1.2.4. Exception Exit Execution after returning from ISR When returning from an ISR, the CPU takes one of the following actions: (a) Tail-chaining If a pending exception exists and there are no stacked exceptions or the pending exception has higher priority than all stacked exceptions, the CPU returns to the ISR of the pending exception.

  • Page 16: Reset Exception

    TX Family TMPM471F10FG Exception 2. Reset Exception Reset exceptions are generated from the following factors. Use reset flag register [RLMRSTFLGn] to identify the factor of a reset. ● Reset exception by external reset pin A reset exception occurs when an external reset pin changes from "Low" to "High". ●...

  • Page 17: Systick

    TX Family TMPM471F10FG Exception 3. SysTick SysTick provides interrupt features using the CPU's system timer. When setting a value in the SysTick Reload Value Register and enable the SysTick features by the SysTick Control and Status Register, the counter loads with the value set in the Reload Value Register and begins counting down.

  • Page 18: Interrupt Request

    TX Family TMPM471F10FG Exception 4.3. Interrupt Request The CPU is notified of interrupt requests by the interrupt signal from each interrupt factor. It sets priority on interrupts and generates the interrupt request with the highest priority. 4.3.1. Interrupt Route The interrupt is available for the release from a low-power consumption mode, and a route varies according to a factor.

  • Page 19: Figure 4.1 Interrupt Transfer Route Diagram

    TX Family TMPM471F10FG Exception INTIF NVIC register/ interrupt mask register Interrupt Control Register A Interrupt Route A Peripheral detection function logic [IANIC00] <INTNFLG><INTNCLR> IDLE STOP1 [IAIMCxx] release sources External <INTEN> Route B interrupt Interrupt Active level detection select logic logic [IAIMCxx] <INTPFLG><INTPCLR>...

  • Page 20: Table 4.1 Explanation Of Each Interrupt Transfer Route

    TX Family TMPM471F10FG Exception Table 4.1 Explanation of Each Interrupt Transfer Route Route Interrupt No. Interrupt request Description of route This route is non-maskable interrupt. It is a route input into CPU via INTIF. LVD interrupt An interrupt release setup is carried out by the interrupt control register A ([IANIC00]).

  • Page 21: Interrupt Request Generation

    TX Family TMPM471F10FG Exception 4.3.2. Interrupt Request Generation An interrupt request is generated from an external interrupt pin or peripheral function which are assigned as interrupt request factors, or setting the relevant bit of NVIC's interrupt set-pending register for interrupt factor. ●...

  • Page 22: List Of Interrupt Factors

    TX Family TMPM471F10FG Exception 4.4. List of Interrupt Factors Table 4.2 shows the list of interrupt factors of non-maskable interrupts. The setting for clearing the NMI factors can be done by Interrupt Control Registers A and B Table 4.2 List of Interrupt Factors (Non-Maskable Interrupt) Interrupt control Interrupt monitor Interrupt factor...

  • Page 23: Table 4.4 List Of Interrupt Factors (Interrupt Control Register B) (2/3)

    TX Family TMPM471F10FG Exception Table 4.4 List of Interrupt Factors (Interrupt Control Register B) (2/3) Interrupt Interrupt Interrupt Interrupt factor Interrupt request control monitor register register INTEMG0 A-PMD ch0 EMG Interrupt INTEMG1 A-PMD ch1 EMG Interrupt INTOVV0 A-PMD ch0 OVV Interrupt INTOVV1 A-PMD ch1 OVV Interrupt INTPWM0...

  • Page 24: Table 4.5 List Of Interrupt Factors (Interrupt Control Register B) (3/3)

    TX Family TMPM471F10FG Exception Table 4.5 List of Interrupt Factors (Interrupt Control Register B) (3/3) Interrupt Interrupt Interrupt Interrupt factor Interrupt request control monitor register register INTI2C0RBF EI2C ch0 receive buffer full interrupt INTI2C1ST EI2C ch1 status interrupt INTI2C1TBE EI2C ch1 transmit buffer empty interrupt INTI2C1RBF EI2C ch1 receive buffer full interrupt INTT32A00AC (Note)

  • Page 25: Joint Interrupt

    TX Family TMPM471F10FG Exception 4.4.1. Joint Interrupt Details of the joint interrupts in TMPM471F10FG are as follows. Table 4.6 Joint Interrupt List (1/3) Interrupt Interrupt Interrupt Joint interrupt Interrupt factor Interrupt request control monitor factor register register INTT0RX TSPI ch0 reception interrupt INTSC0RX INTUART0RX UART ch0 reception interrupt...

  • Page 26: Table 4.7 Joint Interrupt List (2/3)

    TX Family TMPM471F10FG Exception Table 4.7 Joint Interrupt List (2/3) Interrupt Interrupt Interrupt Joint interrupt factor Interrupt factor Interrupt request control monitor register register INTT32A00A T32A ch0 timer A match, overflow, and underflow INTT32A00AC INTT32A00C T32A ch0 timer C match, overflow, and underflow INTT32A00ACAP0 T32A ch0 timer A capture 0 INTT32A00ACCAP0...

  • Page 27: Table 4.8 Joint Interrupt List (3/3)

    TX Family TMPM471F10FG Exception Table 4.8 Joint Interrupt List (3/3) Interrupt Interrupt Interrupt monitor Interrupt request control register register [IBIMC016] [IMNFLG3]<INT112FLG> [IBIMC017] [IMNFLG3]<INT113FLG> [IBIMC018] [IMNFLG3]<INT114FLG> [IBIMC019] [IMNFLG3]<INT115FLG> [IBIMC020] [IMNFLG3]<INT116FLG> [IBIMC021] [IMNFLG3]<INT117FLG> [IBIMC022] [IMNFLG3]<INT118FLG> [IBIMC023] [IMNFLG3]<INT119FLG> [IBIMC024] [IMNFLG3]<INT120FLG> [IBIMC025] [IMNFLG3]<INT121FLG> ch10 [IBIMC026] [IMNFLG3]<INT122FLG>...

  • Page 28: Interrupt Detection Level

    TX Family TMPM471F10FG Exception 4.5. Interrupt Detection Level When using interrupt via INTIF, interrupt detection level ("Low" level/"High" level/Rising edge/Falling edge) can be selected by interrupt control register A or B. The detected interrupt is output to the CPU with a "High" level signal.

  • Page 29: Interrupt Handling

    TX Family TMPM471F10FG Exception 4.6. Interrupt Handling 4.6.1. Flowchart of Interrupt Handling The following shows the flowchart of interrupt handling. The flowchart below explains the interrupt handling process by hardware and software. Processing Details Refer to Set the relevant NVIC registers for detecting interrupts. Setting INTIF for the interrupt which is used as releasing the low-power consumption mode is required to set an interrupt detection level.

  • Page 30: Preparation

    TX Family TMPM471F10FG Exception 4.6.2. Preparation When preparing for an interrupt, you need to pay attention to the order of configuration to avoid any unexpected interrupt on the way. Initiating an interrupt or changing its configuration must be implemented in the following order basically. First, disable the interrupt by the CPU.
  • Page 31 TX Family TMPM471F10FG Exception Preparation interrupt request (1) (Interrupt from external pin) In order to use external interrupt pin, port setting for the corresponding pin is required. Setting [PxIE]<PxmIE> to "1" allows the pin to be used as the input port. Port register ←...

  • Page 32: Detection (Intif)

    TX Family TMPM471F10FG Exception Enabling Interrupt by CPU Enable the interrupt by the CPU as shown below. Clear the pended interrupt by the interrupt clear-pending register. Enable an interrupt by the interrupt set-enable register. A bit of these registers is assigned to each interrupt factor. Writing "1"...

  • Page 33: Processing In Interrupt Service Routine (Clearing Interrupt Factor)

    TX Family TMPM471F10FG Exception 4.6.6. Processing in Interrupt Service Routine (Clearing Interrupt Factor) An ISR requires specific programming according to the application to be used. This section describes about recommend process and clearing an interrupt factor. Process in ISR An ISR normally pushes register contents to the stack and handles an interrupt processing. The Cortex-M4 processor with FPU automatically pushes the contents of xPSR, PC, LR, r12, and r3 to r0 to the stack.

  • Page 34: Exception/Interrupt-Related Registers

    TX Family TMPM471F10FG Exception 5. Exception/Interrupt-related Registers 5.1. Register List Control registers and their addresses are as follows. Interrupt Control Register A Peripheral function Channel/Unit Base Address Interrupt control register A 0x4003E000 Register name Address (+BASE) Non-Maskable Interrupt A Control Register 00 [IANIC00] 0x0000 Note: Byte access is needed for the interrupt control register A.
  • Page 35 TX Family TMPM471F10FG Exception Interrupt Control Registers B Peripheral function Channel/Unit Base Address Interrupt control register B 0x40083200 Register name Address (+BASE) Non-Maskable Interrupt B Control Register 00 [IBNIC00] 0x0010 Interrupt B Mode Control Register 000 [IBIMC000] 0x0060 Interrupt B Mode Control Register 001 [IBIMC001] 0x0061 Interrupt B Mode Control Register 002...
  • Page 36 TX Family TMPM471F10FG Exception Register name Address (+BASE) Interrupt B Mode Control Register 040 [IBIMC040] 0x0088 Interrupt B Mode Control Register 041 [IBIMC041] 0x0089 Interrupt B Mode Control Register 042 [IBIMC042] 0x008A Interrupt B Mode Control Register 043 [IBIMC043] 0x008B Interrupt B Mode Control Register 044 [IBIMC044] 0x008C...
  • Page 37 TX Family TMPM471F10FG Exception NVIC Registers Peripheral function Channel/Unit Base Address NVIC register 0xE000E000 Register name Address (+BASE) SysTick Control and Status Register 0x0010 SysTick Reload Value Register 0x0014 SysTick Current Value Register 0x0018 SysTick Calibration Value Register 0x001C Interrupt Set-Enable Register 0 0x0100 Interrupt Set-Enable Register 1 0x0104...

  • Page 38: Interrupt Control Register A

    TX Family TMPM471F10FG Exception 5.2. Interrupt Control Register A 5.2.1. [IANIC00] (Non-Maskable Interrupt A Control Register 00) Bit symbol After reset Type Function Detection flag clear control 0: - INTNCLR 1: Clear Read as "0". Read as "0". Detection flag INTNFLG 0: Not detected 1: Detected...

  • Page 39: Ibimc000] To [Ibimc095] Interrupt B Mode Control Registers)

    TX Family TMPM471F10FG Exception 5.3.2. [IBIMC000] to [IBIMC095] Interrupt B Mode Control Registers) [IBIMC000] to [IBIMC015] registers Bit symbol After reset Type Function Falling edge detection flag clear control 0: - INTNCLR 1: Clear Read as "0". Rising edge detection flag clear control 0: - INTPCLR 1: Clear...

  • Page 40: Reset Flag Registers

    TX Family TMPM471F10FG Exception 5.4. Reset Flag Registers 5.4.1. [RLMRSTFLG0] (Reset Flag Register 0) After Bit symbol power-on Type Function reset Undefined Read as an undefined value. LVD/PORF reset flag 0: - 1: Reset by LVD/PORF LVDRSTF Undefined LVD/PORF reset flag 0: Clear 1: don’t care Undefined...

  • Page 41: Rlmrstflg1] (Reset Flag Register 1)

    TX Family TMPM471F10FG Exception 5.4.2. [RLMRSTFLG1] (Reset Flag Register 1) After Bit symbol power-on Type Function reset Read as "0". OFD reset flag 0: - 1: Reset by OFD OFDRSTF OFD reset flag 0: Clear 1: don’t care SIWDT reset flag 0: - 1: Reset by SIWDT WDTRSTF...

  • Page 42: Interrupt Monitor Registers

    TX Family TMPM471F10FG Exception 5.5. Interrupt Monitor Registers 5.5.1. [IMNFLGNMI] (Non-Maskable Interrupt Monitor Flag Register) Bit symbol After reset Type Function 31:17 Read as "0". INTWDT0 interrupt detection flag INT016FLG 0: Interrupt not detected 1: Interrupt detected 15:1 Read as "0". INTLVD interrupt detection flag INT000FLG 0: Interrupt not detected...

  • Page 43: Imnflg3] (Interrupt Monitor Flag Register 3)

    TX Family TMPM471F10FG Exception 5.5.2. [IMNFLG3] (Interrupt Monitor Flag Register 3) Bit symbol After reset Type Function INTDMAATC (ch15) interrupt detection flag INT127FLG 0: Interrupt not detected 1: Interrupt detected INTDMAATC (ch14) interrupt detection flag INT126FLG 0: Interrupt not detected 1: Interrupt detected INTDMAATC (ch13) interrupt detection flag INT125FLG...
  • Page 44 TX Family TMPM471F10FG Exception Bit symbol After reset Type Function INTB interrupt detection flag INT107FLG 0: Interrupt not detected 1: Interrupt detected INTA interrupt detection flag INT106FLG 0: Interrupt not detected 1: Interrupt detected INT9 interrupt detection flag INT105FLG 0: Interrupt not detected 1: Interrupt detected INT8 interrupt detection flag INT104FLG...

  • Page 45: Imnflg4] (Interrupt Monitor Flag Register 4)

    TX Family TMPM471F10FG Exception 5.5.3. [IMNFLG4] (Interrupt Monitor Flag Register 4) Bit symbol After reset Type Function 31:17 Read as "0". INTDMAAERR interrupt detection flag INT144FLG 0: Interrupt not detected 1: Interrupt detected INTDMAATC (ch31) interrupt detection flag INT143FLG 0: Interrupt not detected 1: Interrupt detected INTDMAATC (ch30) interrupt detection flag INT142FLG...

  • Page 46: Nvic Registers

    TX Family TMPM471F10FG Exception 5.6. NVIC Registers 5.6.1. SysTick Control and Status Register Bit symbol After reset Type Function 31:17 Read as "0". 0: Timer not counted to 0 1: Timer counted to 0 COUNTFLAG Returns "1" if timer counted to "0" since last time this was read. Clears on read of any part of the SysTick Control and Status Register.

  • Page 47: Systick Calibration Value Register

    TX Family TMPM471F10FG Exception 5.6.4. SysTick Calibration Value Register Bit symbol After reset Type Function 0: Reference clock provided NOREF 1: No reference clock 0: Calibration value is 10 ms. SKEW 1: Calibration value is not 10ms. 29:24 Read as "0". 23:0 TENMS 0x000000...

  • Page 48: Interrupt Control Registers

    TX Family TMPM471F10FG Exception 5.6.5. Interrupt Control Registers Following registers are used to control each interrupt factor; interrupt set-enable register, interrupt clear-enable register, interrupt set-pending register, and interrupt clear-pending register. 5.6.5.1. Interrupt Set-Enable Registers These registers can enable interrupts and check enable/disable condition of interrupts. Writing "1"...
  • Page 49 TX Family TMPM471F10FG Exception Interrupt Set-Enable Register 1 Bit symbol After reset Type Function SETENA (Interrupt 63) SETENA (Interrupt 62) SETENA (Interrupt 61) SETENA (Interrupt 60) SETENA (Interrupt 59) SETENA (Interrupt 58) SETENA (Interrupt 57) SETENA (Interrupt 56) SETENA (Interrupt 55) SETENA (Interrupt 54) SETENA (Interrupt 53) SETENA (Interrupt 52)
  • Page 50 TX Family TMPM471F10FG Exception Interrupt Set-Enable Register 2 Bit symbol After reset Type Function SETENA (Interrupt 95) SETENA (Interrupt 94) SETENA (Interrupt 93) SETENA (Interrupt 92) SETENA (Interrupt 91) SETENA (Interrupt 90) SETENA (Interrupt 89) SETENA (Interrupt 88) SETENA (Interrupt 87) SETENA (Interrupt 86) SETENA (Interrupt 85) SETENA (Interrupt 84)

  • Page 51: Interrupt Clear-Enable Registers

    TX Family TMPM471F10FG Exception 5.6.5.2. Interrupt Clear-Enable Registers These registers can disable interrupts and check enable/disable condition of interrupts. Writing "1" to a bit in these registers disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can check the enable/disable state of the corresponding interrupts. Interrupt Clear-Enable Register 0 Bit symbol After reset...
  • Page 52 TX Family TMPM471F10FG Exception Interrupt Clear-Enable Register 1 Bit symbol After reset Type Function CLRENA (Interrupt 63) CLRENA (Interrupt 62) CLRENA (Interrupt 61) CLRENA (Interrupt 60) CLRENA (Interrupt 59) CLRENA (Interrupt 58) CLRENA (Interrupt 57) CLRENA (Interrupt 56) CLRENA (Interrupt 55) CLRENA (Interrupt 54) CLRENA (Interrupt 53) CLRENA (Interrupt 52)
  • Page 53 TX Family TMPM471F10FG Exception Interrupt Clear-Enable Register 2 Bit symbol After reset Type Function CLRENA (Interrupt 95) CLRENA (Interrupt 94) CLRENA (Interrupt 93) CLRENA (Interrupt 92) CLRENA (Interrupt 91) CLRENA (Interrupt 90) CLRENA (Interrupt 89) CLRENA (Interrupt 88) CLRENA (Interrupt 87) CLRENA (Interrupt 86) CLRENA (Interrupt 85) CLRENA (Interrupt 84)

  • Page 54: Interrupt Set-Pending Registers

    TX Family TMPM471F10FG Exception 5.6.5.3. Interrupt Set-Pending Registers These registers can force interrupts into the pending state and check that interrupts are currently pending. Writing "1" to a bit in these registers pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled.
  • Page 55 TX Family TMPM471F10FG Exception Interrupt Set-Pending Register 1 Bit symbol After reset Type Function SETPEND (Interrupt 63) Undefined SETPEND (Interrupt 62) Undefined SETPEND (Interrupt 61) Undefined SETPEND (Interrupt 60) Undefined SETPEND (Interrupt 59) Undefined SETPEND (Interrupt 58) Undefined SETPEND (Interrupt 57) Undefined SETPEND (Interrupt 56) Undefined...
  • Page 56 TX Family TMPM471F10FG Exception Interrupt Set-Pending Register 2 Bit symbol After reset Type Function SETPEND (Interrupt 95) Undefined SETPEND (Interrupt 94) Undefined SETPEND (Interrupt 93) Undefined SETPEND (Interrupt 92) Undefined SETPEND (Interrupt 91) Undefined SETPEND (Interrupt 90) Undefined SETPEND (Interrupt 89) Undefined SETPEND (Interrupt 88) Undefined...

  • Page 57: Interrupt Clear-Pending Registers

    TX Family TMPM471F10FG Exception 5.6.5.4. Interrupt Clear-Pending Registers These registers can clear pending interrupts and check that interrupts are currently pending. Writing "1" to a bit in these registers clears the corresponding pending interrupt. However, writing "1" has no effect on an interrupt that is already being serviced. Writing "0"...
  • Page 58 TX Family TMPM471F10FG Exception Interrupt Clear-Pending Register 1 Bit symbol After reset Type Function CLRPEND (Interrupt 63) Undefined CLRPEND (Interrupt 62) Undefined CLRPEND (Interrupt 61) Undefined CLRPEND (Interrupt 60) Undefined CLRPEND (Interrupt 59) Undefined CLRPEND (Interrupt 58) Undefined CLRPEND (Interrupt 57) Undefined CLRPEND (Interrupt 56) Undefined...
  • Page 59 TX Family TMPM471F10FG Exception Interrupt Clear-Pending Register 2 Bit symbol After reset Type Function CLRPEND (Interrupt 95) Undefined CLRPEND (Interrupt 94) Undefined CLRPEND (Interrupt 93) Undefined CLRPEND (Interrupt 92) Undefined CLRPEND (Interrupt 91) Undefined CLRPEND (Interrupt 90) Undefined CLRPEND (Interrupt 89) Undefined CLRPEND (Interrupt 88) Undefined...

  • Page 60: Interrupt Priority Register

    TX Family TMPM471F10FG Exception 5.6.6. Interrupt Priority Register Each interrupt is provided with eight bits of the interrupt priority register. The following shows the addresses of the interrupt priority registers corresponding to interrupt numbers. Address 0xE000E400 PRI_3 PRI_2 PRI_1 PRI_0 0xE000E404 PRI_7 PRI_6...

  • Page 61: Vector Table Offset Register

    TX Family TMPM471F10FG Exception The number of bits to be used for assigning a priority varies with each product. This product uses four bits for assigning a priority. The following shows the configuration of the interrupt priority registers for interrupt numbers 0 to 3. Unused bits return "0"...

  • Page 62: Application Interrupt And Reset Control Register

    TX Family TMPM471F10FG Exception 5.6.8. Application Interrupt and Reset Control Register Bit symbol After reset Type Function Register key Writing to this register requires 0x05FA in the <VECTKEY>. VECTKEY/ 31:16 Undefined VECTKEYSTAT[15:0] Register key Read as "0xFA05". Endianness bit (Note 1) ENDIANESS 0: Little endian 1: Big endian...

  • Page 63: System Handler Priority Register

    TX Family TMPM471F10FG Exception 5.6.9. System Handler Priority Register Each exception is provided with eight bits of the system handler priority register. The following shows the addresses of the system handler priority registers corresponding to each exception. Address PRI_4 PRI_6 PRI_5 0xE000ED18 PRI_7...

  • Page 64: System Handler Control And Status Register

    TX Family TMPM471F10FG Exception 5.6.10. System Handler Control and Status Register Bit symbol After reset Type Function 31:19 Read as "0". Usage Fault USGFAULTENA 0: Disabled 1: Enabled Bus Fault BUSFAULTENA 0: Disabled 1: Enabled Memory Management MEMFAULTENA 0: Disabled 1: Enabled SVCall SVCALLPENDED...

  • Page 65: Revision History

    TX Family TMPM471F10FG Exception 6. Revision History Table 6.1 Revision History Revision Date Description 2024-08-30 - First release 65 / 66 2024-08-30 Rev. 1.0...

  • Page 66: Restrictions On Product Use

    Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.

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