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Related Manuals for Toshiba TXZ+ TMPM4G Series
Summary of Contents for Toshiba TXZ+ TMPM4G Series
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Page 1: Tmpm4G Group
TMPM4G Group (1) Clock Control and Operation Mode 32-bit RISC microcontroller TXZ+ Family TMPM4G Group (1) Reference Manual Clock Control and Operation Mode (CG-M4G(1)-C) Revision 1.4 2024-05 2024-05-31 © 2020-2024 1 / 93 Toshiba Electronic Devices & Storage Corporation Rev. 1.4... -
Page 2: Table Of Contents
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Contents Preface ................................. 7 Related Document ..............................7 Conventions ................................8 Terms and Abbreviations ............................10 Clock Control and Operation Mode ......................11 1.1. Outlines ................................11 1.2. Clock Control ..............................11 1.2.1. - Page 3 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.4.3. NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition ..............38 1.4. Registers ................................39 1.4.1. List of Registers ................................39 1.4.1.1. Clock Control and Operation Mode ..........................39 1.4.1.2.
- Page 4 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Reset and Power Control ..........................77 3.1. Outlines ................................77 3.2. Function and Operation ........................... 78 3.2.1. Cold Reset .................................. 78 3.2.1.1. Reset by Power-on Reset Circuit (without Using RESET_N Pin) .................. 79 3.2.1.2.
- Page 5 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode List of Figure Figure 1.1 Clock System Diagram ......................13 Figure 1.2 Change State Transition ......................30 Figure 1.3 STOP2 Mode Restart Operation Flow ..................36 Figure 1.4 NORMAL → STOP1 → NORMAL Operation Mode Transition ..........37 Figure 1.5 NORMAL →...
- Page 6 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode List of Tables Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> Setup ..............16 Table 1.2 PLL Correction Value (example) ....................17 Table 1.3 PLL0SET Setting Value (example) ..................17 Table 1.4 Clock Domains of CPU and Peripherals .................. 20 Table 1.5 Time Interval for Changing System Clock ................
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Page 7: Preface
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Preface Related Document Document name ® ® Cortex -M4 Processor Technical Reference Manual Datasheet product (electrical characteristics) Exception Voltage Detection Circuit Flash Memory 2024-05-31 7 / 93 Rev. 1.4... -
Page 8: Conventions
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 - It is possible to omit the "0b"... - Page 9 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.
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Page 10: Terms And Abbreviations
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Terms and Abbreviations Some of abbreviations used in this document are as follows: Analog to Digital Converter Advanced Peripheral Bus A-PMD Advanced Programmable Motor Control Circuit Consumer Electronics Control Clock Control and Operation Mode Digital to Analog Converter Digital Noise Filter ELOSC... -
Page 11: Clock Control And Operation Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1. Clock Control and Operation Mode 1.1. Outlines The clock/mode control block can select a clock gear and prescaler clock and set the warming-up of oscillator and so on. Furthermore, it has NORMAL mode and a low-power consumption mode to reduce power consumption using mode transition. -
Page 12: Initial Value By Reset Operation
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.2. Initial Value by Reset Operation A clock setup is initialized to the following states by a reset action. External high-speed oscillator: Stop Internal high-speed oscillator 1: Oscillation Internal high-speed oscillator 2: Stop (Note) External low-speed oscillator: Stop... -
Page 13: Clock System Diagram
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.3. Clock System Diagram The figure below shows a clock system diagram. [CGSPCLKEN] <ADCKEN> ADCLK Source clock control [CGWUPHCR]<WUON> [CGWUPHCR]<WUPT[15:4]> High-speed warming-up timer [CGFCEN] fsysh [CGWUPHCR] <FCIPENx> (Middle-speed system clock) <WUCLK>... -
Page 14: Warming-Up Function
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.4. Warming-up Function A warming-up function is used to secure the oscillation stable time at the time of the STOP1 mode release which starts the warming-up timer for high-speed oscillation automatically. It is available also as a count up timer which uses the exclusive warming-up timer of high-speed clock /each low-speed clock for the waiting for the stability of an external oscillator or an internal oscillator. -
Page 15: Warming-Up Timer For Low-Speed Oscillation
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.4.2. Warming-up Timer for Low-speed Oscillation A 19-bit up-timer is built in as a warming-up timer only for a low-speed oscillation. The setting value is calculated in the following formula, set [CGWUPLCR]<WUPT[18:4]> to the upper 15 bits of the setting value. Lower 4 bits are ignored. -
Page 16: Clock Multiplying Circuit (Pll) For Fsys
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.5. Clock Multiplying Circuit (PLL) for fsys The clock multiplying circuit outputs the f clock (up to 200MHz) multiplied by the optimum condition for the frequency (8 MHz to 24 MHz) of the output clock f of the high-speed oscillator. -
Page 17: Table 1.2 Pll Correction Value (Example)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode is denoted by the following formulas. = fosc × ([CGPLL0SEL]<PLL0SET[7:0]> + [CGPLL0SEL]<PLL0SET[11:8]>) × ([CGPLL0SEL]<PLL0SET[13:12]>) Note1: Frequency accuracy is not guaranteed. Note2: There is no Linearity in the frequency by the fractional part of multiplication setting. ≤... -
Page 18: Change Of Pll Multiplication Value Under Operation
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.5.3. Change of PLL Multiplication Value under Operation It changes to a setup which sets "0" to [CGPLL0SEL]<PLL0SEL> first, and does not use a PLL multiplication clock during PLL multiplication clock operation when changing a multiplication value. And [CGPLL0SEL] <PLL0ST>... -
Page 19: Pll Operation Start/Stop/Switching Procedure
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.5.4. PLL Operation Start/stop/switching Procedure (1) fc setup (PLL stop → PLL start) As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as follows. -
Page 20: System Clock
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.6. System Clock An internal high-speed oscillation clock or external high-speed oscillation clock (connected oscillator or clock input) can be used as a source of system clock. The system clock consists of "high-speed system clock (fsysh) (up to 200MHz)" for high-speed operation and "middle-speed system clock (fsysm) (up to 100MHz)"... -
Page 21: Table 1.6 Example Of Operating Frequency
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Table 1.6 shows the example of operating frequency by the clock gear ratio (1/1 to 1/16) to the frequency fc set up with oscillation frequency, a PLL multiplication value, etc. Table 1.6 Example of Operating Frequency Operating frequency by clock Operating frequency by clock... -
Page 22: Setting Method Of System Clock
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.6.1. Setting Method of System Clock (1) fosc setup (internal oscillation → external oscillation) As a fosc setup, the example of switching procedure to the external high-speed oscillator (EHOSC) from an internal high-speed oscillator 1 (IHOSC1) is shown below. - Page 23 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode (3) fosc setup (external oscillation/external clock input → internal oscillation) As a fosc setup, the example of switching procedure to the internal high-speed oscillator 1 (IHOSC1) from an external high-speed oscillator (EHOSC) or an external clock input (EHCLKIN) is shown below. <<State before switching>>...
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Page 24: Low-Speed Clock
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.7. Low-speed Clock (1) ELOSC setup (not used low-speed clock → external low-speed oscillator used) An example of setting procedure is shown as follows to use the external low-speed oscillator (ELOSC). <<State before switching>>... -
Page 25: Clock Supply Setting Function
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.2.8. Clock Supply Setting Function TMPM4G Group (1) has the clock on/off function for the peripheral circuits. To reduce the power consumption, TMPM4G Group (1) can stop supplying the clock to the peripheral functions that are not used. Except some peripheral functions, clocks are not supplied after reset. -
Page 26: Operation Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3. Operation Mode There are NORMAL mode and a low-power consumption mode (IDLE, STOP1, and STOP2) in TMPM4G Group (1) as an operation mode, and it can reduce power consumption by performing mode transition according to directions for use. -
Page 27: Transition To And Return From Low-Power Consumption Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode This product will be cut off the power except for the following circuit in STOP2 mode. ● External low-speed oscillator (ELOSC) ● ● Backup RAM ● Port pin status ● ●... -
Page 28: Peripheral Function State In Low-Power Consumption Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.1.4. Peripheral Function State in Low-power Consumption Mode The following Table 1.10 shows the operation state of the peripheral function (block) in each low-power consumption mode. In addition, after reset release, it will be in the state where a clock is not supplied except for some blocks. If needed, set up [CGFSYSENA], [CGFSYSMENA], [CGFSYSMENB], [CGFSYSMENC], [CGFCEN], [CGSPCLKEN] and enable clock supply. - Page 29 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Note4: This peripheral circuit can operate by using LTTMR as a sampling clock. Note5: This peripheral circuit can operate when [RLMLOSCCR]<POSCEN> is set to "1". Note6: It becomes a data hold when peripheral functions (DMA etc.) which carry out data access (R/W), except CPU, are not connected on the bus matrix.
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Page 30: Mode State Transition
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.2. Mode State Transition STOP2 mode Reset release reset After release reset, internal high-speed oscillator Interrupt 1 (IHOSC1) starts oscillation. (Note2) Interrupt (Note2) STOP2 mode STOP1 mode (CPU and main power NORMAL mode (CPU and peripherals domain stop and internal... -
Page 31: Stop1 Mode Transition Flow
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.2.2. STOP1 Mode Transition Flow Set up the following procedure at transition to STOP1 mode. Because STOP1 mode is released by an interrupt, set the interrupt before transition to STOP1 mode. For the interrupts that can be used to release the STOP1 mode, refer to "1.3.3.1. -
Page 32: Stop2 Mode Transition Flow
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.2.3. STOP2 Mode Transition Flow Set up the following procedure at transition to STOP2 mode. Because STOP2 mode is released by an interrupt, set the interrupt before transition to STOP2 mode. For the interrupts that can be used to release the STOP2 mode, refer to "1.3.3.1. -
Page 33: Return Operation From Low-Power Consumption Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.3. Return Operation from Low-power Consumption Mode 1.3.3.1. Release Source of Low-power Consumption Mode Interrupt, Non-Maskable Interrupt, and reset can perform release from a low-power consumption mode. The low-power consumption mode release source which can be used is decided by a low-power consumption mode. It shows the following table about details. - Page 34 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode ● Released by an interrupt request When interrupt releases a low-power consumption mode, it is necessary to prepare so that interrupt may be detected by CPU. The interrupt used for release in STOP1 and STOP2 modes needs to set for detecting the interrupt by INTIF other than a setting of CPU.
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Page 35: Warming Up At Release Of Low-Power Consumption Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.3.2. Warming Up at Release of Low-power Consumption Mode Warming up may be required because of stability of an internal oscillator at the time of mode transition. When the transition from STOP1 mode to NORMAL mode is done, an internal oscillator 1 (IHOSC1) is selected automatically and the warming-up timer is started. -
Page 36: Restart Operation From Stop2 Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.3.3. Restart Operation from STOP2 Mode The restart operation flow from STOP2 mode release factor interrupt generating is as follows. Generate release factor Check reset flag (Note1) • [RLMRSTFLGx] = xx (it is checked by which factor reset has occured.) STOP2 release interrupt RESET_N pin or LVD reset... -
Page 37: Clock Operation By Mode Transition
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.4. Clock Operation by Mode Transition The clock operation in case of mode transition is shown below. 1.3.4.1. NORMAL → IDLE → NORMAL Operation Mode Transition CPU stops at IDLE mode. The clock supply to a peripheral function holds a setting state. Please perform operation/stop by the register of each peripheral function, a clock supply setting function, etc. -
Page 38: Normal → Stop2 → Reset → Normal Operation Mode Transition
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.3.4.3. NORMAL → STOP2 → RESET → NORMAL Operation Mode Transition Warming up is not performed when returning to NORMAL mode. Even when returning to NORMAL mode by no reset, the CPU branches to the interrupt routine of reset. A reset operation is performed to an internal main power domain after STOP2 mode released. -
Page 39: Registers
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4. Registers 1.4.1. List of Registers The register related to CG and its address information are shown below. Peripheral function Channel/unit Base address Clock Control and Operation 0x40083000 Mode Low-speed oscillation/ power 0x4003E400 control 1.4.1.1. -
Page 40: Details Of Register
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2. Details of Register 1.4.2.1. [CGPROTECT] (CG Write Protection Register) Bit symbol After reset Type Function 31:8 Read as "0". Control write protection for the CG registers (all registers except this register). -
Page 41: Cgsyscr] (System Clock Control Register)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.3. [CGSYSCR] (System Clock Control Register) Bit symbol After reset Type Function Middle-speed prescaler clock (ΦT0m) selection status 00: <PRCK[3:0]> setting value (no division) 31:30 MCKSELPST[1:0] 01: <PRCK[3:0]> setting value is divided by 2 Others: <PRCK[3:0]>... -
Page 42: Cgstbycr] (Standby Control Register)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.4. [CGSTBYCR] (Standby Control Register) Bit symbol After reset Type Function 31:2 Read as "0". Select a low-power consumption mode. 00: IDLE STBY[1:0] 01: STOP1 10: STOP2 11: Reserved 1.4.2.5. [CGPLL0SEL] (PLL Selection Register for fsys) Bit symbol After reset Type... -
Page 43: Cgwuphcr] (High-Speed Oscillation Warming-Up Register)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.6. [CGWUPHCR] (High-speed Oscillation Warming-up Register) Bit symbol After reset Type Function Set the upper 12 bits of the 16 bits of calculation values of the warming-up timer. 31:20 WUPT[15:4] 0x800 About a setup of a warming-up timer, refer to "1.2.4.1. -
Page 44: Cgfsysmenc] (Middle-Speed Clock Supply And Stop Register C For Fsysm)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.8. [CGFSYSMENC] (Middle-speed Clock Supply and Stop Register C for fsysm) Bit symbol After reset Type Function 31:17 Read as "0". Clock enable of T32A ch15 IPMENC16 0: Clock stop 1: Clock supply Clock enable of T32A ch14 IPMENC15... -
Page 45: Cgfsysmena] (Middle-Speed Clock Supply And Stop Register A For Fsysm)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.9. [CGFSYSMENA] (Middle-speed Clock Supply and Stop Register A for fsysm) Bit symbol After reset Type Function Clock enable of I2C ch2 IPMENA31 0: Clock stop 1: Clock supply Clock enable of I2C ch1 IPMENA30 0: Clock stop 1: Clock supply... - Page 46 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Bit symbol After reset Type Function Clock enable of T32A ch05 IPMENA11 0: Clock stop 1: Clock supply Clock enable of T32A ch04 IPMENA10 0: Clock stop 1: Clock supply Clock enable of T32A ch03 IPMENA09 0: Clock stop...
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Page 47: Cgfsysmenb] (Middle-Speed Clock Supply And Stop Register B For Fsysm)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.10. [CGFSYSMENB] (Middle-speed Clock Supply and Stop Register B for fsysm) Bit symbol After reset Type Function Clock enable of SIWDT IPMENB31 0: Clock stop 1: Clock supply Clock enable of NBDIF IPMENB30 0: Clock stop 1: Clock supply... - Page 48 TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode Bit symbol After reset Type Function Clock enable of PORT G IPMENB08 0: Clock stop 1: Clock supply Clock enable of PORT F IPMENB07 0: Clock stop 1: Clock supply Clock enable of PORT E IPMENB06 0: Clock stop...
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Page 49: Cgfsysena] (High-Speed Clock Supply And Stop Register A For Fsysh)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.11. [CGFSYSENA] (High-speed Clock Supply and Stop Register A for fsysh) Bit symbol After reset Type Function 31:10 Read as "0". Clock enable of TSPI ch5 IPENA09 0: Clock stop 1: Clock supply Clock enable of TSPI ch4 IPENA08... -
Page 50: Cgfcen] (Clock Supply And Stop Register For Fc)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.12. [CGFCEN] (Clock Supply and Stop Register for fc) Bit symbol After reset Type Function 31:28 Read as "0" Clock enable of DNF unit B FCIPEN27 0: Clock stop 1: Clock supply Clock enable of DNF unit A FCIPEN26 0: Clock stop... -
Page 51: Cgextend2] (Function Extension Register 2)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.14. [CGEXTEND2] (Function Extension Register 2) Bit symbol After reset Type Function 31:3 Read as "0". MDMAC software reset It is generated with the continuous writes of "0", "1" and "0" in order. -
Page 52: Rlmshtdnop] (Power Supply Cut Off Control Register)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.4.2.16. [RLMSHTDNOP] (Power Supply Cut Off Control Register) Bit symbol After reset Type Function Write "0". Read as "0". The I/O control signal in the STOP2 mode is held. 0: Control by Port. 1: Hold the state when it changes into "1"... -
Page 53: Information For Each Product
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.5. Information for Each Product The information about [CGFSYSENA], [CGFSYSMENA], [CGFSYSMENB], [CGFSYSMENC] and [CGFCEN] which are different according to each product is shown below. 1.5.1. [CGFSYSENA] Table 1.13 Allocation of [CGFSYSENA] by Each Product Channel number/ Bit symbol Destination... -
Page 54: Cgfsysmena]
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.5.2. [CGFSYSMENA] Table 1.14 Allocation of [CGFSYSMENA] by Each Product Channel number/ Bit symbol Destination unit name/ M4GR M4GQ M4GN port name ✓ ✓ ✓ IPMENA31 ✓ ✓ ✓ IPMENA30 ✓... -
Page 55: Cgfsysenb]
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.5.3. [CGFSYSENB] Table 1.15 Allocation of [CGFSYSMENB] by Each Product Channel number/ Bit symbol Destination unit name/ M4GR M4GQ M4GN port name ✓ ✓ ✓ IPMENB31 SIWDT ✓ ✓ ✓ IPMENB30 NBDIF IPMENB29... -
Page 56: Cgfsysenc]
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.5.4. [CGFSYSENC] Table 1.16 Allocation of [CGFSYSMENC] by Each Product Channel number/ Bit symbol Destination unit name/ M4GR M4GQ M4GN port name IPMENC31 IPMENC30 IPMENC29 IPMENC28 IPMENC27 IPMENC26 IPMENC25 IPMENC24 IPMENC23 IPMENC22 IPMENC21... -
Page 57: Cgfcen]
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 1.5.5. [CGFCEN] Table 1.17 Allocation of [CGFCEN] by Each Product Channel number/ Bit symbol Destination unit name/ M4GR M4GQ M4GN port name FCIPEN31 FCIPEN30 FCIPEN29 FCIPEN28 ✓ ✓ ✓ FCIPEN27 ✓... -
Page 58: Memory Map
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2. Memory Map 2.1. Outline The memory maps for TMPM4G Group (1) are based on the Cortex-M4 (with FPU) processor core memory map. The internal ROM, internal RAM, and special function registers (SFR) of TMPM4G Group (1) are mapped to the Code, SRAM, and peripheral regions of the Cortex-M4 (with FPU) respectively. -
Page 59: Tmpm4Gxf20
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.1.1. TMPM4GxF20 ● Code Flash: 2048KB ● RAM: 256KB+2KB (Backup RAM) ● Data Flash: 32KB ● Target products: TMPM4GRF20FG, TMPM4GRF20XBG, TMPM4GQF20FG, TMPM4GQF20XBG, TMPM4GNF20FG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000... -
Page 60: Tmpm4Gxf15
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.1.2. TMPM4GxF15 ● Code Flash: 1536KB ● RAM: 256KB+2KB (Backup RAM) ● Data Flash: 32KB ● Target products: TMPM4GRF15FG, TMPM4GRF15XBG, TMPM4GQF15FG, TMPM4GQF15XBG, TMPM4GNF15FG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000... -
Page 61: Tmpm4Gxf10
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.1.3. TMPM4GxF10 ● Code Flash: 1024KB ● RAM: 256KB+2KB (Backup RAM) ● Data Flash: 32KB ● Target products: TMPM4GRF10FG, TMPM4GRF10XBG, TMPM4GQF10FG, TMPM4GQF10XBG, TMPM4GNF10FG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000... -
Page 62: Tmpm4Gxfd
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.1.4. TMPM4GxFD ● Code Flash: 512KB ● RAM: 192KB+2KB (Backup RAM) ● Data Flash: 32KB ● Target products: MPM4GRFDFG, TMPM4GRFDXBG, TMPM4GQFDFG, TMPM4GQFDXBG, TMPM4GNFDFG 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 CPU Register Region CPU Register Region 0xE0000000 0xE0000000... -
Page 63: Bus Matrix
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.2. Bus Matrix TMPM4G Group (1) have the main masters consisted of the CPU core and high-speed DMA controllers (HDMAC) and sub master consisted of a multi-function DMA controller (MDMAC) and NBDIF. The main masters are connected to the slave ports (S1 to S5) of the bus matrix. -
Page 64: Configuration
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.2.1. Configuration 2.2.1.1. Single Chip Mode High speed clock domain NBDIF Middle speed clock domain Cortex-M4 HDMAC HDMAC UnitA UnitB with FPU SyncUp Instruction Code Flash Data System Data Flash BootROM RAM0 TSPI(SFR) -
Page 65: Single Boot Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.2.1.2. Single Boot Mode High speed clock domain Middle speed clock domain NBDIF Cortex-M4 HDMAC HDMAC UnitA UnitB with FPU SyncUp Instruction Data Code Flash System Data Flash BootROM RAM0 TSPI(SFR) RAM1 EBIF(SFR) -
Page 66: Connection Table
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.2.2. Connection Table 2.2.2.1. Code Area/SRAM Area/SMIF Area/External Bus Area (1) TMPM4GxF20 ● Single chip mode Table 2.1 TMPM4GxF20 Single Chip Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start address... -
Page 67: Table 2.2 Tmpm4Gxf20 Single Boot Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode ● Single Boot mode Table 2.2 TMPM4GxF20 Single Boot Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus... -
Page 68: Table 2.3 Tmpm4Gxf15 Single Chip Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode (2) TMPM4GxF15 ● Single chip mode Table 2.3 TMPM4GxF15 Single Chip Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start address Slave NBDIF unit A unit A unit B S-Bus D-Bus... -
Page 69: Table 2.4 Tmpm4Gxf15 Single Boot Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode ● Single Boot mode Table 2.4 TMPM4GxF15 Single Boot Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start Address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus... -
Page 70: Table 2.5 Tmpm4Gxf10 Single Chip Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode (3) TMPM4GxF10 ● Single chip mode Table 2.5 TMPM4GxF10 Single Chip Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start address Slave NBDIF unit A unit A unit B S-Bus D-Bus... -
Page 71: Table 2.6 Tmpm4Gxf10 Single Boot Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode ● Single Boot mode Table 2.6 TMPM4GxF10 Single Boot Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus... -
Page 72: Table 2.7 Tmpm4Gxfd Single Chip Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode (4) TMPM4GxFD ● Single chip mode Table 2.7 TMPM4GxFD Single Chip Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start address Slave NBDIF unit A unit A unit B S-Bus D-Bus... -
Page 73: Table 2.8 Tmpm4Gxfd Single Boot Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode ● Single Boot mode Table 2.8 TMPM4GxFD Single Boot Mode Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start Address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus... -
Page 74: Peripheral Area
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.2.2.2. Peripheral Area Table 2.9 Peripheral Area Sub master Main master MDMAC HDMAC HDMAC Core Core Core Start address Slave NBDIF unit A unit A unit B S-Bus D-Bus I-Bus ✓... -
Page 75: Ram Access
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.2.3. RAM Access The number of clocks required to access the internal RAM is shown in the table below. Table 2.10 Number of Clocks to Access Each RAM fsys No. of clocks Description RAM0 fsysh... -
Page 76: Details Of Register
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 2.2.3.2. Details of Register (1) [FCKCR] (Flash Key Code Register) Bit symbol After reset Type Function Locked register release key code When [FCRACCR] is rewritten, write the specific code (0xA74A9D23) to this register. And then rewrite the value of the 31:0 KEYCODE 0x00000000... -
Page 77: Reset And Power Control
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3. Reset and Power Control 3.1. Outlines This section describes how to turn on a power supply, and how to assert and deassert a power-on reset and reset. Function classification Factor Functional description Reset which occurs at the time of turning on or off a... -
Page 78: Function And Operation
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2. Function and Operation This section explains about power-on, power off and reset. Note: Refer to "Electrical Characteristics" of a datasheet for the time and voltage of description of the symbol in a figure. -
Page 79: Reset By Power-On Reset Circuit (Without Using Reset_N Pin)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.1.1. Reset by Power-on Reset Circuit (without Using RESET_N Pin) After a supply voltage exceeds the release voltage of a power-on reset (POR), internal reset is deasserted after "Internal initialization time" is elapsed. Please increase a supply voltage goes up into an operating voltage range before "Internal initialization time"... -
Page 80: Reset By Reset_N Pin
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.1.2. Reset by RESET_N Pin When turn on a power supply, it can control the timing of reset release by using RESET_N pin. After a supply voltage exceeds the release voltage of a power-on reset and even after "Internal initialization time" elapsed, if the RESET_N pin is "Low", internal reset continues. -
Page 81: Figure 3.3 Reset Operation By Reset_N Pin (2)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode In case of RESET_N pin input change from "Low" level to "High" level before "Internal initialization time" elapses, internal reset signal is released after "Internal initialization time" elapses. Please goes up a supply voltage into an operating voltage range before "Internal initialization time" elapses. The CPU operates after internal reset release. -
Page 82: Continuation Of Reset By Lvd
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.1.3. Continuation of Reset by LVD When the power supply voltage has not exceeded the LVD release voltage even after "Internal initialization time" elapsed, LVD generates the reset signal, and the reset state continues. After the power supply voltage exceeds the LVD release voltage and "LVD detection release time"... -
Page 83: Warm Reset
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.2. Warm Reset 3.2.2.1. Warm Reset by REST_N Pin When resetting with the RESET_N pin, set the RESET_N pin to "Low" level for 17.2 μs or more while the power supply voltage is within the operating range. -
Page 84: Reset By Stop2 Mode Release
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.3. Reset by STOP2 Mode Release When RESET_N pin changed "Low" level or LVD reset occurred during STOP2 mode, STOP2 released. The power supply is turned on and assert reset to main power domain. After RESET_N pin changes to "High" level or LVD reset released, start operating in NORMAL mode. -
Page 85: Starting Single Boot Mode
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.4. Starting Single Boot Mode For the details of the single mode, refer to the reference manual "Flash memory". 3.2.4.1. Starting Single Boot Mode by RESET_N pin When "Low" level is input to a Boot_N pin, and then reset release, "single Boot mode" will be started. When turn on power supply, the time of input "Low"... -
Page 86: Starting Single Boot Mode By Power-On Reset (Not Using Reset_N Pin)
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.4.2. Starting Single Boot Mode by Power-on Reset (Not Using RESET_N Pin) When and turning on power supply, "Low" level is input to Boot_N pin. After the internal reset is deasserted, the CPU operation starts, and the single Boot mode starts up. -
Page 87: Starting Single Boot Mode When Power Supply Is Stable
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.4.3. Starting Single Boot Mode when Power Supply is Stable When the supply voltage is stable within an operating voltage range, input "Low" level to RESET_N pin for reset equal to or longer than "Internal processing time", while "Low" level is input to the Boot_N pin. DVDD3= DVDD3A= DVDD3B= DVDD3C= DVDD3D= DVDD3E= DVDD3F= DVDD3G= DVDD3H= AVDD3 DVDD3 Operating voltage range... -
Page 88: Power-On Reset Circuit
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.5. Power-on Reset Circuit The power-on reset circuit (POR) generates a reset signal when the power is turned on or turned off. Note: The power-on reset circuit may not operate correctly due to the fluctuation of the power supply. Equipment should be designed with full consideration of the electrical characteristics. -
Page 89: Precautions When Turning Off Power
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.6. Precautions when Turning Off Power When turning off the power, always follow the prescribed procedure to reduce the power supply voltage. DVDD3= DVDD3A= DVDD3B= DVDD3C= DVDD3D= DVDD3E= DVDD3F= DVDD3G= DVDD3H= AVDD3 Power off falling gradient Operation voltage POFF... -
Page 90: About Turn On Power Supply After Turn Off
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.7. About Turn On Power Supply after Turn Off 3.2.7.1. When Using External Reset Circuit or Internal LVD Reset Output When the power supply is turned off and the power supply voltage drops below the operation guaranteed voltage, reset is performed with an external reset circuit or built-in LVD (when the voltage is less than the set voltage). -
Page 91: Reset Factor And Reset Range
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 3.2.8.1. Reset Factor and Reset Range Reset factors and the range initialized are shown in Table 3.1. Table 3.1 Reset Factor and Range Initialized Reset factors STOP2 mode release Cold Reset Warm reset (Note1) Registers and Reset... -
Page 92: Revision History
TXZ+ Family TMPM4G Group (1) Clock Control and Operation Mode 4. Revision History Table 4.1 Revision History Revision Date Description 2020-12-14 First release - Correct Figure 1.3. - 1.3.3.3. The restart operation from the STOP2 mode Change Note2 to Note3, and Note3 is corrected. Added Note2. -
Page 93: Restrictions On Product Use
Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.
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