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Related Manuals for Toshiba TX TMPM471F10FG
Summary of Contents for Toshiba TX TMPM471F10FG
- Page 1 TX Family TMPM471F10FG Clock Control and Operation Mode 32-bit RISC Microcontroller TX Family TMPM471F10FG Reference Manual Clock Control and Operation Mode (CG-TMPM471F10FG) Revision 1.0 2024-08 © 2024 1 / 58 2024-08-30 Toshiba Electronic Devices & Storage Corporation Rev. 1.0...
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Page 2: Table Of Contents
TX Family TMPM471F10FG Clock Control and Operation Mode Contents Preface ................................. 6 Related Documents ..............................6 Conventions ................................7 Terms and Abbreviations ............................9 Clock Control and Operation Mode ......................10 1.1. Outlines ................................10 1.2. Clock Control ..............................11 1.2.1. - Page 3 TX Family TMPM471F10FG Clock Control and Operation Mode 1.4.2. Detail of Register ................................ 31 1.4.2.1. [CGPROTECT] (CG Write Protection Register) ......................31 1.4.2.2. [CGOSCCR] (Oscillation Control Register)........................31 1.4.2.3. [CGSYSCR] (System Clock Control Register) ....................... 32 1.4.2.4. [CGSTBYCR] (Standby Control Register) ........................33 1.4.2.5.
- Page 4 TX Family TMPM471F10FG Clock Control and Operation Mode RESTRICTIONS ON PRODUCT USE ....................... 58 4 / 58 2024-08-30 Rev. 1.0...
- Page 5 TX Family TMPM471F10FG Clock Control and Operation Mode List of Figures Figure 1.1 Clock System Diagram ......................12 Figure 1.2 Mode State Transition ......................25 Figure 1.3 NORMAL >>> STOP1 >>> NORMAL Operation Mode Transition ........29 Figure 2.1 TMPM471F10FG ........................40 Figure 2.2 Single Chip Mode ........................
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Page 6: Preface
TX Family TMPM471F10FG Clock Control and Operation Mode Preface Related Documents Document name ® ® documentation set for the Arm Cortex Exception Oscillation frequency detector Voltage detection circuit Clock selective watchdog timer Flash memory Datasheet 6 / 58 2024-08-30 Rev. 1.0... -
Page 7: Conventions
TX Family TMPM471F10FG Clock Control and Operation Mode Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC Decimal: 123 or 0d123 - Only when it needs to be explicitly shown that they are decimal numbers. Binary: 0b111 - It is possible to omit the "0b"... - Page 8 TX Family TMPM471F10FG Clock Control and Operation Mode *********************************************************************************************************************** Arm, Cortex and Thumb are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. All rights reserved. *********************************************************************************************************************** All other company names, product names, and service names mentioned herein may be trademarks of their respective companies.
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Page 9: Terms And Abbreviations
TX Family TMPM471F10FG Clock Control and Operation Mode Terms and Abbreviations Some of abbreviations used in this document are as follows: Analog to digital converter A-ENC32 Advanced encoder input circuit (32-bit) A-PMD Advanced programmable motor control circuit Clock control and operation mode Cyclic redundancy check D-Bus DCode memory interface... -
Page 10: Clock Control And Operation Mode
TX Family TMPM471F10FG Clock Control and Operation Mode 1. Clock Control and Operation Mode 1.1. Outlines The clock/mode control block can select a clock gear and prescaler clock, and set the warming-up of oscillator and so on. Furthermore, it has Normal mode and a low-power consumption mode in order to reduce power consumption using mode transition. -
Page 11: Clock Control
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2. Clock Control 1.2.1. Clock Type This section shows a list of clocks: EHCLKIN : The high-speed clock input from the external fosc : A clock generated in the internal oscillation circuit or input from the X1 and X2 pins after being selected by [CGOSCCR]<OSCSEL>. -
Page 12: Clock System Diagram
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2.3. Clock System Diagram The figure below shows a clock system diagram. [CGWUPHCR]<WUON> [CGWUPHCR]<WUPT[15:4]> High-speed ADCLK warming-up timer [CGWUPHCR] [CGSPCLKEN] <WUCLK> <ADCKEN[1:0]> [CGOSCCR]<IHOSC1EN> Peripheral function using fc After reset：oscillation [CGPLL0SEL] DNF, OFD (Target clock) <PLL0ON>... -
Page 13: Warming-Up Function
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2.4. Warming-up Function A warming-up function starts the warming-up timer for high-speed oscillator automatically to secure the oscillation stable time when the STOP1 mode is released. It is also available as a count-up timer which uses the warming-up timer for high-speed oscillator to secure the stability of an external oscillator or an internal oscillator. -
Page 14: The Directions For Warming-Up Timer
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2.4.2. The Directions for Warming-up Timer The directions for a warming-up function are explained. (1) Selection of a clock In a high-speed oscillation, the clock classification (internal oscillation/external oscillation) counted with a warming-up timer is selected by [CGWUPHCR]<WUCLK>. -
Page 15: The Formula And Example Of Setting Of Pll Multiplication Value
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2.5.2. The Formula and Example of Setting of PLL Multiplication Value The details of the items of [CGPLL0SEL]<PLL0SET[23:0]> which set up a PLL multiplication value are shown below. Table 1.1 Details of [CGPLL0SEL]<PLL0SET[23:0]> Setup Items of PLL0SET Function Correction... -
Page 16: Change Of Pll Multiplication Value Under Operation
TX Family TMPM471F10FG Clock Control and Operation Mode The main examples of a setting of [CGPLL0SEL]<PLL0SET[23:0]> are shown below. It multiplies by PLL, and dividing is carried out and the target Clock frequency (f ) is generated for input frequency (fosc). A dividing value is chosen from 1/2, 1/4, and 1/8. -
Page 17: Pll Operation Start/Stop/Switching Procedure
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2.5.4. PLL Operation Start/Stop/Switching Procedure (1) fc setup (PLL stop >>> PLL start) As an fc setup, the example of switching procedure from the PLL stop state to the PLL operation state is as follows. -
Page 18: System Clock
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2.6. System Clock An internal high-speed oscillation clock or external high-speed oscillation clock (connected oscillator or clock input) can be used as a source of system clock. The system clock consists of "High-speed system clock (fsysh) (maximum 160MHz)" for high-speed operation and "Middle-speed system clock (fsysm) (maximum 80MHz)"... -
Page 19: Setting Method Of System Clock
TX Family TMPM471F10FG Clock Control and Operation Mode Table 1.8 Example of Operating Frequency (fc = 120MHz) Operating frequency (MHz) Operating frequency (MHz) External Built-in External multiplication Maximum by clock gear ratio by clock gear ratio clock oscillation oscillation value frequency PLL = ON PLL = OFF... -
Page 20: Fosc Setup (Internal Oscillation >>> External Clock Input)
TX Family TMPM471F10FG Clock Control and Operation Mode (2) fosc setup (Internal oscillation >>> External clock input) As a fosc setup, the example of switching procedure to the external clock input (EHCLKIN) from an internal oscillator1 (IHOSC1) is shown below. <<... -
Page 21: Clock Supply Setting Function
TX Family TMPM471F10FG Clock Control and Operation Mode 1.2.7. Clock Supply Setting Function This MCU has the clock supply on/off function for the peripheral circuits. To reduce the power consumption, this MCU can stop supplying the clock to the peripheral functions that are not used. Except some peripheral functions, clocks are not supplied after reset. -
Page 22: Operation Mode
TX Family TMPM471F10FG Clock Control and Operation Mode 1.3. Operation Mode There are NORMAL mode and a low-power consumption mode (IDLE, STOP1) in this product as an Operation mode, and it can reduce power consumption by performing mode changes according to directions for use. 1.3.1. -
Page 23: Transition To And Return From Low-Power Consumption Mode
TX Family TMPM471F10FG Clock Control and Operation Mode 1.3.1.2. Transition to and Return from Low-power Consumption Mode In order to shift to each low-power consumption mode, the IDLE/STOP1 mode is chosen by standby control register [CGSTBYCR]<STBY[1:0]>, and a WFI (Wait For Interrupt) command is executed. When the transition to the low-power consumption mode has been done by WFI instruction, the return from the mode can be done by the reset or an interrupt generation. -
Page 24: Peripheral Function State In Low-Power Consumption Mode
TX Family TMPM471F10FG Clock Control and Operation Mode 1.3.1.4. Peripheral Function State in Low-power Consumption Mode The following Table 1.12 shows the Operation State of the peripheral function (block) in each mode. In addition, after reset release, it will be in the state where a clock is not supplied except for some blocks. If needed, set up [CGFSYSENA], [CGFSYSMENA], [CGFSYSMENB], [CGFCEN], [CGSPCLKEN] and enable clock supply. -
Page 25: Mode State Transition
TX Family TMPM471F10FG Clock Control and Operation Mode 1.3.2. Mode State Transition Reset After reset, the high-speed oscillator1 (IHOSC1) oscillates. (Note2) Interrupt NORMAL STOP1 Mode Mode (CPU stops except some peripheral functions) Instruction (Note1) Interrupt Instruction IDLE Mode (CPU stops) (Operating peripheral function can be selected) Figure 1.2 Mode State Transition... -
Page 26: Stop1 Mode Transition Flow
TX Family TMPM471F10FG Clock Control and Operation Mode 1.3.2.2. STOP1 Mode Transition Flow Set up the following procedure at switching to STOP1. Because STOP1 mode is released by an interrupt, set the interrupt before switching to STOP1 mode. For the interrupts that can be used to release the STOP1 mode, refer to "1.3.3.1. -
Page 27: Return From Low-Power Consumption Mode
TX Family TMPM471F10FG Clock Control and Operation Mode 1.3.3. Return from Low-power Consumption Mode 1.3.3.1. Release Source of Low-power Consumption Mode Interrupt, Non-maskable interrupt, and reset can perform return from a low-power consumption mode. The standby release source which can be used is decided by a low-power consumption mode. It shows the following table about details. -
Page 28: Warming-Up At Release Of Low-Power Consumption Mode
TX Family TMPM471F10FG Clock Control and Operation Mode ● Released by an interrupt request When interrupt cancels a low-power consumption mode, it is necessary to prepare so that interrupt may be detected by CPU. The interrupt used for release in STOP1 mode needs to set up CPU, and needs to set up detection by INTIF. -
Page 29: Clock Operation By Mode Transition
TX Family TMPM471F10FG Clock Control and Operation Mode 1.3.4. Clock Operation by Mode Transition The clock operation in case of mode transition is shown below. 1.3.4.1. NORMAL >>> IDLE >>> NORMAL Operation Mode Transition CPU stops at IDLE mode. The clock supply to a peripheral function holds a setting state. Please perform operation/stop by the register of each peripheral function, a clock supply setting function, etc. -
Page 30: Explanation Of Register
TX Family TMPM471F10FG Clock Control and Operation Mode 1.4. Explanation of Register 1.4.1. Register List The register related to CG and its address information are shown below. Peripheral function Channel/Unit Base address Clock control and operation mode 0x40083000 Register name Address (Base+) CG write protection register [CGPROTECT]... -
Page 31: Detail Of Register
TX Family TMPM471F10FG Clock Control and Operation Mode 1.4.2. Detail of Register 1.4.2.1. [CGPROTECT] (CG Write Protection Register) Bit symbol After reset Type Function 31:8 Read as "0" Control write-protection for the CG register (all registers included except this register) PROTECT[7:0] 0xC1 0xC1: CG Registers are write-enabled. -
Page 32: Cgsyscr] (System Clock Control Register)
TX Family TMPM471F10FG Clock Control and Operation Mode Note3: When using the oscillator connection, set this bit to "01" (external high-speed oscillator). Note4: To wait stabilizing oscillation of an internal high-speed oscillator1 (IHOSC1), use a warming-up timer and confirm [CGWUPHCR]<WUEF> instead of <IHOSC1F>. 1.4.2.3. -
Page 33: Cgstbycr] (Standby Control Register)
TX Family TMPM471F10FG Clock Control and Operation Mode 1.4.2.4. [CGSTBYCR] (Standby Control Register) Bit symbol After reset Type Function 31:2 Read as "0" Selects a low-power consumption mode. 00: IDLE STBY[1:0] 01: STOP1 10: Reserved 11: Reserved 1.4.2.5. [CGPLL0SEL] (PLL Selection Register for fsys) Bit symbol After reset Type... -
Page 34: Cgwuphcr] (High-Speed Oscillation Warming-Up Register)
TX Family TMPM471F10FG Clock Control and Operation Mode 1.4.2.6. [CGWUPHCR] (High-speed Oscillation Warming-up Register) Bit symbol After reset Type Function Sets the upper 12 bits of the 16 bits of calculation values of the warming-up timer. 31:20 WUPT[15:4] 0x800 About a setup of a warming-up timer, refer to "1.2.4.1. The Warming-up Timer for High-speed Oscillation". - Page 35 TX Family TMPM471F10FG Clock Control and Operation Mode Bit symbol After reset Type Function Clock enable of PORT H IPMENA12 0: Clock stop 1: Clock supply Clock enable of PORT G IPMENA11 0: Clock stop 1: Clock supply Clock enable of PORT F IPMENA10 0: Clock stop 1: Clock supply...
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Page 36: Cgfsysmenb] (Supply And Stop Register B For Fsysm)
TX Family TMPM471F10FG Clock Control and Operation Mode 1.4.2.8. [CGFSYSMENB] (Supply and Stop Register B for fsysm) Bit symbol After reset Type Function Clock enable of SIWDT IPMENB31 0: Clock stop 1: Clock supply 30:29 Read as "0". IPMENB28 Write as "1". 27:16 Read as "0"... -
Page 37: Cgfsysena] (Supply And Stop Register A For Fsysh)
TX Family TMPM471F10FG Clock Control and Operation Mode Bit symbol After reset Type Function Clock enable of TSPI ch2 IPMENB02 0: Clock stop 1: Clock supply Clock enable of TSPI ch1 IPMENB01 0: Clock stop 1: Clock supply Clock enable of TSPI ch0 IPMENB00 0: Clock stop 1: Clock supply... -
Page 38: Cgfcen] (Clock Supply And Stop Register For Fc)
TX Family TMPM471F10FG Clock Control and Operation Mode 1.4.2.10. [CGFCEN] (Clock Supply and Stop Register for fc) Bit symbol After reset Type Function 31:25 Read as "0" Clock enable of DNF (INT0 to F) FCIPEN24 0: Clock stop 1: Clock supply 23:21 Read as "0"... -
Page 39: Memory Map
TX Family TMPM471F10FG Clock Control and Operation Mode 2. Memory Map 2.1. Outlines The memory map for TMPM471F10FG is based on the Arm Cortex-M4 (with FPU) processor core memory map. The internal ROM, internal RAM and special function registers (SFR) of TMPM471F10FG are mapped to the Code, SRAM and peripheral regions of the Cortex-M4 (with FPU) respectively. -
Page 40: Tmpm471F10Fg
TX Family TMPM471F10FG Clock Control and Operation Mode 2.1.1. TMPM471F10FG ● Code Flash: 1MB ● RAM: 64KB 0xFFFFFFFF 0xFFFFFFFF Vendor-Specific Vendor-Specific 0xE0100000 0xE0100000 0xE00FFFFF 0xE00FFFFF CPU Register Region CPU Register Region 0xE0000000 0xE0000000 Fault Fault 0x5E100000 0x5E100000 Code Flash Code Flash (Mirror 1MB) (1MB) 0x5E000000... -
Page 41: Bus Matrix
TX Family TMPM471F10FG Clock Control and Operation Mode 2.2. Bus Matrix The Bus Matrix of TMPM471F10FG consists of a high-speed system clock domain and a middle-speed system clock domain. In the high-speed system clock domain, a CPU core connected to the slave ports (S1 to S3) accesses peripheral functions connected to the master ports (M0 to M8) via symbols (○) or (●) indicating the connection. -
Page 42: Structure
TX Family TMPM471F10FG Clock Control and Operation Mode 2.2.1. Structure 2.2.1.1. Single Chip Mode High-speed system clock domain Cortex-M4 (with FPU） S-Bus D-Bus I-Bus Code Flash Boot ROM RAMP (ch0) RAM0 RAM1 IB (INTIF) IMN (INTIF) A-PMD A-ENC32 Clock Clock synchronous synchronous circuit... -
Page 43: Single Boot Mode
TX Family TMPM471F10FG Clock Control and Operation Mode 2.2.1.2. Single Boot Mode High-speed system clock domain Cortex-M4 (with FPU) S-Bus D-Bus I-Bus Code Flash Boot ROM RAMP (ch0) RAM0 RAM1 IB (INTIF) IMN (INTIF) A-PMD A-ENC32 Clock Clock synchronous synchronous circuit circuit Middle-speed system clock domain... -
Page 44: Connection Table
TX Family TMPM471F10FG Clock Control and Operation Mode 2.2.2. Connection Table 2.2.2.1. Connection of Memory Related (1) TMPM471F10FG ● Single chip mode Table 2.1 Single Chip Mode Main master master Core Core Core Start address Slave DMAC S-Bus D-Bus I-Bus ✓... -
Page 45: Connection Of Peripheral Function
TX Family TMPM471F10FG Clock Control and Operation Mode 2.2.2.2. Connection of Peripheral Function Table 2.3 Connection of Peripheral Function Main master master Core Core Core Start address Slave DMAC S-Bus D-Bus I-Bus ✓ 0x4003E000 IA (INTIF) Fault ✓ 0x4003E400 Fault ✓... -
Page 46: Reset And Power Supply Control
TX Family TMPM471F10FG Clock Control and Operation Mode 3. Reset and Power Supply Control 3.1. Outlines Function classification Factor Functional description Reset which occurs at the time of a power supply turning Power on reset on or turning off. LVD reset Reset which occurs below the set-up voltage Cold reset (Reset by turning on a power supply) -
Page 47: Reset By Power On Reset Circuit (Without Using Reset_N Pin)
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.1.1. Reset by Power On Reset Circuit (without Using RESET_N Pin) After a supply voltage exceeds the release voltage of a power on reset (POR), internal reset is deasserted after "Internal initialization time" is elapsed. Please increase a supply voltage goes up into an operating voltage range before "Internal initialization time"... -
Page 48: Reset By Reset_N Pin
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.1.2. Reset by RESET_N Pin When turn on a power supply, it can control the timing of reset release by using RESET_N pin. After a supply voltage exceeds the release voltage of a power on reset and even after "Internal initialization time" elapsed, if the RESET_N pin is "Low", internal reset continues. -
Page 49: Figure 3.3 Reset Operation By Reset_N Pin (2)
TX Family TMPM471F10FG Clock Control and Operation Mode In case of RESET_N pin input change from "Low" to "High" before "Internal initialization time" elapses, internal reset signal is released after "Internal initialization time" elapses. Please goes up a supply voltage into an operating voltage range before "Internal initialization time" elapses. The CPU operates after internal reset release. -
Page 50: Continuation Of Reset By Lvd
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.1.3. Continuation of Reset by LVD When the power supply voltage has not exceeded the LVD release voltage even after "Internal initialization time" elapsed, LVD generates the reset signal and the reset state continues. After the power supply voltage exceeds the LVD release voltage and "LVD detection release time"... -
Page 51: Warm Reset
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.2. Warm Reset 3.2.2.1. Warm Reset by RESET_N Pin When resetting with the RESET_N pin, set the RESET_N pin to "Low" for 17.2 µs or more while the power supply voltage is within the operating range. When the "Low"... -
Page 52: Starting In Single Boot Mode
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.3. Starting in Single Boot Mode Refer to the reference manual "Flash Memory" for details of "Single Boot Mode". 3.2.3.1. Starting by RESET_N Pin When "Low" is inputted to a BOOT_N pin, if reset is released (a RESET_N pin "Low" to "High"), "Single Boot Mode"... -
Page 53: Starting In Single Boot Mode When Power Supply Is Stable
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.3.2. Starting in Single Boot Mode when Power Supply is Stable When the supply voltage is stable within an operating voltage range, input "Low" to RESET_N pin for reset longer than "Internal processing time", while "Low" is inputted to the BOOT_N pin. And release reset (RESET_N pin to "High"). -
Page 54: Power On Reset Circuit
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.4. Power On Reset Circuit The power on reset circuit (POR) generates a reset signal when the power is turned on or turned off. Note: The power on reset circuit may not operate correctly due to the fluctuation of the power supply. Equipment should be designed with full consideration of the electrical characteristics. -
Page 55: Turning Off And Re-Turning On Power Supply
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.5. Turning Off and Re-turning on Power Supply When a power supply is turned off, a power supply voltage must be down gentler gradient than Max value of "Power gradient (V )" specified in "Electrical Characteristics". POFF 3.2.5.1. -
Page 56: Reset Factor And Reset Range
TX Family TMPM471F10FG Clock Control and Operation Mode 3.2.6.1. Reset Factor and Reset Range Reset factors and the range initialized are shown in Table 3.1. Table 3.1 Reset Factor and Range Initialized Reset factors Cold Warm reset reset Registers and peripheral function <SYS Reset... -
Page 57: Revision History
TX Family TMPM471F10FG Clock Control and Operation Mode 4. Revision History Table 4.1 Revision History Revision Date Description 2024-08-30 - First release 57 / 58 2024-08-30 Rev. 1.0... - Page 58 Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.
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