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Related Manuals for Toshiba TX TMPM471F10FG
Summary of Contents for Toshiba TX TMPM471F10FG
- Page 1 TX Family TMPM471F10FG Input/Output Ports 32-bit RISC Microcontroller TX Family TMPM471F10FG Reference Manual Input/Output Ports PORT-TMPM471F10FG Revision 1.0 2024-08 1 / 41 2024-08-30 © 2024 Toshiba Electronic Devices & Storage Corporation Rev. 1.0...
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Page 2: Table Of Contents
TX Family TMPM471F10FG Input/Output Ports Contents Preface ................................. 4 Related Document ..............................4 Conventions ................................5 Terms and Abbreviations ............................7 Outlines ................................. 8 Function ................................ 8 Clock Supply ..............................8 Signal Connection List ..........................9 Registers ..............................16 List of Register ..............................17 List of Port Functions and Settings ........................ - Page 3 TX Family TMPM471F10FG Input/Output Ports List of Figures Figure 5.1 Port Type FTU1a ........................32 Figure 5.2 Port Type FTU2a ........................33 Figure 5.3 Port Type FTU3a ........................34 Figure 5.4 Port Type FTU4a ........................35 Figure 5.5 Port Type FTU5a ........................36 Figure 5.6 Port Type FTU11a ........................
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Page 4: Preface
TX Family TMPM471F10FG Input/Output Ports Preface Related Document Document name Product information Clock control and operation mode Exception Flash memory C interface version A Serial peripheral interface 12-bit analog to digital converter 32-bit timer event counter Asynchronous serial communication circuit Advanced programmable motor control circuit Advanced encoder input circuit (32bit) Debug interface... -
Page 5: Conventions
TX Family TMPM471F10FG Input/Output Ports Conventions ● Numeric formats follow the rules as shown below: Hexadecimal: 0xABC 123 or 0d123 – Only when it needs to be explicitly shown that they are decimal numbers. Decimal: 0b111 – It is possible to omit the “0b” when the number of bits can be distinctly Binary: understood from a sentence. - Page 6 TX Family TMPM471F10FG Input/Output Ports All other company names, product names, and service names mentioned herein may be trademarks of their respective companies. 6 / 41 2024-08-30 Rev. 1.0...
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Page 7: Terms And Abbreviations
TX Family TMPM471F10FG Input/Output Ports Terms and Abbreviations Some of abbreviations used in this document are as follows: Inter-integrated circuit JTAG Joint test action group Serial wire 7 / 41 2024-08-30 Rev. 1.0... -
Page 8: Outlines
TX Family TMPM471F10FG Input/Output Ports 1. Outlines It is described the register and setting of port. A list of the functions is indicated below. Function Function Description classification Programmable pull-up/Programmable pull-down/Open-drain output are Port possible. External Interrupt Interrupt pin has a noise filter (Filter width 30ns Typ.). 32-bit timer event counter Input capture input pin. -
Page 9: Signal Connection List
TX Family TMPM471F10FG Input/Output Ports 3. Signal Connection List This table is sorted the function pins by the signal name of the block diagram which is described each reference manual. Register setting of the peripherals function is being explained in the port order, so please use for a reverse lookup of port name. -
Page 10: Table 3.2 Signal Connection List: Uart Ch4/Ei2C/Tspi
TX Family TMPM471F10FG Input/Output Ports Table 3.2 Signal Connection List: UART ch4/EI2C/TSPI Function pin Port TMPM471F10FG Related reference manual name name (LQFP100) UT4RXD UT4TXDA Asynchronous serial communication circuit UT4CTS_N UT4RTS_N EI2C0SDA EI2C0SCL C interface version A EI2C1SDA EI2C1SCL TSPI0RXD TSPI0TXD TSPI0SCK TSPI0CSIN TSPI0CS0... -
Page 11: Table 3.3 Signal Connection List: T32A
TX Family TMPM471F10FG Input/Output Ports Table 3.3 Signal Connection List: T32A Function pin Port TMPM471F10FG Related reference manual name name (LQFP100) T32A00INA0 T32A00OUTA T32A00INB0 T32A00OUTB T32A00INC0 T32A00OUTC T32A01INA0 T32A01OUTA T32A01INB0 T32A01OUTB T32A01INC0 T32A01OUTC T32A02INA0 T32A02OUTA T32A02INB0 32-bit timer event counter T32A02OUTB T32A02INC0 T32A02OUTC... -
Page 12: Table 3.4 Signal Connection List: Adc
TX Family TMPM471F10FG Input/Output Ports Table 3.4 Signal Connection List: ADC Function pin Port TMPM471F10FG Related reference manual name name (LQFP100) AINA12 AINA13 AINA14 AINA15 AINA16 AINA17 AINA18 AINA19 AINA20 AINA21 AINA22 12-bit analog to digital converter AINA23 AINB12 AINB13 AINB14 AINB15 AINB16... -
Page 13: Table 3.5 Signal Connection List: Int
TX Family TMPM471F10FG Input/Output Ports Table 3.5 Signal Connection List: INT Function pin Port TMPM471F10FG Related reference manual name name (LQFP100) INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Exception INT8 INT9 INTA INTB INTC INTD INTE INTF 13 / 41 2024-08-30 Rev. -
Page 14: Table 3.6 Signal Connection List: A-Pmd/A-Enc32
TX Family TMPM471F10FG Input/Output Ports Table 3.6 Signal Connection List: A-PMD/A-ENC32 Function pin Port TMPM471F10FG Related reference Manual name name (LQFP100) EMG0 OVV0 Advanced programmable motor control circuit EMG1 OVV1 ENC0A ENC0B Advanced encoder input ENC0Z circuit (32-bit) ENC1A ENC1B ENC1Z 14 / 41 2024-08-30... -
Page 15: Table 3.7 Signal Connection List: Jtag/Sw/Trace/Control Pin
TX Family TMPM471F10FG Input/Output Ports Table 3.7 Signal Connection List: JTAG/SW/TRACE/Control Pin Function pin Port TMPM471F10FG Related reference manual name name (LQFP100) Debug interface TRST_N SWDIO SWCLK TRACECLK TRACEDATA0 Debug interface (trace) TRACEDATA1 TRACEDATA2 TRACEDATA3 Clock control and operation mode EHCLKIN Flash memory BOOT_N... -
Page 16: Registers
TX Family TMPM471F10FG Input/Output Ports 4. Registers The following registers should be set appropriately to use the ports. Each register is 32 bits. The configuration of the register depends on the port count and its function assignment. "x" and "n" in the following table show a port name and a function number, respectively. Register name Type Setting value... -
Page 17: List Of Register
TX Family TMPM471F10FG Input/Output Ports List of Register When the bit which is assigned to no functions is read, 0 is returned. The write to the bit is ignored. Table 4.1 Ports Base Address Peripheral function Channel/Unit Base address 0x400E0000 0x400E0100 0x400E0200 0x400E0300... -
Page 18: Table 4.2 Register List
TX Family TMPM471F10FG Input/Output Ports Table 4.2 Register List Address Register name Port A Port B Port C Port D Port E Port F (Base+) Data register 0x0000 [PADATA] [PBDATA] [PCDATA] [PDDATA] [PEDATA] [PFDATA] Output control register 0x0004 [PACR] [PBCR] [PCCR] [PDCR] [PECR]... -
Page 19: List Of Port Functions And Settings
TX Family TMPM471F10FG Input/Output Ports List of Port Functions and Settings It is explained about the viewpoint of a port register setting table. The column of [PxFRn] shows the function register which should be set. When this register is set to “1”, the corresponding function is enabled. -
Page 20: Port A
TX Family TMPM471F10FG Input/Output Ports 4.2.2. PORT A Table 4.3 Port A Registers Setting Reset status Control register PORT PORT Input/Output Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] type After reset Input port Input Output port Output INT3 Input FTU4a T32A00INA0 Input... - Page 21 TX Family TMPM471F10FG Input/Output Ports Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output INT8 Input FTU4a UT1RTS_N Output FTU1a [PAFR1] UT1CTS_N Input FTU1a [PAFR2] TSPI1CSIN Input FTU1a...
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Page 22: Port B
TX Family TMPM471F10FG Input/Output Ports 4.2.3. PORT B Table 4.4 Port B Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output TSPI3CS1 Output FTU1a [PBFR3] TRACECLK... -
Page 23: Port C
TX Family TMPM471F10FG Input/Output Ports 4.2.4. PORT C Table 4.5 Port C Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output Output FTU2a [PCFR6] After reset Input port... -
Page 24: Port D
TX Family TMPM471F10FG Input/Output Ports 4.2.5. PORT D Table 4.6 Port D Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output T32A04INA0 Input FTU1a [PDFR4] T32A04INC0... -
Page 25: Port E
TX Family TMPM471F10FG Input/Output Ports 4.2.6. PORT E Table 4.7 Port E Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output UT0TXDA Output FTU1a [PEFR1] UT0RXD... -
Page 26: Port F
TX Family TMPM471F10FG Input/Output Ports 4.2.7. PORT F Table 4.8 Port F Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] During reset Input FTU16a 0 (Note) 0 (Note) (BOOT_N) After reset Input port Input Output port... -
Page 27: Port G
TX Family TMPM471F10FG Input/Output Ports 4.2.8. PORT G Table 4.9 Port G Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output Output FTU2a [PGFR6] After reset Input port... -
Page 28: Port H
TX Family TMPM471F10FG Input/Output Ports 4.2.9. PORT H Table 4.10 Port H Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output INT0 input FTU4a AINA12 Input... -
Page 29: Port J
TX Family TMPM471F10FG Input/Output Ports 4.2.10. PORT J Table 4.11 Port J Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output AINB15 Input FTU5a After reset Input port... -
Page 30: Port K
TX Family TMPM471F10FG Input/Output Ports 4.2.11. PORT K Table 4.12 Port K Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output INTE Input FTU4a EI2C1SDA Input/Output... -
Page 31: Port P
TX Family TMPM471F10FG Input/Output Ports 4.2.14. PORT P Table 4.15 Port P Registers Setting Reset status Control register PORT PORT Input/Output type Function [PADATA] [PACR] [PAFRn] [PAOD] [PAPUP] [PAPDN] [PAIE] After reset Input port Input Output port Output AINA20 Input FTU5a After reset Input port... -
Page 32: Block Diagrams Of Ports
TX Family TMPM471F10FG Input/Output Ports 5. Block Diagrams of Ports The ports have these types of circuits, FTU1a to FTU5a, FTU11a and FTU16a. Each circuit diagram is shown in the following. The dot line block shows an equivalent circuit which is described in "Datasheet". The "I/O Reset"... -
Page 33: Type Ftu2A
TX Family TMPM471F10FG Input/Output Ports Type FTU2a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) Output function enable [PxFRn] (Function control) Function output Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Port read Function input Figure 5.2 Port Type FTU2a 33 / 41 2024-08-30... -
Page 34: Type Ftu3A
TX Family TMPM471F10FG Input/Output Ports Type FTU3a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) [PxFRn] (Function control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Port read Noise filter Function input (30ns Typ.) Figure 5.3 Port Type FTU3a 34 / 41 2024-08-30... -
Page 35: Type Ftu4A
TX Family TMPM471F10FG Input/Output Ports Type FTU4a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Port read Noise filter Function input (30ns Typ.) Figure 5.4 Port Type FTU4a 35 / 41 2024-08-30 Rev. -
Page 36: Type Ftu5A
TX Family TMPM471F10FG Input/Output Ports Type FTU5a I/O reset [PxPUP] (Pull-up control) [PxPDN] (Pull-down control) [PxCR] (Output control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) Analog input Port read Figure 5.5 Port Type FTU5a 36 / 41 2024-08-30 Rev. -
Page 37: Type Ftu11A
TX Family TMPM471F10FG Input/Output Ports Type FTU11a I/O reset [PxPDN] (Pull-down control) Port External clock input enable Input ([CGOSCCR]<EOSCEN> = 10) [PxIE] (Input control) Port read EHCLKIN Oscillation circuit Figure 5.6 Port Type FTU11a 37 / 41 2024-08-30 Rev. 1.0... -
Page 38: Type Ftu16A
TX Family TMPM471F10FG Input/Output Ports Type FTU16a RESET_N [PxPUP] (Pull up control) [PxPDN] (Pull down control) [PxCR] (Output control) Port [PxDATA] Input/Output (Output latch) [PxOD] (Open-drain control) [PxIE] (Input control) BOOT_N Figure 5.7 Port Type FTU16a 38 / 41 2024-08-30 Rev. -
Page 39: Precaution
TX Family TMPM471F10FG Input/Output Ports 6. Precaution Pin Status During Reset Period During the reset period, the pin status is high-impedance except for below pins. And, the pull-up/pull-down is invalid. ● The debug interface alternate pins (PB3 to PB6) are debugging pin status. ●... -
Page 40: Revision History
TX Family TMPM471F10FG Input/Output Ports 7. Revision History Table 7.1 Revision History Revision Date Description 2024-08-30 - First release 40 / 41 2024-08-30 Rev. 1.0... -
Page 41: Restrictions On Product Use
Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for.
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