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The PE25203 is an ultra-high efficiency charge pump capacitor divider that is configurable to divide down an input voltage by two or three and deliver up to 4A output at up to 99% peak efficiency. The PE25203 supports an input voltage range of 5.7V to 10V in divide-by-2 and 8.4V to 15V in divide-by-3 mode and is available in a WLCSP package.
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■ DC test leads Caution: The PE25203 EVK contains components that might be damaged by exposure to voltages more than the specified voltage, including voltages produced by electrostatic discharges. Handle the board in accordance with procedures for handling static-sensitive components. Avoid applying excessive voltages to the power supply terminals or signal inputs or outputs.
The evaluation board is designed to ease customer evaluation of the PE25203. This section guides you through configuring the hardware and the start-up procedures. The evaluation board is shown in Figure 1.The board contains: ■ Input/output terminals ■ PCB headers ■...
Table 4. Two-way PCB Header Information Table 5 includes information from all the test points (TP) that can be found in the PE25203 EVK. The aim of each TP is to facilitate users’ ability to capture the waveforms from critical signals, To make accurate measurements from input and output voltages, it is critical to use the SO and SI test points already included in the PE25203 EVK.
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The FREQ pin can be used to set the operating frequency of the PE25203. To save a resistor, the FREQ pin can also be connected to GND to oscillate at a nominal 200 kHz. Note that this is the frequency of oscillation at the VX pin and the charge pump frequency per phase will be switching at 50% of this value.
Test Results The following test results show the typical performance of the PE25203 evaluation board at nominal voltages 7.7V divide-by-2 and 11.55V divide-by-3. PE25203 Efficiency vs IOUT (Inductor: 100nH, TFM252012ALMAR10MTAA, Fsw=200KHz) Div2 cycle skip Div2 fixed frequency Div3 cycle skip...
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This function allows the EVK to automatically change the division ratio by measuring the input voltage. An inverting comparator with hysteresis shown in Figure 11 is implemented to achieve the auto-switch mode of the PE25203 EVK. The hysteresis is used to improve stability against noise, and it also can be used to set two different threshold voltages, Vtrigger_low to change from div3 to div2 division ratio and Vtrigger_high to change from div2 to div3 division ratio.
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Figure 15 shows the critical components require to implement the PE25203. The red lines (highlighted) are the high- power nodes in the design. Close attention must be paid to both parasitic resistance and inductance at these nodes. Figure 15. PE25203 Simplified Application Schematic http://www.murata.com/products/power...
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PE25203 IC. All components are placed on the top layer of the PCB. In the PE25203 EVK, the IC is placed as shown in Figure 16 where the Vin voltage is on the right side and the VX voltage (output voltage from IC that needs to be filtered) is on the left side.
Disclaimers The information in this document is believed to be reliable. However, Murata and its affiliates do not assume any liability for the use of this information or use of this product. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party.
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