Murata PE25203 User Manual page 21
Divide-by-2 and -3, 4a charge pump, capacitor divider
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Figure 18 shows the PCB routing of the IC, wide traces are used to reduce the resistance and multiple vias are used
to connect different layers, thus improving the vertical connection and reducing the parasitic inductance.
The figures that follow show a Type-III PCB layout example using a 4-layer board. Trace width and spacing is
0.1mm/0.1 mm. Vias size is 0.2 mm hole and 0.1 mm pad.
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Copyright ©2023 Murata Manufacturing Co., Ltd. and pSemi Corporation, a Murata Company. All rights reserved.
DOC-111189-2 (10/2023)
Figure 18. PE25203 PCB Routing Example
Page 21 of 32
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