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Phytec phyCORE-i.MX 91/93 Hardware Manual

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Hardware Manual - phyCORE-i.MX 91/93 /
phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0)
A product of PHYTEC Technology Holding Company

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Summary of Contents for Phytec phyCORE-i.MX 91/93

  • Page 1 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) A product of PHYTEC Technology Holding Company...
  • Page 2 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Document Title Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Article Number L-1070e.A0 Release Date 28.05.2024 SoM Prod. No. PCL-077 SoM PCB No.
  • Page 3 Design Considerations Preface Ordering Information Product Specific Information and Technical Support Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 91/93 Product Change Management and Information Regarding Parts Populated on the SoM / SBC PHYTEC Documentation Conversions, Abbreviations, and Acronyms...
  • Page 4 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) GPIO Changing I/O Voltage FlexIO User LED Debug Interface UART Debug Display Interfaces Low Voltage Differential Signal Display Interface (LVDS) Parallel Display Interface Camera Connections MIPI CSI-2 Interface Parallel Camera Interface (CSI)
  • Page 5 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Expansion Connector (X16) Switches CPU ON/OFF (S1) System Reset Switch (S2) Boot Mode Switch (S3) System-Level Customizing Differences in SOM Pinout Soldering Jumpers Fan (X48) I2C Connectivity I2C EEPROM (U27) USB OTG Connectivity...
  • Page 6 The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and are known to work. The schematics have been re-formatted to fit better in this hardware manual.
  • Page 7 (L-1070e.A0) 2 Preface As a member of PHYTEC's phyCORE® product family, the phyCORE‑i.MX 91/93 is one of a series of PHYTEC System on Modules (SoMs) that can be populated with different controllers, various types of memory (RAM, eMMC), and many other features.
  • Page 8 Populated on the SoM / SBC With the purchase of a PHYTEC SoM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCNs (Product Change Notifications) from vendors and distributors concerning parts that are used in our products.
  • Page 9 2.5 PHYTEC Documentation PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following: •...
  • Page 10 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0)  After finishing the Quickstart Guide, we recommend working through the Development Environment Guide. This will give you a comprehensive overview of the features and functions of both the SoM and carrier board.
  • Page 11  The BSP delivered with the phyCORE-i.MX 91/93 usually includes drivers and/or software for controlling all components such as interfaces, memory, etc. Programming close to hardware at the register level is not necessary in most cases. For this reason, this manual does not contain detailed descriptions of the controller's registers or information relevant to software development.
  • Page 12 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 3.2 Types of Signals Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal. TABLE 1: Signal Types...
  • Page 13 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Signal Type Description Abbreviation CAN FD IO Differential line pairs 120 Ohm  CAN FD level bidirectional input/output CAN_I/O © PHYTEC Messtecknik GmbH...
  • Page 14 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 3.3 Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document. TABLE 2: Abbreviations and Acronyms Used in this Manual...
  • Page 15 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Abbreviation Definition GPIO General- purpose input and output General- purpose output IRAM Internal RAM; the internal static RAM on the NXP® Semiconducto r i.MX 91/93 microcontroll Solder jumpers; these types of...
  • Page 16 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Abbreviation Definition Product Change Notification PMIC Power management Real-time clock Single Board Computer Surface mount technology System on Module; used in reference to the PCL-077/ ® phyCORE i.MX 91/93 module User button Sx (e.g.
  • Page 17 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Abbreviation Definition Virtual Machine © PHYTEC Messtecknik GmbH...
  • Page 18 The phyCORE‑i.MX 91/93 belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SoMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.
  • Page 19 1x 10/100 Mbit/s Ethernet interface and 1x  GbE (RGMII) with TSN support (the 10/100 Mbit/s Ethernet transceiver on the phyCORE-i.MX 91/93 enables a direct connection to an existing Ethernet network. The second one is available at the phyCORE-Connector with RGMII signals at TTL‑level) • 1x I C interfaces •...
  • Page 20 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 4.2 phyCORE-i.MX 91/93 Block Diagram FIGURE 1: phyCORE-i.MX 91/93 Block Diagram © PHYTEC Messtecknik GmbH...
  • Page 21 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 4.3 phyCORE-i.MX 91/93 Component Placement FIGURE 2: phyCORE-i.MX 91/93 Component Placement (Top View) © PHYTEC Messtecknik GmbH...
  • Page 22 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) FIGURE 3: phyCORE-i.MX 91/93 Component Placement (Bottom View) © PHYTEC Messtecknik GmbH...
  • Page 23 +3.3 V balls. In addition, proper implementation of the phyCORE-i.MX 91/93 module into a target application also requires connecting all GND pins. Refer to Power for more information. Before the phyCORE-i.MX 91/93 can be used, please make sure the host system meets the minimum operating requirements. These include: •...
  • Page 24 PHYTEC provides a complete pinout table for the phyCORE-i.MX 91/93 Connector (X1). This table contains a complete signal path for the phyCORE‑i.MX 91/93 and the carrier board phyBOARD-Nash, including signal names, pin muxing paths, and descriptions specific to each pin.
  • Page 25 Pins.  • It is necessary to avoid voltages at the IO pins of the phyCORE-i.MX 91/93 which are sourced from the supply voltage of peripheral devices attached to the SoM during power-up or power-down. These voltages can cause a current flow into the controller, especially if peripheral devices are attached to the interfaces of the i.MX 91/93 are supposed to be powered while the phyCORE‑i.MX...
  • Page 26 (e.g. Camera_0). Thus, some signals might not be available on your module. • As the phyCORE-i.MX 91/93 is delivered with the carrier board phyBOARD‑Nash, the pin muxing might be changed within the appropriate BSP in order to support all features of the carrier board. If so, information on the differences from the pinout given in the following tables can be found in the carrier board's documentation.
  • Page 27 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 6 Unused Signals Unused signals should be set according to the table below: TABLE 3: Abbreviations and Acronyms Used in this Manual Interface Signals Recommendation MIPI-CSI X_MIPI_CSI1_CLK_N Connect to GND X_MIPI_CSI1_CLK_P...
  • Page 28 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 7 Jumpers For configuration purposes, the phyCORE-i.MX 91/93 (PCL-077) has several solder jumpers, some of which have been installed before delivery. A typical Jumper Pad Numbering Scheme illustrates the numbering of the solder jumper pads while Jumper Locations (top...
  • Page 29 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Please pay special attention to the “TYPE” column to ensure you are using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The jumpers (J = solder jumper) have the following functions:...
  • Page 30 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Jumper Position Description Type Pin 35 = X_LCD_D9 J7 selects the signals that are connected Ω (0201) to phyCORE-Connector pin 38 Pin 38 = X_LVDS_D2_P Pin 38 = X_LCD_D12 J8 selects the signals that are connected Ω...
  • Page 31 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Jumper Position Description Type VDDR_IO = 0.6 V J17 selects the signals which are 2 x 0 Ω connected to phyCORE-Connector pins 44 (0201) and 45 1+4, 2+3 Pin 44 = LCD_D18...
  • Page 32 (VIN_3V3) to compensate for the trace inductance. Power Management IC (PMIC) (U3) The phyCORE-i.MX 91/93 provides an on-board Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the on-board components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision.
  • Page 33 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) External Logic IO Supply Voltage There are three voltage levels in consideration, with certain components requiring a voltage of 1.8 V. The voltage level (VDD_IO) of the logic interface circuitry in phyCORE can be configured to either VDD_3V3 (3.3 V) or VDD_1V8 (1.8 V) based on the settings of jumpers J13 and J14 (see...
  • Page 34 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Reset Pin 98 at X1 on the phyCORE‑Connector is designated as reset output. Pin 100 at X1 on the phyCORE‑Connector is designated as a reset input. The reset output signal X_nRESET_OUT is brought out to allow resetting devices on the carrier board. Please consider that the X_nRESET_OUT is not affected by a software reset.
  • Page 35 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) System Boot Configuration Most features of the i.MX 91/93 microcontrollers are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.
  • Page 36 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Boot X_BOOT_MODE3 X_BOOT_MODE2 X_BOOT_MODE1 X_BOOT_MODE0 Boot Source Mode Reserved LPB: Boot from Internal Fuses LPB: Serial Downloader (USB1) LPB: uSDHC1 8- bit 1.8 V eMMC LPB: uSDHC2 4- bit SD 3.0...
  • Page 37 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 6: phyCORE-i.MX 93 Boot Configuration Pins SoM Connector Pin / SoM Signal SoM Voltage Signal Level Signal Description phyBOARD-Nash Name Domain Type Carrier Board Connector Pin X_UART1_TXD/ VDD_IO 1.8 V / 3.3 V...
  • Page 38 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) System Memory The phyCORE‑i.MX 91/93 provides three types of on-board memory: TABLE 7: phyCORE‑i.MX 91/93 System Memory Low-Cost- Kit-Version Exclusive- Maximum Available Version Version One 16-bit LPDDR4 512 MB 1 GB...
  • Page 39 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) The control registers for I C port 3 are mapped between addresses 0x4253 0000 and 0x4253 FFFF. Please see the NXP Semiconductor i.MX 91/93 Reference Manual for detailed information on the registers.
  • Page 40 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 11.6 SDIO SD2 (4-bit) SDIO SD2 is a 4-bit wide interface. The I/O voltage is determined by NVCC_SD2 which is statically configured for the system to 3.3 V or 1.8 V (refer to External Logic IO Supply Voltage).
  • Page 41 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 8: SDIO Interface Pinout of SD2 SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_SD2_nRESET NVCC_SD2  1.8 V / 3.3 V...
  • Page 42 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 11.7 SDIO SD3 (4-bit) SDIO SD3 is a 4-bit wide interface. The I/O voltage is determined by VDD_IO which is statically configured for the system to 3.3 V or 1.8 V (refer to External Logic IO Supply Voltage).
  • Page 43 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 9: SDIO Interface Pinout of SD3 SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_SD3_CMD/LCD_D18 (J17 VDD_IO 1.8 V / 3.3 V...
  • Page 44 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) was added to provide compatibility mode with phyCORE-i.MX 6UL/ULL module. A straight 24 bit LCD interface (J17 1+4, 2+3) or congruent SD interface (J17 1+2, 3+4) can be selected. 11.8 Universal Asynchronous Interfaces (UARTs) The phyCORE‑i.MX 91/93 provides three high-speed universal asynchronous interfaces.
  • Page 45 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 10: UART Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_UART_TX_FLEXIO1_22 VDD_IO 1.8 V / 3.3 V...
  • Page 46 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_UART2_TXD/ VDD_IO 1.8 V / 3.3 V UART2 serial data transmit BOOT_MODE_1...
  • Page 47 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 11.9 USB Interfaces The phyCORE‑i.MX 91/93 provides two USB 2.0 interfaces, which support high-speed (480 Mbit/s), full-speed (12 Mbit/s), and low-speed (1.5 Mbit/s) operation. The applicable interface signals can be found on the phyCORE‑Connector X1.
  • Page 48 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 11: USB 1 Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_USB1_ID VDD_3V3 USB1 ID Pin...
  • Page 49 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 12: USB 2 Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_USB2_ID VDD_3V3 USB2 ID Pin X_USB2_D_N...
  • Page 50 Please note that only ENET1 has TSN support. PHYTEC has chosen to make the ETH1 available as RGMII for customers to accommodate their individual needs when it comes to choosing the right PHY or switching components applicable to their network topology.
  • Page 51 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 13: Ethernet PHY Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_ENET2_TX+ ETH_O Data A+ X_ENET2_TX- ETH_O...
  • Page 52 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 11.10.1.1 Ethernet Signal Locations of ENET2 The on-board Ethernet PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly.
  • Page 53 MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 91/93 is located on the barcode sticker attached to the module. This number is a 12-digit HEX value.
  • Page 54 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 14: ENET1 RGMII Interface Signal Locations SoM Connector Pin / SoM Signal Name SoM Voltage Domain Signal Level** Signal Type Description phyBOARD-Nash Carrier Board Connector Pin X_ENET1_TX_D3/GPIO4_2 VDD_IO 1.8 V / 3.3 V...
  • Page 55 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) SoM Connector Pin / SoM Signal Name SoM Voltage Domain Signal Level** Signal Type Description phyBOARD-Nash Carrier Board Connector Pin X_ENET1_RX_D3/I2C_FLEXIO2_13 VDD_IO 1.8 V / 3.3 V Receive Data 3 X_ENET2_MDIO VDD_IO 1.8 V / 3.3 V...
  • Page 56 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 11.11 SPI Interface The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides one SPI on the phyCORE‑Connector X1. The SPI provides one chip select signal.
  • Page 57 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 15: SPI Interface Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_SAI1_TXD0/SPI1_CLK/ VDD_IO 1.8 V / 3.3 V...
  • Page 58 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 11.12 C Interface The Inter-Integrated Circuit (I C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 91/93 contains up to four identical and independent Multimaster fast-mode I C modules.
  • Page 59 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 16: I2C Interface Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_ENET1_RX_D2/ VDD_IO 1.8 V / 3.3 V...
  • Page 60 11.13.1 I S Audio Interface (SAI) The phyCORE-i.MX 91/93 features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-Connector X1. ...
  • Page 61 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 17: SAI1 Interface Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_SAI1_TXD0/SPI1_CLK/ VDD_IO 1.8 V / 3.3 V...
  • Page 62 The CAN-FD interface of the phyCORE‑i.MX 91/93 is connected to the first FLEXCAN module (FLEXCAN1) of the phyCORE-i.MX 91/93 which is a full implementation of the CAN FD protocol specification version 2.0B. It supports a flexible message payload, ranging from 0, 8, 12, 16, 20, 24, 32, 48, and 64 bytes. It supports also standard and extended message frames and programmable bit rates of 2, 5, and 8 Mb/s.
  • Page 63 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 19: GPIO Pin Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_GPIO1_0 VDD_IO 1.8 V / 3.3 V...
  • Page 64 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_WDOG_ANY/GPIO1_15 VDD_IO 1.8 V / 3.3 V GPIO1_15 is used to trigger the PMIC WDOG_B input from the i.MX 91/93 to...
  • Page 65 Programmable state machine for offloading basic system control functions from the CPU  Note Some interfaces of the phyCORE-i.MX 91/93 are realized by using FlexIO Modules. Driver support for these interfaces is currently in development. Please check PHYTEC BSP Releases for progress and availability of driver support...
  • Page 66 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) User LED The phyCORE‑i.MX 91/93 provides one green user LED (D2) on board. It can be controlled by setting GPIO1_1 to the desired output level. A high-level turns the LED on, a low-level turns it off.
  • Page 67 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Debug Interface The phyCORE‑i.MX 91/93 is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The phyCORE‑i.MX 91/93 is equipped also with SWD, a 2-pin interface with a clock (SWDCLK), and a single bi-directional data pin (SWDIO), providing all the normal JTAG debug and test functionality.
  • Page 68 Display Interfaces 14.1 Low Voltage Differential Signal Display Interface (LVDS) The phyCORE-i.MX 91/93 offers one LVDS display interface which supports one output channel.  Note The LVDS pins are shared with some LCD pins, you can select them with jumpers (see section Jumper Settings).
  • Page 69 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 21: Display Interface LVDS Signal Locations SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_LCD_RESET/LVDS_D0_P VDD_1V8 LVDS LVDS_O LVDS DATA0+...
  • Page 70 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 14.2 Parallel Display Interface The signals from the LCD interface of the i.MX 6UL/ULL are brought out at the phyCORE‑Connector X1. An LCD with up to 24-bit bus width can be connected directly to the phyCORE‑i.MX 6UL/ULL.
  • Page 71 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 22: Parallel Display Interface Signal Location SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_LCD_ENABLE VDD_IO 1.8 V / 3.3 V...
  • Page 72 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_LCD_D6 VDD_IO 1.8 V / 3.3 V LCD data 6 Ground 0 V...
  • Page 73 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) SoM Connector Pin / phyBOARD- SoM Signal Name SoM Voltage Signal Level Signal Type Description Nash Carrier Board Connector Domain X_LCD_D16/LVDS_D3_P VDD_IO 1.8 V / 3.3 V LCD data 16 X_LCD_D17/LVDS_D3_N VDD_IO 1.8 V / 3.3 V...
  • Page 74 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) was added to provide compatibility mode with phyCORE-i.MX 6UL/ULL module. A straight 24 bit LCD interface (J17 1+4, 2+3) or congruent SD interface (J17 1+2, 3+4) can be selected. © PHYTEC Messtecknik GmbH...
  • Page 75 15.1 MIPI CSI-2 Interface The phyCORE-i.MX 91/93 offers one MIPI-CSI2 interface to connect a digital camera with a resolution of up to 12MP. The  MIPI/CSI‑2 camera interface of the i.MX 91/93 extends to the phyCORE‑Connector X1 with 2 data lanes and one clock lane.
  • Page 76 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 23: Camera Interface MIPI / CSI-1 Signal Locations SoM Connector Pin / SoM Signal Name SoM Voltage Domain Signal Level Signal Type Description phyBOARD-Nash Carrier Board Connector Pin X_MIPI_CSI1_CLK_N MIPI_CSI1_VPH CSI1_I...
  • Page 77 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 15.2 Parallel Camera Interface (CSI) The camera parallel interface CSI is available at the phyCORE‑Connector with 10 data bits, HSYNC, VSYNC, MCLK, PIXCLK, and I²C Bus.   Warning Only possible if no parallel display signals are used.
  • Page 78 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 24: Parallel Camera Interface CSI Signal Location SoM Connector Pin / SoM Signal Name SoM Voltage Domain Signal Level Signal Type Description phyBOARD-Nash Carrier Board Connector Pin pCAM_PCLK VDD_IO 1.8 V / 3.3 V...
  • Page 79 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) SoM Connector Pin / SoM Signal Name SoM Voltage Domain Signal Level Signal Type Description phyBOARD-Nash Carrier Board Connector Pin pCAM_D8 VDD_IO 1.8 V / 3.3 V CAM Data 8 pCAM_D9 VDD_IO 1.8 V / 3.3 V...
  • Page 80 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) The i.MX 91/93 processor also has an integrated RTC. By default, the RTC is supplied by the external (32 kHz or 32.768 kHz) oscillator to provide a higher level of accuracy.
  • Page 81 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 25: Camera Interface MIPI / CSI-1 Signal Locations SoM Connector Pin / SoM Signal Name SoM Voltage Domain Signal Level Signal Type Description phyBOARD-Nash Carrier Board Connector Pin X_RTC_XTALI_PMIC Low-frequency input clock...
  • Page 82 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0)  Warning If an external crystal is used, R68 must be removed from the phyCORE-i.MX 91/93 SoM. Please consider that the two signals are located underneath the module beside the GND‑pads (phyCORE- i.MX 91/93 Component Placement (Bottom View))! ©...
  • Page 83 CPU Core Frequency Scaling The phyCORE-i.MX 91/93 on the phyBOARD‑Nash can scale the clock frequency and voltage. This is used to save power and reduce heat dissipation when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).
  • Page 84 3.3 V.  These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here. ...
  • Page 85 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Ramp-Up Time (10 %-90 %) 100 µs to 10 ms Allowed Tolerance of Supply Voltage 3.2 V .. 3.5 V Max. current consumption For power measurement, a SoM (PCL-077-23231211I.A1) with 2 GB RAM, 32GB eMMC, and a MIMX9352CVVXMAB.
  • Page 86 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 28: phyCORE-i.MX 91/93 Power Consumption Test Scenarios Case 1 Case 2 Case  3 Case 4 Case 5 Case Case Case eMMC-Boot cp random data to sdcard  CPU-Load (2x dd from /dev/urandom to /...
  • Page 87 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Additionally, some values cannot be tested. Situations such as suspending to RAM, suspending freeze, and standby mode must be tested on a case-by-case basis to ensure the application's power consumption stays within the guidelines stated above.
  • Page 88 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Product Controller  Range Other Temperature (Junction Temperature) (Case Temperature) (Ambient) Grade Commercial: 0 °C to +95 °C Consumer: 0 °C to +95 °C Consumer: 0 °C to +70 °C © PHYTEC Messtecknik GmbH...
  • Page 89 (L-1070e.A0) 18.3 Connectors on the phyCORE-i.MX 91/93 The phyCORE-i.MX 91/93 SoM can be directly soldered onto your carrier board. The dimensions of the half-hole connector and its footprint underneath can be found in Reference Points (bottom view). Four orientation marks in each corner on the bottom side can be used for automatic SMD production.
  • Page 90 Successful integration in user target circuitry greatly depends on adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. At a minimum, all GND pin neighboring signals that are being used in the application circuitry should be connected to GND.
  • Page 91 91/93 on the phyBOARD-Nash 20.1 Hardware Overview The phyBOARD‑Nash i.MX 91/93 for phyCORE-i.MX 91/93 modules is a low-cost, feature-rich software development platform supporting the NXP® Semiconductor i.MX 91/93 microcontroller. Moreover, due to the numerous standard interfaces the phyBOARD‑Nash i.MX 91/93 can serve as the bedrock for your application. At the core of the phyBOARD‑Nash i.MX 91/93 is the PCL‑077/phyCORE-i.MX 91/93 System On Module (SOM), containing the...
  • Page 92 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) • • UART • • Flexio • External RTC • Backup supply for RTC via external 2-pole pin header or with Gold cap • on-board measurement of SOM Power Consumption •...
  • Page 93 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.3 Block Diagram FIGURE 9: phyBOARD‑Nash i.MX 91/93 Block Diagram © PHYTEC Messtecknik GmbH...
  • Page 94 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.4 View of the phyBOARD-Nash i.MX 91/93 FIGURE 10: phyBOARD‑Nash i.MX 91/93 Components (top) © PHYTEC Messtecknik GmbH...
  • Page 95 FIGURE 11: phyBOARD‑Nash 91/93 Components (bottom) 20.5 Accessing the phyBOARD-Nash i.MX 91/93 Features PHYTEC phyBOARD‑Nash i.MX 91/93 is fully equipped with all mechanical and electrical components necessary for a speedy and secure start-up. 20.6 Overview of the phyBOARD-Nash i.MX 91/93 Peripherals The phyBOARD‑Nash i.MX 91/93 is depicted in...
  • Page 96 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.7 Connectors and Pin Header The following table lists all available connectors on the phyBOARD‑Nash i.MX 91/93. phyBOARD‑Nash i.MX 91/93 Components (top) and phyBOARD‑Nash i.MX 91/93 Components (bottom) highlights the location of each connector for easy identification.
  • Page 97 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) A/V connector #2 (2×8 dual entry socket 2 mm pitch) Fan (X48) Power supply 12-24 V via (2‑pole Phoenix Contact Power Connector (X49) MINI COMBICON)  Warning Ensure that all module connections do not exceed their expressed maximum voltage or current. The corresponding controller User's Manual/Data Sheets indicates maximum signal input values.
  • Page 98 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Green Indicates the presence of VBUS at the USB OTG interface (X8) Green Indicates the presence of VBUS at the USB2 HUB host interface (X36) Blue Indicates the presence of VBUS at the USB...
  • Page 99 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.9 Switches FIGURE 13: phyBOARD‑Nash i.MX 91/93 Switches The phyBOARD-Nash i.MX 91/93 is populated with 3 switches. Their function is listed in the table below: TABLE 32: phyBOARD-Nash i.MX 91/93 Buttons Description Switch...
  • Page 100 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.10 Jumpers FIGURE 14: phyBOARD‑Nash i.MX 91/93 Jumpers The phyBOARD-Nash i.MX 91/93 comes pre-configured with four removable jumpers (JP) and several solder jumpers (J). The jumpers allow flexible configuring of a limited number of features for the development purposes of the user.
  • Page 101 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) JP13 SAI1 MCLK Selection SAI1 MCLK Selection JP15 JTAG Mode Selection JTAG Interface (X41)  Note Detailed descriptions of the assembled connectors, jumpers, and switches can be found in the following sections.
  • Page 102 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.11.1.1 Power Connector (X49) The phyBOARD‑Pollux is available with one power supply connector, a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X49) suitable for a single 12 V/24 V supply voltage. The required current load capacity...
  • Page 103 11½ days. 20.11.2 UARTs The phyCORE-i.MX 91/93 supports up to 4 UART units. On the phyBOARD-Nash, TTL level signals of UART1 (the standard console) and UART2 are routed to FTDI FT2232H UART to USB converter expansion. This USB is brought out at USB Type-C connector X37.
  • Page 104 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.11.3 RS-232 and RS-485 (X40) FIGURE 17: RS-232 and RS-485 Connector (X40) Pin header connector X40 provides the UART7 signals of the i.MX 91/93 at either the RS-232 or RS-485 level The mode is selected by setting JP10 and JP11.
  • Page 105 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 37: RS-232 and RS-485 Cable Options PHYTEC Art-No. Description WF072 Insulation-displacement connector to DE-9 female WF228 Insulation-displacement connector to DE-9 male WK161 DE-9 RS-232 extension cable 1:1 3 m WK041 DE-9 null modem cable 1.8 m...
  • Page 106 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 38: RS-232/RS-485 (X40) Pin Assignment Interface Pin # Signal name Signal Type Signal Level Description N.C. not connected N.C. not connected X_RS232_RXD RS232_I Input depends on JP10 and JP11 settings.
  • Page 107 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Interface Pin # Signal name Signal Type Signal Level Description Ground N.C. not connected © PHYTEC Messtecknik GmbH...
  • Page 108 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) © PHYTEC Messtecknik GmbH...
  • Page 109 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) An adapter cable is included in the phyBOARD‑Nash i.MX 91/93 Kit to facilitate the use of the UART5 interface. The following figure shows the signal mapping of the adapter. 20.11.4 CAN FD (X39) FIGURE 18: CAN FD Connector (X39) The phyCORE i.MX 91/93 FLEXCAN1 and FLEXCAN2 interfaces are brought out at X39 and X16...
  • Page 110 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 40:  CAN FD1 (X39) Pin Assignment Interface Pin # Signal name Signal Type Signal Level Description N.C. not connected N.C. not connected X_CAN_L CAN_I/O Low-level CAN bus input/output line X_CAN_H...
  • Page 111 MAC address. To guarantee that the MAC address is unique, all addresses are managed in a central location. Phytec has acquired a pool of MAC addresses. The MAC address of the phyBOARD‑Nash i.MX 91/93 is located on the barcode sticker attached to the module.
  • Page 112 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.11.6 USB Connectivity (X8/X36) The phyBOARD-Nash i.MX 91/93 provides two USB hosts and one USB OTG interface. USB1 is accessible at connector X8 (USB Micro-AB). It is configured as USB OTG. USB OTG devices are capable of initiating a session, controlling the connection, and exchanging host and peripheral roles with each other.
  • Page 113 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) FIGURE 22: USB Host and OTG LEDs 20.11.7 USB Debug (X37) FIGURE 23: USB Debug Connector (X37) The main debug interface is UART1. UART2 is the debug interface for the M33 core. Both UART interfaces are connected to a UART-to-USB Converter (FTDI FT2232H).
  • Page 114 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.11.8 Secure Digital Memory Card / MulitMedia Card (X4)  FIGURE 24: SD/MM Card Connector (X4) The phyBOARD-Nash i.MX 91/93 provides a standard microSDHC card slot at X4 for connection to uSDHC2 interface cards.
  • Page 115 FIGURE 25: phyCAM-M MIPI CSI-2 Camera Connector (X5) The phyCORE-i.MX 91/93 on the phyBOARD-Nash offers one independent interface to connect digital camera boards with the MIPI CSI-2 interface. The 2-lane MIPI CSI-2 interface is brought out as phyCAM-M camera interface at connector X5.
  • Page 116 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 42: MIPI_CSI (X5) Pin Assignment Interface Pin # Signal name Signal Type Signal Level Description Ground X_MIPI_CSI_D0_P MIPI CSI-2 MIPI-CSI-2 Data 0 Positive Lane X_MIPI_CSI_D0_N MIPI CSI-2 MIPI-CSI-2 Data 0 Negative Lane...
  • Page 117 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Interface Pin # Signal name Signal Type Signal Level Description Ground N.C. not connected N.C. not connected Ground X_DAP_TMS_SWDIO/ OD-BI-PU 3.3 V CSI2_CTRL4 CSI_CTRL4_3V3 X_DAP_TDI/ OD-BI-PU 3.3 V CSI2_CTRL3 CSI_CTRL3_3V3 X_DAP_TCK_SWDCLK/ OD-BI-PU 3.3 V...
  • Page 118 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Interface Pin # Signal name Signal Type Signal Level Description CSI_ADDR 3.3 V Choose the I2C address of the Camera CSI_nRESET 3.3 V Hard reset for camera CSI_VCC_SELECT OD-I-PU 3.3 V Interface voltage selection open = 3.3 V...
  • Page 119 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) © PHYTEC Messtecknik GmbH...
  • Page 120 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.11.10 Boot Mode (JP12) FIGURE 26: Boot Mode (JP12) The phyBOARD-Nash i.MX 91/93 has two defined boot sequences which can be selected by configuring jumper JP12. TABLE 43: Boot Jumper Configuration JP12...
  • Page 121 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.11.11 Audio / Video Connectors (X43/X44) FIGURE 27: Audio/Video Connectors (X43/X44) The Audio/Video (A/V) connectors X43 and X44 provide an easy way to add typical A/V functions and features to the phyBOARD-Nash i.MX 91/93.
  • Page 122 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 44: X43 Pin Assignment Interface Pin # Signal name Signal Type Signal Level Description Ground X_LVDS_D2_P LVDS_O LVDS Data 2 Positive Lane X_LVDS_CLK_P LVDS_O LVDS Clock Positive Lane X_LVDS_D2_N LVDS_O LVDS Data 2 Negative Lane...
  • Page 123 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Interface Pin # Signal name Signal Type Signal Level Description Ground X_LVDS_D0_P LVDS_O MIPI DSI Data 0 Positive Lane VCC_IN_AV PWR_O 12 V to 24 V Input Supply Voltage of phyBOARD Nash...
  • Page 124 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 45: X44 Pin Assignment Interface Pin # Signal name Signal Type Signal Level Description X_USB3_HUB_D_P USB_I/O USB 2.0 Data positive X_USB3_HUB_D_N USB_I/O USB 2.0 Data negative X_nRESET_OUT_3V3 OD-BI-PU 3.3 V...
  • Page 125 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Interface Pin # Signal name Signal Type Signal Level Description N.C. not connected X_SAI1_TXD0/SPI1_CLK / 3.3 V SAI TXD0 BOOT_MODE_3_AV Ground N.C. not connected X_SAI1_TXC / 3.3 V SAI TXC SPI1_MISO_AV X_GPIO1_10_AV 3.3 V...
  • Page 126 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Interface Pin # Signal name Signal Type Signal Level Description N.C. not connected X_I2C2_SCL_3V3 OD-BI-PU 3.3 V I²C Clock N.C. not connected Ground VCC_5V_AV PWR_O 5 V Supply VCC_3V3_AV PWR_O 3.3 V 3.3 V Supply...
  • Page 127 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0)  Note The SAI1 interface is currently unavailable due to a hardware issue (X_SAI1_TXC/SPI1_MISO and X_SAI1_RXD0/SPI1_MOSI are swapped). This issue affects only the 1616.0 Board. 20.11.11.1 SAI1 MCLK Selection FIGURE 28: SAI1 MCLK Selection (JP13) The default debug console for the M33 is UART2.
  • Page 128 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.11.12 Expansion Connector (X16) Expansion connector X16 provides an easy way to add other functions and features to the phyBOARD-Nash i.MX 91/93. Standard interfaces such as USB, UART, SD, SPI, I...
  • Page 129 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 20.12.3 Boot Mode Switch (S3)  The phyBOARD‑Nash i.MX 91/93 has several defined boot sources that can be selected with DIP switch S3. More information about the Boot Switch can be found in the section Boot Mode Selection.
  • Page 130 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 21 System-Level Customizing This section addresses advanced developers who want to design custom expansion boards or display adapters. It includes detailed information on the different interfaces and features of the phyBOARD-Nash i.MX 91/93 at a system level.
  • Page 131 21.3 Fan (X48) FIGURE 30: Fan (X48) If heatsinking is required for the phyCORE-i.MX 91/93, a PWM-controlled fan can be connected to the phyBOARD- Nash. The fan's supply voltage is 5 V and the PWM signal is brought out as open-drain.
  • Page 132 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 21.4 I C Connectivity  The I2C2 interface of the i.MX 91/93 is available at different connectors on the phyBOARD‑Nash i.MX 91/93. The following table provides a list of connectors and pins with I C connectivity.
  • Page 133 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 21.5 C EEPROM (U27) The phyBOARD‑Nash is populated with a non-volatile 4 kB I C EEPROM at U27. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I C port 2 on the i.MX 91/93.
  • Page 134 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 21.7 Expansion Connector (X16)  FIGURE 31: Expansion Connector (X16) Expansion connector X16 (2×30 socket connector 2 mm pitch) provides an easy way to add other functions and features to the phyBOARD‑Nash i.MX 91/93. Standard interfaces such as UART, I...
  • Page 135 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Signal Name Signal Signal Level Description Type X_UART5_RX/ 1.8 V UART 5 receive data CAN2_TX Ground X_UART3_RX/ 1.8 V Refer to the i.MX 91/93 Datasheet for GPIO2_15 all muxing options X_I2C2_SDA OD-BI-PU 1.8 V...
  • Page 136 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Signal Name Signal Signal Level Description Type X_SD3_CMD 1.8 V SD/MMC command X_SD3_D0 1.8 V SD/MMC data 0 X_SD3_CLK 1.8 V SD/MMC clock X_SD3_D1 1.8 V SD/MMC data 1 Ground X_SD3_D2 1.8 V...
  • Page 137 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Signal Name Signal Signal Level Description Type X_GPIO4_26/ 1.8 V External RTC interrupt output RTC_nINT Ground X_GPIO3_27/ 1.8 V Refer to the i.MX 91/93 Datasheet for CCM_CLK2 all muxing options X_nRESET_IN 1.8 V...
  • Page 138 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) Signal Name Signal Signal Level Description Type VCC_IN PWR_O Backlight power supply X_ETH1_LED_1 3.3 V GPIO_1 pin of phyCORE i.MX 91/93 Ethernet-PHY Ti DP83867 Ground VCC5V PWR_O 5.0 V 5 V input supply voltage 5.
  • Page 139 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) TABLE 54: JTAG Connector Pinout Interface Pin # Signal Name Signal Type Signal Level Description VCC1V8 PWR_O 1.8 V Vtref reference voltage 1.8 V X_DAP_TMS_SWDIO/ 1.8 V JTAG TMS CSI_CTRL4 Ground X_DAP_TCK_SWDCLK/ 1.8 V...
  • Page 140 Hardware Manual - phyCORE-i.MX 91/93 / phyBOARD-Nash (1607.1/1616.0) (L-1070e.A0) 22 Revision History TABLE 55: Revision History Date Version # Changes in this manual Preliminary Manual Describes the phyCORE‑i.MX 91/93 28.05.2024 L-1070e.A0 SoM Version: 1607.1 Describes the phyBOARD-Nash PCB Version: 1616.0...

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