Technical Reference Guide
CHAPTER 4 SYSTEM SUPPORT ..............................................................................................................
4.1
INTRODUCTION....................................................................................................................... 4-1
4.2
PCI BUS OVERVIEW ................................................................................................................ 4-2
4.2.1
PCI BUS TRANSACTIONS............................................................................................... 4-3
4.2.2
4.2.3
OPTION ROM MAPPING ................................................................................................. 4-7
4.2.4
PCI INTERRUPTS.............................................................................................................. 4-7
4.2.5
4.2.6
PCI SUB-BUSSES .............................................................................................................. 4-7
4.2.7
PCI CONNECTOR ............................................................................................................. 4-8
4.3
AGP BUS OVERVIEW .............................................................................................................. 4-9
4.3.1
BUS TRANSACTIONS ...................................................................................................... 4-9
4.3.2
AGP CONNECTOR.......................................................................................................... 4-13
4.4
SYSTEM RESOURCES ........................................................................................................... 4-14
4.4.1
INTERRUPTS................................................................................................................... 4-14
4.4.2
DIRECT MEMORY ACCESS.......................................................................................... 4-18
4.5
4.6
4.6.1
CLEARING CMOS........................................................................................................... 4-22
4.6.2
4.6.3
4.7
SYSTEM MANAGEMENT...................................................................................................... 4-24
4.7.1
SECURITY FUNCTIONS ................................................................................................ 4-24
4.7.2
POWER MANAGEMENT ............................................................................................... 4-26
4.7.3
SYSTEM STATUS ........................................................................................................... 4-26
4.7.4
4.8
4.8.1
SYSTEM I/O MAP ........................................................................................................... 4-29
4.8.2
5.1
INTRODUCTION....................................................................................................................... 5-1
5.2
5.2.1
EIDE INTERFACES ............................................................................................................ 5-1
5.2.2
SATA INTERFACES ............................................................................................................ 5-4
5.3
DISKETTE DRIVE INTERFACE .............................................................................................. 5-6
5.3.1
5.3.2
5.4
SERIAL INTERFACE .............................................................................................................. 5-10
5.4.1
SERIAL CONNECTOR.................................................................................................... 5-10
5.4.2
5.5
PARALLEL INTERFACE ........................................................................................................ 5-13
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.6
5.6.1
5.6.2
5.6.3
iv
Featuring the Intel Pentium 4 Processor
First Edition -- June 2003