List Of Figures - HP Compaq d330 DT Technical Reference Manual

Technical Reference Guide
F 2-1. C
IGURE HP OMPAQ D
F 2-2. F V
IGURE RONT IEWS
F 2-3. R V
IGURE EAR IEWS
F 2-4. U S
IGURE LTRA LIM
F 2-5. S T
IGURE LIM OWER
F 2-6. S F
IGURE MALL ORM
F 2-7. D C
IGURE ESKTOP HASSIS
F 2-8. M
IGURE ICROTOWER
F 2-9. C
IGURE ONFIGURABLE
F 2-10. S B
IGURE YSTEM OARD
F 2-13. S A
IGURE YSTEM RCHITECTURE
F 2-14. P
IGURE ROCESSOR
F 3–1. P
IGURE ROCESSOR
F 3–2. P 4 P
IGURE ENTIUM
F 3–3. S M
IGURE YSTEM EMORY
F 4-1. PCI B D
IGURE US EVICES AND
F 4-2. C
IGURE ONFIGURATION
F 4-3. PCI C
IGURE ONFIGURATION
F 4-4. PCI B C
IGURE US ONNECTOR
F 4-5. AGP 1X D
IGURE ATA
F 4-6. AGP 2X D
IGURE ATA
F 4-7. AGP 4X D
IGURE ATA
F 4-8. AGP 8X D
IGURE ATA
F 4-9. 1.5- AGP B
IGURE VOLT
F 4-10. M
IGURE ASKABLE
F 4-11. C
IGURE ONFIGURATION
F 4-12. F C
IGURE AN ONTROL
F 5-1. 40-P IDE C
IGURE IN
F 5-2. 7-P SATA C
IGURE IN
F 5-3. 34-P D
IGURE IN ISKETTE
F 5-4. S I
IGURE ERIAL NTERFACE
F 5-5. P I
IGURE ARALLEL NTERFACE
F 5-6. 8042-T -K
IGURE O EYBOARD
F 5-7. K
IGURE EYBOARD OR
F 5-8. USB I/F, B
IGURE LOCK
F 5-9. USB P
IGURE ACKET
F 5-10. U
IGURE NIVERSAL
F 5-11. A S
IGURE UDIO UBSYSTEM
F 5-12. AC'97 L
IGURE INK
F 5-13. AD1981B A
IGURE
F 5-14. N
IGURE ETWORK
F 5-15. E
IGURE THERNET
F 6-1. 865G-B
IGURE ASED
F 6-2. 82865G GMCH I
IGURE
F 6-3. VGA M
IGURE ONITOR
hp compaq d330 and d530 Series Personal Computers
viii
Featuring the Intel Pentium 4 Processor

LIST OF FIGURES

330 530 S P
AND D ERIES
......................................................................................................................... 2-5
.......................................................................................................................... 2-6
D C L
ESKTOP HASSIS AYOUT
C L , L V
HASSIS AYOUT EFT
F C L
ACTOR HASSIS AYOUT
L , T V
AYOUT OP IEW
C L , L
HASSIS AYOUT EFT
M C L
INITOWER HASSIS
L .................................................................................................... 2-13
AYOUTS
, B
LOCK DIAGRAM
A A M
SSEMBLY ND OUNTING
/M S A
EMORY UBSYSTEM RCHITECTURE
I A
ROCESSOR NTERNAL RCHITECTURE
M .......................................................................................................... 3-7
AP
F ......................................................................................... 4-2
UNCTIONS
C ......................................................................................................... 4-4
YCLE
S M
PACE APPING
(32-B T )...................................................................................... 4-8
IT YPE
T (P T
RANSFER EAK RANSFER
T (P T
RANSFER EAK RANSFER
T (P T
RANSFER EAK RANSFER
T (P T
RANSFER EAK RANSFER
C .......................................................................................... 4-13
US ONNECTOR
I P , B
NTERRUPT ROCESSING
M M ......................................................................................... 4-22
EMORY AP
B D ......................................................................................... 4-28
LOCK IAGRAM
(
ONNECTOR ON SYSTEM BOARD
(
ONNECTOR ON SYSTEM BOARD
D C . ................................................................................... 5-9
RIVE ONNECTOR
C (M
ONNECTOR ALE
C (F
ONNECTOR
T
RANSMISSION OF
P D I
OINTING EVICE NTERFACE
D ................................................................................................... 5-24
IAGRAM
F ........................................................................................................ 5-25
ORMATS
S B C
ERIAL US ONNECTOR
F B
UNCTIONAL LOCK
B P .............................................................................................. 5-30
US ROTOCOL
C F
UDIO ODEC UNCTIONAL
I C
NTERFACE ONTROLLER
TPE C (RJ-45,
ONNECTOR
G , B
RAPHICS LOCK DIAGRAM
G
NTEGRATED RAPHICS
C , (F
ONNECTOR EMALE
First Edition –- June 2003
C ................................................. 2-1
ERSONAL OMPUTERS
, T V .............................................................. 2-7
OP IEW
............................................................................ 2-8
IEW
, T V ............................................................... 2-9
OP IEW
................................................................................. 2-10
S V ................................................................ 2-11
IDE IEW
, L S V
AYOUT EFT IDE IEW
......................................................................... 2-15
............................................................................ 2-16
............................................................... 3-1
................................................................ 3-3
................................................................................... 4-5
R : 266 MB/ ) ........................................... 4-10
ATE S
R : 532 MB/ ) ........................................... 4-11
ATE S
R : 1064 MB/ ) ......................................... 4-11
ATE S
R : 2128 MB/ ) ......................................... 4-12
ATE S
D ..................................................... 4-14
LOCK IAGRAM
). ...................................................................... 5-3
)...................................................................... 5-5
DB-9
AS VIEWED FROM REAR OF CHASSIS
DB-25
EMALE AS VIEWED FROM REAR OF CHASSIS
C ED , T D
ODE H IMING IAGRAM
C .................................................. 5-23
ONNECTOR
................................................................................ 5-27
D ........................................................... 5-29
IAGRAM
B D ................................................. 5-31
LOCK IAGRAM
B D ...................................................... 5-34
LOCK IAGRAM
VIEWED FROM CARD EDGE
............................................................................ 6-2
C ......................................................... 6-3
ONTROLLER
DB-15,
AS VIEWED FROM REAR
(M
INITOWER CONFIGURATION
) ............ 5-10
).. 5-17
.............................. 5-18
) ...................................... 5-37
). ............................... 6-7
)2-12