HP Compaq d330 DT Technical Reference Manual page 59

The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space
of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration
data (Figure 4-3), of which the first 64 bytes comprise the configuration space header.
31 24
Min. Lat.
Expansion ROM Base Address
Subsystem ID
Configuration
Space
Header
BIST
Status
Device ID
PCI Configuration Space Type 0
Data required by PCI protocol
Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest
Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on
the system board are listed in Table 4-2 (NOTE: Only device IDs that are implemented in these
systems are listed. nu = not used. n/a = not available).
Table 4-2. System Board PCI Device Identification
PCI Device
Intel 82865G GMCH:
Memory Controller
AGP Bridge
Intgrated Graphics
Intel 82801EB ICH5:
PCI Bridge
LPC Bridge
EIDE (UATA) Controller
Serial ATA (SATA)
USB Controller #1
USB Controller #2
USB Controller #3
USB 2.0 Controller
SMBus Controller
AC97 Audio Controller
Broadcom BCM5782 NIC
23 16 15 8 7
Device-Specific Area
Min. GNT Int. Pin Int. Line
Reserved
Reserved
Subsystem Vendor ID
Card Bus CIS Pointer
Base Address Registers
Hdr. Type Lat. Timer Line Size
Class Code Revision ID
Command
Vendor ID
System Board PCI Device Identification
Device
Controller
0 Index 31
FCh
40h
Bridge Control
3Ch
38h
34h
30h I/O Limit Upper 16 Bits
2Ch
28h
Prefetch. Mem. Limit
Secondary Status
nd
2 Lat.Tmr
10h
BIST
0Ch
08h
04h
00h
Not required
Table 4-2.
Vendor ID
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
n/a
hp compaq d330 and d530 Series of Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - June 2003
Technical Reference Guide
24 23 16 15
Device-Specific Area
Int. Pin
Expansion ROM Base Address
Reserved
I/O Base Upper 16 Bits
Prefetchable Limit Upper 32 Bits
Prefetchable Base Upper 32 Bits
Prefetch. Mem. Base
Memory Limit Memory Base
I/O Limit
Sub. Bus # Sec. Bus #
Base Address Registers
Hdr. Type Lat. Timer
Class Code
Status Command
Device ID Vendor ID
PCI Configuration Space Type 1
Dev ice ID
2570h
2571h
2572h
244Eh
24D0h
24DBh
24D1h
24D2h
24D4h
24D7h
24DDh
24D3h
24D5h
n/a
Index
8 7 0
FCh
40h
3Ch
Int. Line
38h
34h
30h
2Ch
28h
24h
20h
1Ch
I/O Base
18h
Pri. Bus #
10h
0Ch
Line Size
08h
Revision ID
04h
00h
4-5