HP Compaq d330 DT Technical Reference Manual page 52

Chapter 3 Processor/Memory Subsystem
The SPD address map is shown below.
Table 3–1. SPD Address Map (SDRAM DIMM)
Byte Description
0 No. of Bytes Written Into EEPROM
1 Total Bytes (#) In EEPROM
2 Memory Type
3 No. of Row Addresses On DIMM
4 No. of Column Addresses On DIMM
5 No. of Module Banks On DIMM
6, 7 Data Width of Module
8 Voltage Interface Standard of DIMM
9 Cycletime @ Max CAS Latency (CL)
10 Access From Clock
11 Config. Type (Parity, Nonparity, etc.)
12 Refresh Rate/Type
13 Width, Primary DRAM
14 Error Checking Data Width
15 Min. Clock Delay
16 Burst Lengths Supported
17 No. of Banks For Each Mem. Device
18 CAS Latencies Supported
19 CS# Latency
20 Write Latency
21 DIMM Attributes
22 Memory Device Attributes
23 Min. CLK Cycle Time at CL X-1
24 Max. Acc. Time From CLK @ CL X-1
NOTES:
[1] Programmed as 128 bytes by the DIMM OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be
re-sent as highest order CAS# address.
[4] Refer to memory manufacturer's datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] HP usage. This system requires that the DIMM EEPROM have this
space available for reads/writes.
[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is
invalid.
Can also be used to indicate s/n mismatch and flag system adminstrator of possible system
Tampering.
[11] Contains the socket # of the module (first module is "1"). Intended as backup identifier (refer to
note [10]).
3-6 hp compaq d330 and d530 Series Personal Computers
Featuring the Intel Pentium 4 Processor
Table 3-3.
SPD Address Map (SDRAM DIMM)
Notes
[1]
[2]
[3]
[4]
[4]
[4] [5]
[6]
[4]
[4]
[4]
[4]
[7]
[7]
First Edition - June 2003
Byte Description
25 Min. CLK Cycle Time at
CL X-2
26 Max. Acc. Time From
CLK @ CL X-2
27 Min. Row Prechge. Time
28 Min. Row Active to Delay
29 Min. RAS to CAS Delay
30, 31 Reserved
32..61 Superset Data
62 SPD Revision
63 Checksum Bytes 0-62
64-71 JEP-106E ID Code
72 DIMM OEM Location
73-90 OEM's Part Number
91, 92 OEM's Rev. Code
93, 94 Manufacture Date
95-98 OEM's Assembly S/N
99-125 OEM Specific Data
126 Intel frequency check
127 Reserved
128-131 Compaq header "CPQ1"
132 Header checksum
133-145 Unit serial number
146 DIMM ID
147 Checksum
Reserved
Notes
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[9]
[9]
[9] [10]
[9] [11]
[9]
[9]