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Phytec phyCORE-i.MX 91 Hardware Manual

1607.0/1472.4
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Hardware Manual - phyCORE-i.MX 91/93/
phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)
A product of PHYTEC Technology Holding Company

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Summary of Contents for Phytec phyCORE-i.MX 91

  • Page 1 Hardware Manual - phyCORE-i.MX 91/93/ phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) A product of PHYTEC Technology Holding Company...
  • Page 2 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Document Title Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Article Number L-1058e.A1 Release Date 30.11.2023 SOM Prod. No. PCL-077 SOM PCB No. 1607.0 SBC Prod. No.: PBA-CD-10 CB PCB No.: ...
  • Page 3 Design Considerations Preface Ordering Information Product Specific Information and Technical Support Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 91/93 Product Change Management and Information Regarding Parts Populated on the SOM / SBC PHYTEC Documentation Conversions, Abbreviations, and Acronyms...
  • Page 4 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) GPIO Changing I/O Voltage FlexIO User LED Debug Interface UART Debug Display Interfaces Low Voltage Differential Signal Display Interface (LVDS) Parallel Display Interface Camera Connections MIPI CSI-2 Interface Parallel Camera Interface (CSI) CPU Core Frequency Scaling Technical Specifications phyCORE-i.MX 91/93 Power Consumption...
  • Page 5 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) System Reset Switch (S2) Boot Mode Switch (S3) System-Level Customizing Differences in SOM Pinout Soldering Jumpers I2C Connectivity I2C EEPROM (U27) USB OTG Connectivity Configuring the OTG Operating Mode (R34) Audio/Video Connectors (X14 and X15)

  • Page 6: Information On This Manual

    The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and are known to work. The schematics have been re-formatted to fit better in this hardware manual.

  • Page 7: Ordering Information

    (L-1058e.A1) 2 Preface As a member of PHYTEC's phyCORE® product family, the phyCORE‑i.MX 91/93 is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, eMMC), and many other features.
  • Page 8 Populated on the SOM / SBC With the purchase of a PHYTEC SOM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCNs (Product Change Notifications) from vendors and distributors concerning parts that are used in our products.
  • Page 9 2.5 PHYTEC Documentation PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following: •...
  • Page 10 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)  After finishing the Quickstart Guide, we recommend working through the Development Environment Guide. This will give you a comprehensive overview of the features and functions of both the SOM and carrier board.
  • Page 11  The BSP delivered with the phyCORE-i.MX 91/93 usually includes drivers and/or software for controlling all components such as interfaces, memory, etc. Programming close to hardware at the register level is not necessary in most cases. For this reason, this manual does not contain detailed descriptions of the controller's registers or information relevant to software development.
  • Page 12 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 3.2 Types of Signals Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal. TABLE 1: Signal Types Signal Type...
  • Page 13 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Signal Type Description Abbreviation CAN FD IO Differential line pairs 120 Ohm  CAN FD level bidirectional input/output CAN_I/O © PHYTEC Messtecknik GmbH...

  • Page 14: Abbreviations And Acronyms

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 3.3 Abbreviations and Acronyms Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document. TABLE 2: Abbreviations and Acronyms Used in this Manual...
  • Page 15 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Abbreviation Definition GPIO General- purpose input and output General- purpose output IRAM Internal RAM; the internal static RAM on the NXP® Semiconducto r i.MX 91/93 microcontroll Solder jumpers; these types of jumpers require solder...
  • Page 16 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Abbreviation Definition Product Change Notification PMIC Power management Real-time clock Single Board Computer Surface mount technology System on Module; used in reference to the PCL-077/ ® phyCORE i.MX 91/93 module User button Sx (e.g. S1, S2, etc.) used in...
  • Page 17 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Abbreviation Definition Virtual Machine © PHYTEC Messtecknik GmbH...
  • Page 18 Populated with the NXP® Semiconductor i.MX 91/93 microcontroller (FCBGA 306 11x11 mm packaging) • Up to 2 ARM-A55 cores (clock frequency up to 1.7 GHz) (for phyCORE-i.MX 91 only one ARM-A55 core and clock frequency up to 1.5 GHz) •...
  • Page 19 1x 10/100 Mbit/s Ethernet interface and 1x  GbE (RGMII) with TSN support (the 10/100 Mbit/s Ethernet transceiver on the phyCORE-i.MX 91/93 enables a direct connection to an existing Ethernet network. The second one is available at the phyCORE-Connector with RGMII signals at TTL‑level) • 1x I C interfaces •...
  • Page 20 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 4.2 phyCORE-i.MX 91/93 Block Diagram FIGURE 1: phyCORE-i.MX 91/93 Block Diagram © PHYTEC Messtecknik GmbH...
  • Page 21 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 4.3 phyCORE-i.MX 91/93 Component Placement FIGURE 2: phyCORE-i.MX 91/93 Component Placement (Top View) © PHYTEC Messtecknik GmbH...
  • Page 22 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) FIGURE 3: phyCORE-i.MX 91/93 Component Placement (Bottom View) © PHYTEC Messtecknik GmbH...
  • Page 23 +3.3 V balls. In addition, proper implementation of the phyCORE-i.MX 91/93 module into a target application also requires connecting all GND pins. Refer to Power for more information. Before the phyCORE-i.MX 91/93 can be used, please make sure the host system meets the minimum operating requirements. These include: •...

  • Page 24: Pin Description

    PHYTEC provides a complete pinout table for the phyCORE-i.MX 91/93 Connector (X1). This table contains a complete signal path for the phyCORE‑i.MX 91/93 and the carrier board phyBOARD-Segin, including signal names, pin muxing paths, and descriptions specific to each pin.
  • Page 25 Pins.  • It is necessary to avoid voltages at the IO pins of the phyCORE-i.MX 91/93 which are sourced from the supply voltage of peripheral devices attached to the SOM during power-up or power-down. These voltages can cause a current flow into the controller, especially if peripheral devices are attached to the interfaces of the i.MX 91/93 are supposed to be powered while the phyCORE‑i.MX...
  • Page 26 (e.g. Camera_0). Thus, some signals might not be available on your module. • As the phyCORE-i.MX 91/93 is delivered with the carrier board phyBOARD‑Segin, the pin muxing might be changed within the appropriate BSP in order to support all features of the carrier board. If so, information on the differences from the pinout given in the following tables can be found in the carrier board's documentation.
  • Page 27 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 6 Unused Signals It is recommended to handle unused signals according to the table below: Interface Signals Recommendation MIPI-CSI X_MIPI_CSI1_CLK_N Connect to GND X_MIPI_CSI1_CLK_P X_MIPI_CSI1_D0_N X_MIPI_CSI1_D0_P X_MIPI_CSI1_D1_N X_MIPI_CSI1_D1_P LVDS X_LVDS_CLK_N Leave unconnected X_LVDS_CLK_P...
  • Page 28 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 7 Jumpers For configuration purposes, the phyCORE-i.MX 91/93 (PCL-077) has several solder jumpers, some of which have been installed prior to delivery. A typical Jumper Pad Numbering Scheme illustrates the numbering of the solder jumper pads while Jumper Locations (top...
  • Page 29 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) FIGURE 6: Jumper Location (top view) Please pay special attention to the “TYPE” column to ensure you are using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The jumpers (J = solder jumper) have the following functions:...
  • Page 30 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Jumper Position Description Type Pin 26 = X_LVDS_D1_P Pin 26 = X_LCD_D1 J4 selects the signals that are connected Ω (0201) to phyCORE-Connector pin 27 Pin 27 = X_LVDS_D1_N Pin 27 = X_LCD_D2...
  • Page 31 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Jumper Position Description Type Pin 42 = X_LVDS_D3_P Pin 42 = X_LCD_D16 J10 selects the signals that are connected Ω (0201) to phyCORE-Connector pin 43 Pin 43 = X_LVDS_D3_N Pin 43 = X_LCD_D17...

  • Page 32: Power Domains

    (VIN_3V3) to compensate for the trace inductance. Power Management IC (PMIC) (U3) The phyCORE-i.MX 91/93 provides an on-board Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the on-board components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision.
  • Page 33 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) External Logic IO Supply Voltage There are three voltage levels in consideration, with certain components requiring a voltage of 1.8 V. The voltage level (VDD_IO) of the logic interface circuitry in phyCORE can be configured to either VDD_3V3 (3.3 V) or VDD_1V8 (1.8 V) based on the settings of jumpers J13 and J14 (see...
  • Page 34 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Reset Pin 98 at X1 on the phyCORE‑Connector is designated as reset output. Pin 100 at X1 on the phyCORE‑Connector is designated as a reset input. The reset output signal X_nRESET_OUT is brought out to allow resetting devices on the carrier board. Please consider that the X_nRESET_OUT is not affected by a software reset.

  • Page 35: System Boot Configuration

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) System Boot Configuration Most features of the i.MX 91/93 microcontrollers are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.
  • Page 36 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Boot X_BOOT_MODE3 X_BOOT_MODE2 X_BOOT_MODE1 X_BOOT_MODE0 Boot Source Mode Reserved LPB: Boot from Internal Fuses LPB: Serial Downloader (USB1) LPB: uSDHC1 8- bit 1.8 V eMMC LPB: uSDHC2 4- bit SD 3.0 LPB: FlexSPI...
  • Page 37 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 5: phyCORE-i.MX 93 Boot Configuration Pins SOM Connector SOM Signal SOM Voltage Signal Level Signal Description Pin / phyBOARD- Name Domain Type Segin Carrier Board Connector Pin X_UART1_TXD/ VDD_IO 1.8 V / 3.3 V...

  • Page 38: System Memory

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) System Memory The phyCORE‑i.MX 91/93 provides three types of on-board memory: TABLE 6: phyCORE‑i.MX 91/93 System Memory Low-Cost- Kit-Version Exclusive- Maximum Available Version Version One 16-bit LPDDR4 512 MB 1 GB 2 GB...

  • Page 39: Serial Interfaces

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)  Warning EEPROM is reserved for future hardware introspection. Unused space might be available for customer purposes later. 11.4 Serial Interfaces The phyCORE‑i.MX 91/93 provides numerous dedicated serial interfaces, some of which are equipped with a...
  • Page 40 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 11.6 SDIO SD2 (4-bit) SDIO SD2 is a 4-bit wide interface. The I/O voltage is determined by NVCC_SD2 which is statically configured for the system to 3.3 V or 1.8 V (refer to External Logic IO Supply Voltage).
  • Page 41 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 7: SDIO Interface Pinout of SD2 SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_SD2_nRESET NVCC_SD2  1.8 V / 3.3 V...
  • Page 42 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 11.7 SDIO SD3 (4-bit) SDIO SD3 is a 4-bit wide interface. The I/O voltage is determined by VDD_IO which is statically configured for the system to 3.3 V or 1.8 V (refer to External Logic IO Supply Voltage).
  • Page 43 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 8: SDIO Interface Pinout of SD3 SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_SD3_CMD/LCD_D18 (J17 VDD_IO 1.8 V / 3.3 V...
  • Page 44 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) was added to provide compatibility mode with phyCORE-i.MX 6UL/ULL module. A straight 24 bit LCD interface (J17 1+4, 2+3) or congruent SD interface (J17 1+2, 3+4) can be selected. 11.8 Universal Asynchronous Interfaces (UARTs) The phyCORE‑i.MX 91/93 provides three high-speed universal asynchronous interfaces.
  • Page 45 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 9: UART Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_UART_TX_FLEXIO1_22 VDD_IO 1.8 V / 3.3 V UART serial data transmit...
  • Page 46 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_UART2_TXD/ VDD_IO 1.8 V / 3.3 V UART2 serial data transmit BOOT_MODE_1 © PHYTEC Messtecknik GmbH...

  • Page 47: Usb Interfaces

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 11.9 USB Interfaces The phyCORE‑i.MX 91/93 provides two USB 2.0 interfaces, which support high-speed (480 Mbit/s), full-speed (12 Mbit/s), and low-speed (1.5 Mbit/s) operation. The applicable interface signals can be found on the phyCORE‑Connector X1.
  • Page 48 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 10: USB 1 Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_USB1_ID VDD_3V3 USB1 ID Pin X_USB1_D_N VDD_3V3...
  • Page 49 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 11: USB 2 Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_USB2_ID VDD_3V3 USB2 ID Pin X_USB2_D_N VDD_3V3 USB_I/O...
  • Page 50 Please note that only ENET1 has TSN support. PHYTEC has chosen to make the ETH1 available as RGMII for customers to accommodate their individual needs when it comes to choosing the right PHY or switching components applicable to their network topology.
  • Page 51 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 12: Ethernet PHY Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_ENET2_TX+ ETH_O Data A+ X_ENET2_TX- ETH_O Data A-...

  • Page 52: Mac Address

    MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 91/93 is located on the barcode sticker attached to the module. This number is a 12-digit HEX value.
  • Page 53 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 11.10.4 ENET1 RGMII Interface In order to use an external Ethernet PHY, the RGMII/RMII interface (ENET1) of the i.MX 91/93 is brought out at phyCORE‑Connector X1. ENET1 is primarily used for TSN network operation. For that use case, an external TSN- ready ethernet switch device is used.
  • Page 54 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 13: ENET1 RGMII Interface Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Domain Signal Level** Signal Type Description phyBOARD-Segin Carrier Board Connector Pin X_ENET1_TX_D3/GPIO4_2 VDD_IO 1.8 V / 3.3 V...
  • Page 55 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) SOM Connector Pin / SOM Signal Name SOM Voltage Domain Signal Level** Signal Type Description phyBOARD-Segin Carrier Board Connector Pin X_ENET1_RX_D3/I2C_FLEXIO2_13 VDD_IO 1.8 V / 3.3 V Receive Data 3 X_ENET2_MDIO VDD_IO 1.8 V / 3.3 V...

  • Page 56: Spi Interface

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 11.11 SPI Interface The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides one SPI on the phyCORE‑Connector X1. The SPI provides one chip select signal.
  • Page 57 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 14: SPI Interface Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_SPI1_CLK/ VDD_IO 1.8 V / 3.3 V LPSPI1 Clock...
  • Page 58 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 11.12 C Interface The Inter-Integrated Circuit (I C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 91/93 contains up to four identical and independent Multimaster fast-mode I C modules.
  • Page 59 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 15: I2C Interface Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_ENET1_RX_D2/ VDD_IO 1.8 V / 3.3 V I2C Clock...

  • Page 60: Audio Interface

    11.13.1 I S Audio Interface (SAI) The phyCORE-i.MX 91/93 features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-Connector X1. ...
  • Page 61 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 16: SAI1 Interface Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_SPI1_CLK/ VDD_IO 1.8 V / 3.3 V SAI1 transmit data...

  • Page 62: Can Interface

    The CAN-FD interface of the phyCORE‑i.MX 91/93 is connected to the first FLEXCAN module (FLEXCAN1) of the phyCORE-i.MX 91/93 which is a full implementation of the CAN FD protocol specification version 2.0B. It supports a flexible message payload, ranging from 0, 8, 12, 16, 20, 24, 32, 48, and 64 bytes. It supports also standard and extended message frames and programmable bit rates of 2, 5, and 8 Mb/s.
  • Page 63 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 18: GPIO Pin Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_GPIO1_0 VDD_IO 1.8 V / 3.3 V GPIO1_0 X_ENET1_TX_D3/GPIO4_2 VDD_IO 1.8 V / 3.3 V...
  • Page 64 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_WDOG_ANY/GPIO1_15 VDD_IO 1.8 V / 3.3 V GPIO1_15 is used to trigger the PMIC WDOG_B input from the i.MX 91/93 to...
  • Page 65 Programmable state machine for offloading basic system control functions from the CPU  Note Some interfaces of the phyCORE-i.MX 93 are realized by using FlexIO Modules. Driver support for these interfaces is currently in development. Please check PHYTEC BSP Releases for progress and availability of driver support © PHYTEC Messtecknik GmbH...
  • Page 66 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) User LED The phyCORE‑i.MX 91/93 provides one green user LED (D2) on board. It can be controlled by setting GPIO1_1 to the desired output level. A high-level turns the LED on, a low-level turns it off.

  • Page 67: Debug Interface

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Debug Interface The phyCORE‑i.MX 91/93 is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The phyCORE‑i.MX 91/93 is equipped also with SWD, a 2-pin interface with a clock (SWDCLK), and a single bi-directional data pin (SWDIO), providing all the normal JTAG debug and test functionality.

  • Page 68: Display Interfaces

    Display Interfaces 14.1 Low Voltage Differential Signal Display Interface (LVDS) The phyCORE-i.MX 91/93 offers one LVDS display interface which supports one output channel.  Note The LVDS pins are shared with some LCD pins, you can select them with jumpers (see section Jumper Settings).
  • Page 69 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 20: Display Interface LVDS Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_LCD_RESET/LVDS_D0_P VDD_1V8 LVDS LVDS_O LVDS DATA0+ X_LCD_D0/LVDS_D0_N...

  • Page 70: Parallel Display Interface

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 14.2 Parallel Display Interface The signals from the LCD interface of the i.MX 6UL/ULL are brought out at the phyCORE‑Connector X1. Thus an LCD display with up to 24-bit bus width can be connected directly to the phyCORE‑i.MX 6UL/ULL.
  • Page 71 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 21: Parallel Display Interface Signal Location SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_LCD_ENABLE VDD_IO 1.8 V / 3.3 V...
  • Page 72 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_LCD_D6 VDD_IO 1.8 V / 3.3 V LCD data 6 Ground 0 V X_LCD_D7 VDD_IO 1.8 V / 3.3 V...
  • Page 73 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) SOM Connector Pin / SOM Signal Name SOM Voltage Signal Level Signal Type Description phyBOARD-Segin Carrier Board Domain Connector Pin X_LCD_D16/LVDS_D3_P VDD_IO 1.8 V / 3.3 V LCD data 16 X_LCD_D17/LVDS_D3_N VDD_IO 1.8 V / 3.3 V...
  • Page 74 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) was added to provide compatibility mode with phyCORE-i.MX 6UL/ULL module. A straight 24 bit LCD interface (J17 1+4, 2+3) or congruent SD interface (J17 1+2, 3+4) can be selected. © PHYTEC Messtecknik GmbH...

  • Page 75: Camera Connections

    15.1 MIPI CSI-2 Interface The phyCORE-i.MX 91/93 offers one MIPI-CSI2 interface to connect a digital camera with a resolution of up to 12MP. The  MIPI/CSI‑2 camera interface of the i.MX 91/93 extends to the phyCORE‑Connector X1 with 2 data lanes and one clock lane.
  • Page 76 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 22: Camera Interface MIPI / CSI-1 Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Domain Signal Level Signal Type Description phyBOARD-Segin Carrier Board Connector Pin X_MIPI_CSI1_CLK_N MIPI_CSI1_VPH CSI1_I CSI1 Clock-...
  • Page 77 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 15.2 Parallel Camera Interface (CSI) The camera parallel interface CSI is available at the phyCORE‑Connector with 10 data bits, HSYNC, VSYNC, MCLK, PIXCLK, and I²C Bus.   Warning Only possible if no parallel display signals are used.
  • Page 78 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 23: Parallel Camera Interface CSI Signal Location SOM Connector Pin / SOM Signal Name SOM Voltage Domain Signal Level Signal Type Description phyBOARD-Segin Carrier Board Connector Pin pCAM_PCLK VDD_IO 1.8 V / 3.3 V...
  • Page 79 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) SOM Connector Pin / SOM Signal Name SOM Voltage Domain Signal Level Signal Type Description phyBOARD-Segin Carrier Board Connector Pin pCAM_D8 VDD_IO 1.8 V / 3.3 V CAM Data 8 pCAM_D9 VDD_IO 1.8 V / 3.3 V CAM Data 9 ©...
  • Page 80 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) The i.MX 91/93 processor also has an integrated RTC. By default, the RTC is supplied by the external (32 kHz or 32.768 kHz) oscillator to provide a higher level of accuracy. The PMIC U3 generates also a clock signal. The following table shows the location of the RTC_XTALI/O_PMIC pins on the phyCORE-Connector X1.
  • Page 81 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 24: Camera Interface MIPI / CSI-1 Signal Locations SOM Connector Pin / SOM Signal Name SOM Voltage Domain Signal Level Signal Type Description phyBOARD-Segin Carrier Board Connector Pin X_RTC_XTALI_PMIC Low-frequency input clock X_RTC_XTALO_PMIC High-frequency input clock ©...
  • Page 82 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)  Warning If an external crystal is used, R68 must be removed from the phyCORE-i.MX 91/93 SOM (phyCORE-i.MX 91/93 Component Placement (Top View)). Please consider that the two signals are located underneath the module beside the GND‑pads (phyCORE- i.MX 91/93 Component Placement (Bottom...
  • Page 83 CPU Core Frequency Scaling The phyCORE-i.MX 91/93 on the phyBOARD‑Segin is able to scale the clock frequency and voltage. This is used to save power and reduce heat dissipation when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

  • Page 84: Technical Specifications

    3.3 V.  These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here. ...
  • Page 85 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Ramp-Up Time (10 %-90 %) 100 µs to 10 ms Allowed Tolerance of Supply Voltage 3.2 V .. 3.5 V Max. current consumption For power measurement, a SOM (PCL-077-23231211I.A0) with 2 GB RAM, 8GB eMMC, ETH0, and a MIMX9352CVUXMAA.
  • Page 86 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 27: phyCORE-i.MX 91/93 Power Consumption Test Scenarios Case 1 Case 2 Case  3 Case 4 Case 5 Case 6 eMMC-Boot SD-Card-Boot CPU-Load (2x dd from /dev/urandom to / dev/null) Ethernet-Load (Iperftest as...
  • Page 87 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)  For further information and assistance regarding your application's power consumption, please contact PHYTEC sales. 18.2 Product Temperature Grades  Warning The right temperature grade for the module greatly depends on the use case. It is necessary to determine if the use case suits the temperature range of the chosen module (see below).
  • Page 88 (L-1058e.A1) 18.3 Connectors on the phyCORE-i.MX 91/93 The phyCORE-i.MX 91/93 SOM can be directly soldered onto your carrier board. The dimensions of the half-hole connector and its footprint underneath can be found in Reference Points (bottom view). Four orientation marks in each corner on the bottom side can be used for automatic SMD production.
  • Page 89 Successful integration in user target circuitry greatly depends on adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. At a minimum, all GND pin neighboring signals that are being used in the application circuitry should be connected to GND.

  • Page 90: Hardware Overview

    External RTC • Backup supply for RTC via external 2-pole pin header or with Gold cap (lasts approx. 11½ days) 4. phyCORE-i.MX 91 has only one ARM-A55 core and a clock frequency of up to 1.5 GHz © PHYTEC Messtecknik GmbH...

  • Page 91: Block Diagram

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 20.3 Block Diagram FIGURE 9: phyBOARD‑Segin i.MX 91/93 Block Diagram © PHYTEC Messtecknik GmbH...
  • Page 92 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 20.4 View of the phyBOARD-Segin i.MX 91/93 FIGURE 10: phyBOARD‑Segin i.MX 91/93 Components (top) © PHYTEC Messtecknik GmbH...
  • Page 93 FIGURE 11: phyBOARD‑Segin 91/93 Components (bottom) 20.5 Accessing the phyBOARD-Segin i.MX 91/93 Features PHYTEC phyBOARD‑Segin i.MX 91/93 is fully equipped with all mechanical and electrical components necessary for a speedy and secure start-up. 20.6 Overview of the phyBOARD-Segin i.Mx 91/93 Peripherals The phyBOARD‑Segin i.MX 91/93 is depicted in...
  • Page 94 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 20.7 Connectors and Pin Header The following table lists all available connectors on the phyBOARD‑Segin i.MX 91/93. phyBOARD‑Segin i.MX 91/93 Components (top) and phyBOARD‑Segin i.MX 91/93 Components (bottom) highlights the location of each connector for easy identification. TABLE 29: phyBOARD‑Segin i.MX 93 Connectors and Pin Headers...
  • Page 95 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)  Warning Ensure that all module connections do not exceed their expressed maximum voltage or current. The corresponding controller User's Manual/Data Sheets indicates maximum signal input values. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.
  • Page 96 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 20.9 Switches The phyBOARD-Segin i.MX 91/93 is populated with 3 switches. Their function is listed in the table below: TABLE 31: phyBOARD-Segin i.MX 91/93 Buttons Description Switch Description Section i.MX 91/93 ON/OFF (Button) input CPU ON/OFF (S1)
  • Page 97 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Boot Selection Boot Mode (JP1) JTAG Mode Selection JTAG Interface CAN Termination Selection CAN Connectivity (X6, JP5) System Backup Voltage Selection Backup Voltage, RTC, and X3  Note Detailed descriptions of the assembled connectors, jumpers, and switches can be found in the following sections.
  • Page 98 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Segin i.MX 91/93, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.
  • Page 99 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) A detailed description of the Power Module for phyBOARDs including information on the minimum supply current can be found in the Application Guide for phyBOARD Expansion Boards (L-793e). 5. The voltage level depends on the connected power module and the voltage attached is not specified here.
  • Page 100 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)  Note The Evaluation Board (PEB-EVAL-01) delivered with the kit plugs into the expansion connector and allows easy use of the standard console (UART1) which is required for debugging. Please find additional information on the Evaluation Board in the Application Guide for phyBOARD Expansion Boards (L‑793e).
  • Page 101 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 36: X5 Pin Assignment Signal Signal X_UART5_RXD_RS232 X_UART5_RTS_RS232 X_UART5_TXD_RS232 X_UART5_CTS_RS232 X_UART5_RS485_A X_UART5_RS485_B An adapter cable is included in the phyBOARD‑Segin i.MX 91/93 Kit to facilitate the use of the UART5 interface. The following figure shows the signal mapping of the adapter.
  • Page 102 MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. Phytec has acquired a pool of MAC addresses. The MAC address of the phyBOARD‑Segin i.MX 91/93 is located on the barcode sticker attached to the module.
  • Page 103 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) FIGURE 16: USB Interfaces (X7/X8) LED D12 displays the status of USB_OTG1_VBUS and LED D11 indicates the status of X_USB_OTG2_VBUS (shown below). FIGURE 17: USB Host and OTG LEDs Two jumpers and a resistor allow configuring the USB1 interface according to your needs. Please refer to USB OTG Connectivity for more information.
  • Page 104 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) FIGURE 18: Audio Interfaces (X9/X28) TABLE 38: X9 Pin Assignment Signal Signal LINE_IN_L LINE_IN_R AGND AGND LINE_OUT_L LINE_OUT_R TABLE 39: X28 Pin Assignment Signal Description SPOP Class-D positive differential output SPOM Class-D negative differential output The audio codec can be configured via I²C interface I2C1 at address 0x18.
  • Page 105 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 40: Audio Codec Disable Jumper JP2 Mode Selection Description Audio reset signal (JP2 = 1+2) Audio codec normal operation JTAG mode (JP2 = 2+3) Audio codec disabled, JTAG interface can be used 20.11.6 CAN FD Connectivity (X6/JP5)
  • Page 106 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 41: X6 Pin Assignment Signal Signal X_CANL X_CANH Shield An adapter cable is included in the phyBOARD‑Segin i.MX 91/93 Kit to facilitate the use of the CAN interface. The following figure shows the signal mapping of the adapter.
  • Page 107 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 20.11.7 Secure Digital Memory Card / MulitMedia Card (X4)  FIGURE 20: SD/MM Card Connector (X4 (backside)) The phyBOARD-Segin i.MX 91/93 provides a standard microSDHC card slot at X4 for connection to uSDHC2 interface cards.
  • Page 108 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 43: Boot Jumper Configuration JP1 Boot Mode Description Boot mode 1 (JP1 = open) Boot from eMMC Boot mode 2 (JP1 = closed) Boot from SD/MMC 1 20.11.9 Audio / Video Connectors (X14/X15) The Audio/Video (A/V) connectors X14 and X15 provide an easy way to add typical A/V functions and features to the phyBOARD-Segin i.MX 91/93.
  • Page 109 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 20.12.1 CPU ON/OFF (S1)  The phyBOARD-Segin i.MX 91/93 is equipped with a CPU ON/OFF switch at S1. Pressing this switch will toggle the X_ONOFF signal (pin X1-99) of the phyCORE SOM low, causing the i.MX 91/93 CPU to power off. Pressing S1 for about 5 seconds turns off the phyBOARD.
  • Page 110 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 21 System-Level Customizing This section addresses advanced developers who want to design custom expansion boards or display adapters. It includes detailed information on the different interfaces and features of the phyBOARD-Segin i.MX 91/93 at a system level.
  • Page 111 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) X_RTC_nINT 3.3 V External RTC interrupt available on expansion connector X16 X_SNVS_TAMPER0 3.3V GPIO _X_AV_INT 3.3 V I2C1 Clock signal _X_GPIO1_1/nWDOG1 3.3 V I2C1 Data signal X_BOOT_MODE0 3.3 V TAMPER Signal on expansion connector 21.2 Soldering Jumpers  Numerous jumpers and 0 Ohm resistors allow configuring the phyBOARD according to your needs.
  • Page 112 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Connecting AGND and GND via a star point jumper J270, J280 I2C Connectivity Selecting I C from pin 60 61 or 95 96 J290, J300, J310, J320, J330, Selecting between Audio/SPI and JTAG/ J350, J360 UART Interfaces 21.3 I...
  • Page 113 The three lower address bits are fixed to 0x1 which means that the EEPROM can be accessed at I C address 0x54. The EEPROM has a second address on 0x5C, which is called Identification Page, and is reserved for internal PHYTEC uses only.
  • Page 114 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 8. Caution! There is no protective circuit for the USB interfaces brought out at the expansion connector X16. 21.5.1 Configuring the OTG Operating Mode (R34)  Resistor R34 configures the OTG operating mode with the OTG1_ID signal. By default, this resistor is not mounted, which leaves the ID pin floating, thus configuring the interface as USB OTG.
  • Page 115 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) X_LCD_D12 3.3 V LCD data 12 X_LCD_D13 3.3 V LCD data 13 Ground X_LCD_D14 3.3 V LCD data 14 X_LCD_D15 3.3 V LCD data 15 X_LCD_D16 3.3 V LCD data 16 X_LCD_D17 3.3 V LCD data 17 Ground [10] X_LCD_D20_AV 3.3 V...
  • Page 116 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) X_LCD_D1 3.3 V LCD data 01 Ground X_LCD_D2 3.3 V LCD data 02 X_LCD_D3 3.3 V LCD data 03 X_LCD_D4 3.3 V LCD data 04 X_LCD_D5 3.3 V LCD data 05 Ground X_LCD_CLK 3.3 V LCD pixel clock X_LCD_ENABLE 3.3 V...
  • Page 117 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 51: X15 Pin Assignment Pin # Signal Name Type Description X_SAI2_BCLK 3.3 V SAI2 transmit bit clock J290 1+4, 2+3 X_SAI2_SYNC 3.3 V SAI2 transmit frame sync. J310 1+4, 2+3 X_SAI2_RXD 3.3 V SAI2 receive data...
  • Page 118 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 21.6.1.1 Enabling Data Lines D18 to D28  Jumpers J5 and J10 allow routing data lines D18 to D23 of the phyCORE‑i.MX 91/93's parallel LCD interface to A/V connector X14 to enable implementation of a 24-bit LCD interface on a custom A/V expansion board. The following table shows the possible configurations.
  • Page 119 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 21.6.5 User Programmable GPOIs Two pins of the A/V connector X15 are dedicated as GPIO (Routing of the LCD Interface Signals J5 to J10). These signals are also available/used on the corresponding expansion boards, e.g. PEB-AV-02. For more information please look at the Expansion Boards Application Guide (L-793e).
  • Page 120 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) TABLE 54: GPIOs available at A/V Connector X15 Pin # GPIO Name Default Usage Comment GPIO5_5 Can be used as an A/V connector interrupt GPIO1_18 Expansion Connector (X16) FIGURE 24: Expansion Connector (X16) Expansion connector X16 (2×30 socket connector 2 mm pitch) provides an easy way to add other functions and...
  • Page 121 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Signal Name Type Description X_UART2_RX / 3.3 V ECSPI3 clock output J330, J350 and J360 1+2, SPI3_CLK Ground X_UART1_RX 3.3 V UART 1receive data (standard debug interface) X_I2C1_SDA 3.3 V I2C 1 data J270 ?? X_UART1_TX 3.3 V...
  • Page 122 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Signal Name Type Description X_LCD_D18 / 3.3 V SD/MMC command SD2_CMD X_LCD_D20 / 3.3 V SD/MMC data 0 SD2_D0 X_LCD_D19 / 3.3 V SD/MMC clock SD2_CLK X_LCD_D21 / 3.3 V SD/MMC data 1 SD2_D1 Ground X_LCD_D22 / 3.3 V...
  • Page 123 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Signal Name Type Description X_GPIO5_9 3.3 V [16] Power fail signal X_nRESET_IN 3.3 V Reset input  X_GPIO1_3  / 3.3 V ADC input ADC_IN3 X_SNVS_PMIC_ON_R Internal PMIC power on request Ground X_UART3_nCTS / 3.3 V CAN 1 transmit data...
  • Page 124 Please contact PHYTEC for more information about additional or new module configurations available. Default boot mode when pins X_BOOT_MODE[3:0] are left unconnected. phyCORE-i.MX 91 has only one ARM-A55 core and a clock frequency of up to 1.5 GHz The voltage level depends on the connected power module and the voltage attached is not specified here.
  • Page 125 Please contact PHYTEC for more information about additional or new module configurations available. Default boot mode when pins X_BOOT_MODE[3:0] are left unconnected. phyCORE-i.MX 91 has only one ARM-A55 core and a clock frequency of up to 1.5 GHz The voltage level depends on the connected power module and the voltage attached is not specified here.
  • Page 126 Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) Please find additional information on phyBOARD Expansion Boards in the corresponding application guide (L-791/93e). 1 2 3 4 5 6 In the default configuration of the phyBOARD‑Segin i.MX 91/93, the corresponding controller outputs of these signals are muxed as SD card interface signals SD2 and are routed to expansion connector X16 via jumpers J5 to J10.

  • Page 127: Uart Interfaces

    Please contact PHYTEC for more information about additional or new module configurations available. Default boot mode when pins X_BOOT_MODE[3:0] are left unconnected. phyCORE-i.MX 91 has only one ARM-A55 core and a clock frequency of up to 1.5 GHz The voltage level depends on the connected power module and the voltage attached is not specified here.
  • Page 128 [21] Jumpers J3 and J4 allows routing of the TTL level signals of the phyCORE-i.MX 91/93 's UART3 interface to pins 31 (UART3_RX) and 33 (UART3_TX) of expansion connector X16 to enable implementing a serial interface on a custom [22] expansion board if the SAI interface is not needed .

  • Page 129: Jtag Interface

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1)  Note The use of UART3 at expansion connector X16 requires changing the BSP and renders the SAI interface at X16 or X15 unusable. 21. Jumper  J320 and J360 must be set to 1+2, 3+4 22.

  • Page 130: Revision History

    Hardware Manual - phyCORE-i.MX 91/93/phyBOARD-Segin (1607.0/1472.4) (L-1058e.A1) 22 Revision History TABLE 58: Revision History Date Version # Changes in this manual Preliminary Manual Describes the phyCORE‑i.MX 93 27.09.2023 L-1058e.A0 SOM Version: 1607.0 PCB Version: 1472.4 30.11.2023 L-1058e.A1 Updates: SDIO, SD3, JP17 Parallel Display Interface Signals ©...

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