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Phytec phyCORE-AM65x Hardware Manual

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phyCORE
-AM65x
Hardware Manual
Document No.: L-860e.A1
SOM Prod. No.: PCM-067
SOM PCB. No.: 1498.2
CB Prod. No.: PCM-941
CB PCB. No.: 1499.3
Edition: Oct 2023
A product of a PHYTEC Technology Holding company

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  • Page 1 ® phyCORE -AM65x Hardware Manual Document No.: L-860e.A1 SOM Prod. No.: PCM-067 SOM PCB. No.: 1498.2 CB Prod. No.: PCM-941 CB PCB. No.: 1499.3 Edition: Oct 2023 A product of a PHYTEC Technology Holding company...

  • Page 2: Table Of Contents

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 1 Table of Contents Table of Contents ..........................2 List of Figures..........................6 List of Tables ..........................7 SOM Features............................9 Conventions, Abbreviations and Acronyms ................... 10 Conventions ..........................10 Abbreviations and Acronyms ......................10 Types of Signals ...........................
  • Page 3 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Power Sequencing ........................43 Safe Shutdown and Sudden Power Loss ..................43 System Memory ..........................44 SOM Memory ..........................44 6.1.1 DDR4 RAM ........................... 44 6.1.2 EEPROM ..........................44 6.1.3 eMMC Flash .......................... 44 External Memory Bus ........................45 6.2.1...
  • Page 4 PCM-067/phyCORE-AM65x System on Module L-860e.A1 UART ............................73 7.7.1 UART Pinout ......................... 74 USB ............................. 75 7.8.1 USB Pinout..........................75 7.8.2 USB Design In Considerations ....................76 7.8.3 USB Reference Circuits ......................77 Display and Camera Interfaces ......................78 VOUT ............................79 8.1.1...
  • Page 5 11.2.2 UART1 Reference Circuits ..................... 95 12 System Interfaces..........................97 12.1 RTC Pinout ..........................97 13 Integrating and Updating the phyCORE-AM65x ..................98 13.1 Integration ............................ 98 13.2 Modification ..........................98 13.3 In-Field Updates ........................... 98 13.4 Product Change Management....................... 99 14 Additional Information .........................100...

  • Page 6: List Of Figures

    Figure 6. Top Down View of Mating Connectors..................17 Figure 7. Carrier Board Alignment Hole Placement ................18 Figure 8. phyCORE-AM65x Component Placement (processor side) ............ 19 Figure 9. phyCORE-AM65x Component Placement (connector side) ............. 20 Figure 10. 3-Position Solder Jumper Pad Numbering Scheme ............... 22 Figure 11.

  • Page 7: List Of Tables

    Table 5 Solder Jumper Settings ....................... 22 Table 6 Voltage Domain Configurations ....................23 Table 7 phyCORE-AM65x Connector X1, Column A Pinout ..............29 Table 8 phyCORE-AM65x Connector X1, Column B Pinout ..............31 Table 9 phyCORE-AM65x Connector X2, Column A Pinout ..............33 Table 10 phyCORE-AM65x Connector X2, Column B Pinout..............
  • Page 8 Table 39 UART Connections at the phyCORE-Connector ............... 74 Table 40 USB Connections at the phyCORE-Connector ................. 75 Table 41 phyCORE-AM65x USB2.0 Layout Characteristics ..............76 Table 42 phyCORE-AM64xx USB3.1 Layout Characteristics ..............77 Table 43 VOUT Connections at the phyCORE-Connector ............... 79 Table 44 OLDI/LVDS Connections at the phyCORE-Connector ..............

  • Page 9: Som Features

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 2 SOM Features The phyCORE-AM65x offers the following features: • Insert-ready, sub-miniature (55 mm x 65 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology • Populated with the Texas Instruments AM65x microcontroller (23 x 23 mm, 0.8 mm pitch S-PBGA) •...

  • Page 10: Conventions, Abbreviations And Acronyms

    L-860e.A1 3 Conventions, Abbreviations and Acronyms This hardware manual describes the PCM-067 System on Module, henceforth referred to as phyCORE-AM65x. The manual specifies the phyCORE-AM65x's design and function. Precise specifications for the Texas Instruments AM65xx SoC can be found in the AM65xx Technical Reference Manual.
  • Page 11 Peripheral Component Interconnect PCIe PCI express PCM/PCL phyCORE Module (connectorized / direct solder) Product Change Notification PHYTEC Display Interface; defined to connect PHYTEC display adapter boards, or custom adapters PHYTEC Expansion Board PMIC Power management IC Power-on reset Programmable Realtime Unit...

  • Page 12: Types Of Signals

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 3.3 Types of Signals Different types of signals are brought out at the phyCORE-Connector. Table 2 below lists the abbreviations used to specify the type of a signal. Table 2 Signal Types Used in this Manual...

  • Page 13: Introduction

    SoC to the high-density pitch (0.5 mm) connectors aligning two sides of the board, allowing it to be plugged directly into a target application. Implementing a phyCORE-AM65x SOM as the core of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to re-invent microprocessor circuitry or other commonly used circuitry that has already been implemented on the phyCORE-AM65x including a DDR4 RAM, an eMMC, a power distribution network, an Ethernet PHY, an RTC, and an EEPROM.

  • Page 14: Block Diagram

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 Block Diagram Figure 2. phyCORE-AM65x Block Diagram © PHYTEC America L.L.C. 2023...

  • Page 15: Physical Dimensions

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 4.1 Physical Dimensions Figure 3. phyCORE-AM65x Dimensions Top View © PHYTEC America L.L.C. 2023...
  • Page 16 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Figure 4. phyCORE-AM65x Dimensions Bottom View Figure 5. phyCORE-AM65x Dimensions End View © PHYTEC America L.L.C. 2023...

  • Page 17: Connector Alignment For Mating To Carrier Boards

    4.2 Connector Alignment for Mating to Carrier Boards The phyCORE-AM65x has two mounting holes in the lower left and upper right corner sized for M2.5 screws/components. It is recommended to use the following mounting hardware to secure the SOM to a mating carrier board: •...
  • Page 18 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Figure 7. Carrier Board Alignment Hole Placement © PHYTEC America L.L.C. 2023...

  • Page 19: Component Placement Diagram

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 4.3 Component Placement Diagram Figure 8. phyCORE-AM65x Component Placement (processor side) © PHYTEC America L.L.C. 2023...
  • Page 20 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Figure 9. phyCORE-AM65x Component Placement (connector side) A searchable pdf of the phyCORE-AM65x component placement can be found here. © PHYTEC America L.L.C. 2023...

  • Page 21: Technical And Electrical Specifications

    Connect all ground pins to ground. • Implement a power sequencing circuit to avoid driving external power to the I/O pins of the PhyCORE-AM65x SOM before the module is fully powered up. More details on this can be found in section 5.4 Power...

  • Page 22: Solder Jumpers

    SOM to specific design needs. It shows their default positions, possible alternative positions, type, and functions. The jumpers are a 0402 package size with a 1/16W or higher power rating.
  • Page 23 Figure 11 / Figure 12. Some of the phyCORE-AM65x power domains can be configured for 1.8V or 3.3V operation via the solder jumpers in the table above. This allows for configuring the voltage levels of the associated I/O signals under these domains to meet application requirements.
  • Page 24 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Voltage Domain Jumper Associated Signals PRG1_PRU1_GPO12, PRG1_PRU1_GPO13, PRG1_PRU1_GPO14, PRG1_PRU1_GPO15, PRG1_PRU1_GPO16, PRG1_PRU1_GPO17, PRG1_PRU1_GPO18, PRG1_PRU1_GPO19 PRG2_MDIO0_MDC, PRG2_MDIO0_MDIO, PRG2_PRU0_GPO0, PRG2_PRU0_GPO1, PRG2_PRU0_GPO2, PRG2_PRU0_GPO3, PRG2_PRU0_GPO4, PRG2_PRU0_GPO5, PRG2_PRU0_GPO6, PRG2_PRU0_GPO7, PRG2_PRU0_GPO8, PRG2_PRU0_GPO9, PRG2_PRU0_GPO10, PRG2_PRU0_GPO11, PRG2_PRU0_GPO16, PRG2_PRU0_GPO17, PRG2_PRU0_GPO18, VDDSHV5 PRG2_PRU0_GPO19, PRG2_PRU1_GPO0, PRG2_PRU1_GPO1, PRG2_PRU1_GPO2,...
  • Page 25 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Figure 11. Jumper Locations (Processor side) © PHYTEC America L.L.C. 2023...
  • Page 26 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Figure 12. Jumper Locations (Connector side) © PHYTEC America L.L.C. 2023...

  • Page 27: Pin Descriptions

    Tables 7-10 provide an overview of the pinout of the phyCORE-Connector with signal names and descriptions specific to the phyCORE-AM65x SOM as well as the processor ball it connects to, if any. An example of how this information translates to our schematic is shown in Figure 14.
  • Page 28 Most of the processor pins have multiple multiplexed functions. As most of these pins are connected directly to the phyCORE-Connector, alternate functions are available by using the phyCORE-AM65x SOM's pin multiplexing options. Signal names and descriptions in the following tables 7-10, however, are in regards to the specification of the phyCORE- AM65x SOM schematic and may not line up with the functionality defined in the BSP.

  • Page 29: Pinout Table

    Refer to section Power Sequencing for more information about preventing damage from powering up too early. 4.8 Pinout Table Table 7 phyCORE-AM65x Connector X1, Column A Pinout X1, Column A SOM Signal Name Type Level...
  • Page 30 PCM-067/phyCORE-AM65x System on Module L-860e.A1 X1, Column A SOM Signal Name Type Level Processor Ball Description X_MCU_UART0_TXD 1.8V MCU UART0 Transmit Data X_MCU_UART0_RXD 1.8V MCU UART0 Receive Data X_MCU_UART0_CTSn 1.8V MCU UART0 Clear to Send X_MCU_UART0_RTSn 1.8V MCU UART0 Request to Send...
  • Page 31 The voltage level for this signal is configurable for 1.8V or 3.3V. The default voltage level is listed here, but always check the actual jumper setting for the applicable SOM configuration. Refer to section 4.6 Solder Jumpers for details. Table 8 phyCORE-AM65x Connector X1, Column B Pinout X1, Column B Signal Name Type...
  • Page 32 PCM-067/phyCORE-AM65x System on Module L-860e.A1 X1, Column B Signal Name Type Level Processor Ball Description X_USB0_VBUS USB0 VBUS input Ground X_REFCLK0N Differential SERDES0 Differential Clock Output Negative X_REFCLK0P Differential AF10 SERDES0 Differential Clock Output Positive Ground X_USB1_DP USB_IO Differential USB1 2.0 Differential Data Positive...
  • Page 33 X_MCU_ADC0_AIN1 1.8V Analog Input 1 X_MCU_ADC0_AIN2 1.8V Analog Input 2 X_MCU_ADC0_AIN3 1.8V Analog Input 3 Ground Table 9 phyCORE-AM65x Connector X2, Column A Pinout X2, Column A Signal Type Level Processor Ball Description VCC_3V3_IN PWR_I 3.3V Main Power Supply Input...
  • Page 34 PCM-067/phyCORE-AM65x System on Module L-860e.A1 X2, Column A Signal Type Level Processor Ball Description X_PRG1_RGMII1_RXC 1.8V AF22 PRU_ICSSG1 RGMII1 Receive Clock X_PRG1_RGMII1_RX_CTL 1.8V AG23 PRU_ICSSG1 RGMII1 Receive Control Ground X_MCASP0_ACLKX 3.3V MCASP0 Transmit Bit Clock X_MCASP0_AFSX 3.3V MCASP0 Transmit Frame Sync X_MCASP0_ACLKR 3.3V...
  • Page 35 The voltage level for this signal is configurable for 1.8V or 3.3V. The default voltage level is listed here, but always check the actual jumper setting for the applicable SOM configuration. Refer to section 4.6 Solder Jumpers for details. Table 10 phyCORE-AM65x Connector X2, Column B Pinout X2, Column B Processor Signal...
  • Page 36 PCM-067/phyCORE-AM65x System on Module L-860e.A1 X2, Column B Processor Signal Type Level Description Ball Ground X_PRG2_RGMII2_RD0 3.3V AH15 PRU_ICSSG2 RGMII2 Receive Data 0 X_PRG2_RGMII2_RD1 3.3V AC16 PRU_ICSSG2 RGMII2 Receive Data 1 X_PRG2_RGMII2_RD2 3.3V AD17 PRU_ICSSG2 RGMII2 Receive Data 2 X_PRG2_RGMII2_RD3 3.3V...

  • Page 37: Thermal Management

    75C without an active cooling system (heatsink and fan)). The following parts are used to attach the fan to the phyCORE-AM65x SOM processor and to connect the fan power cable to the connector on the PHYTEC phyCORE-AM65x Carrier Board:...

  • Page 38: Layout Guidelines

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 Finally, the fan is secured to the heatsink with screws. The PHYTEC Carrier Board supplies 5V power to the fan via the DF13-2P-1.25DSA connector. 4.10 Layout Guidelines 4.10.1 High-Speed Differential Signal Routing Guidelines Spacing •...

  • Page 39: General Signal Routing Guidelines

    Separate clocks and other high-speed signals as much as possible from nearby traces to reduce crosstalk. A general rule is to use a clearance of at least 3 times the trace width. 5 Power The following sub-sections discuss the power configuration of the phyCORE-AM65x in detail. Table 12 summarizes the relationships between the voltage rails and the devices on the phyCORE-AM65x SOM.

  • Page 40: Primary System Power (Vin)

    VCC_3V3_IN supplied to the SOM. For proper operation, the phyCORE-AM65x SOM must be supplied with a voltage source of 3.3V (±5 %) with a minimum 3A capacity at the VIN pins on the phyCORE-Connector. These pins are A1, A2, A3, B1, and B2 on the X2 connector. In testing the current draw of the SOM did not exceed 3A, but it is important to perform a power analysis to determine how much current your complete system (both SOM and custom CB) requires.

  • Page 41: Backup Power (Vbat)

    To keep the Real-Time Clock (RTC) module running, a secondary voltage source of 1.2-5.5V can be supplied to the phyCORE-AM65x SOM at the VBAT pin (pin B3 of phyCORE-Connector X2). For the RTC to maintain time when main system power is removed, the VBAT input must be supplied with power. PHYTEC recommends using either a battery or a large gold cap capacitor (220mF or larger) for powering VBAT.
  • Page 42 PCM-067/phyCORE-AM65x System on Module L-860e.A1 The X_MCU_PORz_OUT, X_PORz_OUT, and X_EXT_PWR_EN signals are status outputs. X_EXT_PWR_EN indicates when the SOM power is stable and X_MCU_PORz_OUT/ X_PORz_OUT are status outputs for MCU domain/ Main domain respectively. Most of the reset signals are connected to pullups/pulldowns on the SOM (X_nRESET_IN also has an attached capacitor) so pullups/pulldowns are not needed on custom CBs for these signals.

  • Page 43: Power Sequencing

    5.4 Power Sequencing It is mandatory to avoid driving the I/O pins of the phyCORE-AM65x SOM when the SOM is not fully powered up. Prematurely driving the pins may cause current to flow through the I/O pins before the processor is properly powered, potentially resulting in damage or unknown behavior after power-up or reset.

  • Page 44: System Memory

    6.1.1 DDR4 RAM The RAM on the phyCORE-AM65x is comprised of two 16-bit wide DDR4 SDRAM chips for a 32-bit wide interface providing up to 4GB of SDRAM with an optional 16-bit ECC chip. These chips are connected to the dedicated DDR subsystem of the AM65xx processor.

  • Page 45: External Memory Bus

    6.2.1 OSPI and HYPERBUS Two Octal Serial Peripheral Interface modules are supported on the phyCORE-AM65x SOM, which support single, dual, quad, or octal read and write access to external flash devices. Note that only OSPI0 supports octal mode, as OSPI1 is only a 4-bit port.

  • Page 46: Sd/Mmc/Sdio

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description MCU_HYPERBUS0_CKn X1-B47 X_MCU_OSPI0_LBCLKO 1.8V Hyperbus Differential Clock Negative MCU_HYPERBUS0_INTn X1-B64 X_MCU_OSPI0_CSn3 1.8V Hyperbus Interrupt MCU_HYPERBUS0_RESETn X1-B62 X_MCU_OSPI0_CSn1 1.8V Hyperbus Reset Output Hyperbus Reset Status Indicator from...
  • Page 47 SD card power should be connected to a 3.3V power supply regardless of the MMC IO voltage level. • SD card power needs to be toggled with on board power reset. Table 16 phyCORE-AM65x MMC1 Layout Characteristics Signal Name SOM Trace Length (µm) Length Matching (µm)

  • Page 48: System Boot Configuration

    During the power-on reset cycle, the operational system boot mode of the phyCORE-AM65x SOM is determined by the configuration of the BOOTMODE[18:9] and MCU_BOOTMODE[9:0] signals. The BOOTMODE signals must be held at the desired configuration until X_PORz_OUT goes high to be properly latched into the system.
  • Page 49 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Figure 20. BOOTMODE pullups/pulldowns © PHYTEC America L.L.C. 2023...
  • Page 50 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Table 17 MCU_BOOTMODE Description MCU_BOOTMODE Description Default Configuration Default Setting pins Selects which MMCSD port MMCSD1 connected to 1.8V LDO MCU_BOOTMODE[9] is connected to 1.8V SDIO MCU_BOOTMODE[8:5] Enabled certain power-on 0000 POST bypass tests for safety-enabled...
  • Page 51 To modify the default boot configuration on a custom carrier board, it is recommended to use 1kΩ pull-up resistors or 1kΩ pull-down resistors to override the SOM settings. For startup/verification testing, PHYTEC recommends designing the boot configuration circuit to include a DIP switch. This will make it easy to swap between various boot modes (an example circuit is shown below).

  • Page 52: Serial Interfaces

    The following sub-sections detail each of the serial interfaces supported on the phyCORE-AM65x. 7.1 CAN The phyCORE-AM65x SOM provides two Controller Area Network (CAN) ports that are part of the AM65x MCU domain for serial communication. Both interfaces support CAN and CAN FD (flexible data-rate) specifications, conforming with CAN protocol version 2.0 part A, B and ISO 11898-1:2015.

  • Page 53: Ethernet Pinout

    PHY if necessary. Refer to the DP83867IRRGZ datasheet for further details on these configuration and strapping options (DP83867IRRGZ Datasheet). NOTE: Adjusting strapping options and PHY registers is not necessary when using PHYTEC provided BSPs. Table 20 Ethernet PHY Default Strapping Configuration Strapping Option Default Setting Strapping Signals...
  • Page 54 X_WKUP_GPIO0_10 3.3V The phyCORE-AM65x provides access to three Programmable Real-Time Unit and Industrial Communication Subsystems (PRU_ICSSG), which are referred to as PRU_ICSSG0, PRU_ICSSG1, and PRU_ICSSG2. These three subsystems utilize two 32-bit RISC CPU cores, PRU0 and PRU1, as well as two auxiliary 32-bit RISC CPU cores, RTU_PRU0 and RTU_PRU1. The PRU cores are programmed with a small, deterministic instruction set and can either operate independently, in coordination with each other, or in coordination with the host CPU.
  • Page 55 PCM-067/phyCORE-AM65x System on Module L-860e.A1 NOTE: The AM65x is not rated for RGMII operation at 3.3V, which means RGMII signals must be at 1.8V. Table 23 PRU_ICSSG0 Connections at the phyCORE-Connector Processor Signal X1 Pin #(s) SOM Signal(s) Type Level...
  • Page 56 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description pr0_mii_mt0_clk X1-A88 X_GPIO1_65 3.3V PRU0 Transmit Clock 0 - (PRG0_PRU1_GPI16 with internal wrapper multiplex for MII mode) pr0_mii_mt1_clk X2-B43 X_MCASP0_AXR12 3.3V PRU0 Transmit Clock 0 -...
  • Page 57 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description PRG0_RGMII1_TD3 X2-B42 X_MCASP0_AXR11 3.3V PRU_ICSSG0 RGMII1 Transmit Data 3 PRG0_RGMII1_TXC X2-B43 X_MCASP0_AXR12 3.3V PRU_ICSSG0 RGMII1 Transmit Clock PRG0_RGMII1_TX_CTL X2-B37 X_MCASP0_AXR7 3.3V PRU_ICSSG0 RGMII1 Transmit Control...
  • Page 58 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description pr1_mii0_txen X2-A9 X_PRG1_RGMII2_TD3 1.8V PRU1 MII0 Transmit Enable - (PRG1_PRU1_GPO15 with internal wrapper multiplex for MII mode) pr1_mii0_rxlink X1-A60 X_GPIO0_64 1.8V PRU1 MII0 RX Link -...
  • Page 59 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description pr1_mii1_rxlink X1-A68 X_GPIO0_84 1.8V PRU1 MII1 RX Link - (PRG1_PRU1_GPI8 with internal wrapper multiplex for MII mode) pr1_mii1_col X1-A69 X_GPIO0_85 1.8V PRU1 MII1 Collision Detect -...
  • Page 60 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description pr2_mii0_rxd[3] X2-B15 X_PRG2_RGMII1_RD3 3.3V PRU2 MII0 Receive Data 3 - (PRG2_PRU0_GPI3 with internal wrapper multiplex for MII mode) pr2_mii0_rxdv X2-B17 X_PRG2_RGMII1_RX_CTL 3.3V PRU2 MII0 Receive Data Valid -...
  • Page 61 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description pr2_mii1_rxdv X2-B34 X_PRG2_RGMII2_RX_CTL 3.3V PRU2 MII1 Receive Data Valid - (PRG2_PRU1_GPI4 with internal wrapper multiplex for MII mode) pr2_mii1_rxer X2-B33 X_PRG2_RGMII2_RXC 3.3V PRU2 MII1 Receive Error -...

  • Page 62: Ethernet Design In Guide

    CPSW_ETH0 Ethernet Design In Considerations 7.2.2.1 • Connecting the phyCORE-AM65x SOM to an existing 10/100/1000Base-T network involves adding an RJ45 and appropriate magnetic devices in the design. See the reference circuit in section 7.2.3 Ethernet Reference Circuits for an example.
  • Page 63 NOTE: The PRG0 signals are not routed as RGMII by default on the phyCORE-AM65x SOM, so they were not directly length matched. Take extra care noting the trace lengths when routing these signals on a carrier board and adjust as needed.
  • Page 64 PRG1 RGMII1 Receive PRG1_RGMII1_RXD0 25629 PRG1_RGMII1_RXD1 25375 PRG1_RGMII1_RXD2 22149 PRG1_RGMII1_RXD3 25883 able 29 phyCORE-AM65x PRG1 RMGII2 Trace Length Characteristics Signal Name SOM Trace Length (µm) Match Group Recommended Length Match PRG1_RGMII2_TXC 41961 AVERAGE_LENGTH(TXCTL, TXD0, TXD1, TXD2, TXD3) + 1.8ns 2540 µm...
  • Page 65 PCM-067/phyCORE-AM65x System on Module L-860e.A1 PRG2_RGMII1_RXD2 35662 PRG2_RGMII1_RXD3 35331 able 31 phyCORE-AM65x PRG2 RMGII2 Trace Length Characteristics Signal Name SOM Trace Length (µm) Match Group Recommended Length Match AVERAGE_LENGTH(TXCTL, TXD0, TXD1, TXD2, TXD3) + PRG2_RGMII2_TXC 40107 1.8ns 2540 µm PRG2_RGMII2_TXCTL...

  • Page 66: Ethernet Reference Circuits

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 PRG0_RGMII2_TXD0 55956 PRG0 RGMII2 Transmit PRG0_RGMII2_TXD1 56337 PRG0_RGMII2_TXD2 55347 PRG0_RGMII2_TXD3 77343 PRG0_RGMII2_RXC 48844 AVERAGE_LENGTH(RXCTL, RXD0, RXD1, RXD2, RXD3) + 1.8ns PRG0_RGMII2_RXCTL 23774 2540 µm PRG0 RGMII2 Receive PRG0_RGMII2_RXD0 102260 PRG0_RGMII2_RXD1 72619 PRG0_RGMII2_RXD2 107036 PRG0_RGMII2_RXD3 45822 7.2.3 Ethernet Reference Circuits...
  • Page 67 The Inter-Integrated Circuit (I C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE-AM65x SOM provides six independent multimaster fast-mode I modules. The I C interfaces provide the following functionality:...

  • Page 68: I 2 C

    WKUP I2C0 Data 7.4 MCASP The phyCORE-AM65x SOM provides three multichannel audio serial port modules which can operate in both transmit or receive modes. Each module features a TDM stream, I2S protocols, and inter-component digital audio interface transmission. Here is a breakdown of the three modules available: •...

  • Page 69: Mcasp Pinout

    PCM-067/phyCORE-AM65x System on Module L-860e.A1 Some of the MCASP1 and MCASP2 signals are muxed with MCASP0 signals, and therefore these modules cannot be implemented simultaneously in their entirety. 7.4.1 MCASP Pinout Table 35 MCASP Connections at the phyCORE-Connector Processor Signal...

  • Page 70: Pcie

    MCASP2 Serial Data 3 7.5 PCIe The PCI Express interface of the phyCORE-AM65x SOM provides PCIe Gen. 3.1 functionality which supports 8 Gbit/s operation. Furthermore, the interface is backwards compatible to the 2.5 Gbit/s Gen1 specification. There are two PCIe subsystems, PCIE0 and PCIE1, which can be configured as follows: •...

  • Page 71: Pcie (Serdes) Design In Considerations

    SERDES ports are implemented. The external clock must be a high-quality, low-jitter differential 100MHz clock source compliant to the PCIe REFCLK AC specifications. We recommend using the PI6C557-03 clock generator, which is implemented on the PHYTEC carrier board. A PCIe reference circuit is shown in section 7.5.3 PCIe Reference Circuits.

  • Page 72: Spi

    A PCIe clock generator to generate the PCIe clock signals 7.6 SPI The Serial Peripheral Interface (SPI) is a transmit/receive, master/slave synchronous serial bus. The phyCORE-AM65x SOM provides access to four SPI ports at the phyCORE-Connector. © PHYTEC America L.L.C. 2023...

  • Page 73: Spi Pinout

    CPU. There are five UART modules provided, and each can be used for configuration and data exchange with external peripheral devices. UART1 is the default console and as such PHYTEC recommends bringing out UART1 for console access. More information on using it as a debug console is provided in section 11.2...
  • Page 74 PCM-067/phyCORE-AM65x System on Module L-860e.A1 7.7.1 UART Pinout Table 39 UART Connections at the phyCORE-Connector Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description UART0_CTSn X2-B50 X_UART0_CTSn 3.3V UART0 Clear to Send UART0_RTSn X2-B51 X_UART0_RTSn 3.3V UART0 Request to Send...
  • Page 75 HighSpeed USB2.0 subsystem (USB1). Both ports support Dual-Role Device capability and are configurable as host or peripheral. If additional control signals are required, such as overcurrent and power enable, they can be implemented with GPIO and USB_DRVVBUS signals. Please refer to the schematic of the phyCORE-AM65x Carrier Board (PCM-941) for a circuit example.
  • Page 76 (SOM + Carrier Board), though 4 inches is considered typical. The table below shows the length of the USB2.0 traces on the SOM and required constraints. • Route DP/DM traces close together and in parallel for noise rejection, and within 1270 mils in length of each other. Table 41 phyCORE-AM65x USB2.0 Layout Characteristics Signal Name Length (µm) Length...
  • Page 77 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Table 42 phyCORE-AM64xx USB3.1 Layout Characteristics Signal Name Length (µm) Length Single Ended Differential Matching Impedance (Ω) Impedance (Ω) Max Total Max CB (µm) Trace Trace X_SERDES0_TXP 23216 101600 78384 X_SERDES0_TXN 23114 101600 78486 X_SERDES0_RXP...
  • Page 78 A USB power switch to shut down the USB power rails if the current exceeds 0.6A • Three TVS diode arrays for ESD and EMI considerations 8 Display and Camera Interfaces The following sub-sections detail each of the display/camera interfaces supported on the phyCORE-AM65x. © PHYTEC America L.L.C. 2023...
  • Page 79 PCM-067/phyCORE-AM65x System on Module L-860e.A1 8.1 VOUT The phyCORE-AM65x SOM provides a parallel display port for supporting the following display interface modes: • Parallel MIPI DPI 2.0: RGB 16/18/24-bit output with separate sync signals • BT.656/BT.1120 interface: YUV422 output (8/10-bit modes) with embedded syncs 8.1.1 VOUT Pinout...
  • Page 80 Video Output Data Enable 8.2 OLDI/LVDS The phyCORE-AM65x SOM provides an LVDS display port with up to four data lanes and one clock lane to support serialized RGB pixel data transmission. The LVDS interface complies with the ANSI/TIA/EIA644-A standard. More information about the supported video formats are discussed in the AM65xx Technical Reference Manual.
  • Page 81 A 40-pin FFC/FPC connector 8.3 CSI The phyCORE-AM65x SOM provides an LVDS camera port with up to four data lanes and one clock lane with programmable lane positions. It supports both MIPI CSI-2 and non-MIPI LVDS camera sensors. 8.3.1 CSI Pinout...
  • Page 82 CSI supports up to 4x data lanes and 1x clock lane. • More general differential pair routing guidelines are in section 4.10.1 High-Speed Differential Signal Routing Guidelines. Table 47 phyCORE-AM65x USB0 Layout Characteristics Signal Name SOM Trace Intra-Pair Inter-Pair Single Ended...
  • Page 83 Example reference circuits for connecting the CSI signals to a 30-pin connector are shown below. The 30-pin connector pinout is designed to connect to a PHYTEC camera and supports both 3.3V and 5V cameras. Figure 32. CSI Power Toggle Reference Schematic Figure 33.
  • Page 84 The following sub-sections detail each of the control interfaces supported on the phyCORE-AM65x. 9.1 Enhanced Capture The phyCORE-AM65x SOM brings out an enhanced Capture (eCAP) module that can be used for applications such as audio sample rate measurements, measuring rotating machinery speed, measuring pulse train signals, decoding duty cycle encoded current/voltage sensors, and measuring time between position sensor pulses.
  • Page 85 PWM Output 9.2 Enhanced Pulse-Width Modulation The phyCORE-AM65x SOM supports up to six instances of Enhanced High Resolution Pulse-Width Modulator (eHRPWM) modules. High-resolution functionality extends the time resolution capabilities of the pulse-width modulator to improve performance and help satisfy high-frequency PWM requirements. These six independent PWM channels provide timing and control resources on a per PWM channel basis, with each channel providing two PWM outputs, EHRPWMx_A and EHRPWMx_B.
  • Page 86 10.1 ADC The phyCORE-AM65x SOM brings out 4x ADC analog inputs which can each be multiplexed to the single 12-bit ADC of the ADC0 module on the processor. The reference voltage, set at MCU_ADC0_REFP, is connected directly to 1.8V on the module.
  • Page 87 PCM-067/phyCORE-AM65x System on Module L-860e.A1 10.1.1 ADC Pinout Table 52 ADC Connections at the phyCORE-Connector Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description MCU_ADC0_AIN0 X1-B86 X_MCU_ADC0_AIN0 1.8V Analog Input 0 MCU_ADC0_AIN1 X1-B87 X_MCU_ADC0_AIN1 1.8V Analog Input 1 MCU_ADC0_AIN2...
  • Page 88 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor X1 Pin #(s) SOM Signal(s) Type Level Signal GPIO0_2 X2-B57 X_VOUT1_DATA2_BOOTMODE2 3.3V GPIO0_3 X2-B58 X_VOUT1_DATA3_BOOTMODE3 3.3V GPIO0_4 X2-B59 X_VOUT1_DATA4_BOOTMODE4 3.3V GPIO0_5 X2-B61 X_VOUT1_DATA5_BOOTMODE5 3.3V GPIO0_6 X2-B62 X_VOUT1_DATA6_BOOTMODE6 3.3V GPIO0_7 X2-B63 X_VOUT1_DATA7_BOOTMODE7 3.3V GPIO0_8 X2-B64 X_VOUT1_DATA8_BOOTMODE8 3.3V...
  • Page 89 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor X1 Pin #(s) SOM Signal(s) Type Level Signal GPIO0_48 X2-B33 X_PRG2_RGMII2_RXC 3.3V GPIO0_49 X2-B27 X_PRG2_RGMII2_TX_CTL 3.3V GPIO0_50 X2-B20 X_PRG2_MDIO0_MDC 3.3V GPIO0_51 X2-B22 X_PRG2_RGMII2_TD0 3.3V GPIO0_52 X2-B23 X_PRG2_RGMII2_TD1 3.3V GPIO0_53 X2-B24 X_PRG2_RGMII2_TD2 3.3V GPIO0_54 X2-B25 X_PRG2_RGMII2_TD3 3.3V...
  • Page 90 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor X1 Pin #(s) SOM Signal(s) Type Level Signal GPIO0_94 X2-A53 X_UART1_CTSn 1.8V GPIO0_95 X2-A54 X_UART1_RTSn 1.8V The voltage level for this signal is configurable for 1.8V or 3.3V. The default voltage level is listed here, but always check the actual jumper setting for the applicable SOM configuration.
  • Page 91 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Processor X1 Pin #(s) SOM Signal(s) Type Level Signal GPIO1_55 X1-A77 X_GPIO1_55 3.3V GPIO1_56 X2-A56 X_UART2_TXD 3.3V GPIO1_57 X1-A78 X_GPIO1_57 3.3V GPIO1_58 X1-A80 X_GPIO1_58 3.3V GPIO1_59 X1-A81 X_GPIO1_59 3.3V GPIO1_60 X1-A82 X_GPIO1_60 3.3V GPIO1_61 X1-A83 X_GPIO1_61 3.3V...
  • Page 92 3.3V 10.3 WIFI/BT The phyCORE-AM65x SOM a Sterling-LWB WiFi/Bluetooth module populated directly on-board and can be populated with either a 2.4 GHz or the 5 GHz variant. The MMC1 interface used to communicate with the WLAN section of the Sterling-LWB module is routed through a multiplexer switch at U30 to also allow access to the interface at the phyCORE-Connector.
  • Page 93 The following sub-sections detail each of the debug interfaces supported on the phyCORE-AM65x. 11.1 JTAG The phyCORE-AM65x SOM is equipped with a JTAG interface for downloading program code into the internal RAM or for debugging programs currently executing. The JTAG interface is accessible via the phyCORE-Connector and provides seven standard IEEE1149.6 JTAG signals.
  • Page 94 PCM-067/phyCORE-AM65x System on Module L-860e.A1 11.1.2 JTAG Reference Circuit An example reference circuit for connecting the JTAG signals to a 2x20 connector is shown below. Note that the pinout is based on TI’s compact 20-pin JTAG connector setup. More details on the specifics of that pinout can be found here...
  • Page 95 L-860e.A1 11.2 UART1 The phyCORE-AM65x SOM can also be communicated with using UART1 for downloading program code into the internal RAM or for debugging programs currently executing. UART1 is the default console and as such PHYTEC recommends bringing out UART1 for console access. The UART1 interface is accessible via the phyCORE-Connector.
  • Page 96 PCM-067/phyCORE-AM65x System on Module L-860e.A1 Figure 36. UART0 to USB Regulator Reference Schematic The circuit consists of: • Two buffers to isolate the UART signals from the bridge until SOM power is brought up • A dual UART to USB bridge to convert the UART signals into USB signals •...
  • Page 97 PCM-067/phyCORE-AM65x System on Module L-860e.A1 12 System Interfaces The following sub-section covers the on-board RTC. 12.1 RTC Pinout The on-board RTC provides accurate time keeping (±1 ppm @ 25°C) at extremely low power consumption (40 nA @ 3 V). The RTC can keep track of the year, month, date, weekday, hour, minute, and seconds and has timer, alarm, and external event input functionality.
  • Page 98 Minimum Requirements for Operation can be used as a starting point for integrating the phyCORE-AM65x SOM into target circuitry. Additional information/tools are available to facilitate the integration of the phyCORE-AM65x SOM into customer applications, such phyCORE-AM65x SOM and Carrier Board Schematic References: •...
  • Page 99 13.4 Product Change Management Use of PHYTEC products ensures interchangeable SoC core circuitry in the event of obsolescence of parts used on our SOMs and SBCs. End users no longer need to redesign entire CPU circuitry and engage in version control to accommodate new or obsolete parts.
  • Page 100 PHYTEC System on Modules (SOM) and Single Board Computers (SBC) are designed as subcomponents for integration in electrical devices. Combined with PHYTEC Carrier Boards, PHYTEC SOMs can be used as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.
  • Page 101 - are reserved. No reproduction may occur without the express written consent from PHYTEC. The information in this document has been carefully checked and is as reliable as possible. However, PHYTEC assumes no responsibility for any inaccuracies. PHYTEC neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product.
  • Page 102 Transferred document from old webpage template to new document template. Updated images to .2 SOM. Updated table 5 2023/10/30 L-860.A1 to include all the current jumpers in the .2 SOM revision. Changed references to phyCORE-AM65xx to phyCORE-AM65x. © PHYTEC America L.L.C. 2023...

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