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Phytec phyCORE-AM64xx Hardware Manual

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phyCORE
-AM64xx
®
Hardware Manual
Document No.: L-860e.A1
SOM Prod. No.: PCM-072
SOM PCB. No.: 1565.1
CB Prod. No.: PBA-C-25
CB PCB. No.: 1566.1
Edition: Oct 2022
A product of a PHYTEC Technology Holding company

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  • Page 1 -AM64xx ® Hardware Manual Document No.: L-860e.A1 SOM Prod. No.: PCM-072 SOM PCB. No.: 1565.1 CB Prod. No.: PBA-C-25 CB PCB. No.: 1566.1 Edition: Oct 2022 A product of a PHYTEC Technology Holding company...

  • Page 2: Table Of Contents

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 1 Table of Contents Table of Contents ............................2 List of Figures ............................5 List of Tables ............................6 SOM Features ............................8 Conventions, Abbreviations and Acronyms....................9 Conventions ............................9 Abbreviations and Acronyms ....................... 9 Types of Signals ..........................
  • Page 3 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Power Sequencing ..........................38 Safe Shutdown and Sudden Power Loss ................... 39 System Memory ............................40 SOM Memory ............................ 40 6.1.1 DDR4 RAM ..........................40 6.1.2 EEPROM ............................ 40 6.1.3 eMMC Flash ..........................40 6.1.4 OSPI ............................
  • Page 4 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 7.6.1 SPI Pinout ..........................66 UART ..............................67 7.7.1 UART Pinout ..........................67 USB ..............................70 7.8.1 USB Pinout ..........................70 7.8.2 USB Design In Considerations ....................71 7.8.3 USB Reference Circuits ......................72 Control Interfaces ............................. 73 Enhanced Capture ..........................

  • Page 5: List Of Figures

    Figure 6. Top Down View of Mating Connectors ......................... 16 Figure 7. Carrier Board Alignment Hole Placement ......................17 Figure 8. phyCORE-AM64xx Component Placement (processor side) ................. 18 Figure 9. phyCORE-AM64xx Component Placement (connector side) ................. 19 Figure 10. 3-Position Solder Jumper Pad Numbering Scheme ..................... 21 Figure 11.

  • Page 6: List Of Tables

    Table 5 Solder Jumper Settings ........................21 Table 6 Voltage Domain Configurations ...................... 22 Table 7 phyCORE-AM64xx Connector X1, Column A Pinout ..............25 Table 8 phyCORE-AM64xx Connector X1, Column B Pinout ..............27 Table 9 phyCORE-AM64xx Connector X1, Column C Pinout ..............28 Table 10 phyCORE-AM64xx Connector X1, Column D Pinout ..............
  • Page 7 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Table 26 phyCORE-AM64xx PRG1_RMGII1 Trace Length Characteristics ..........56 Table 27 phyCORE-AM64xx PRG1_RMGII2 Trace Length Characteristics ..........56 Table 28 phyCORE-AM64xx RMGII1 Trace Length Characteristics ............57 Table 29 phyCORE-AM64xx RMGII2 Trace Length Characteristics ............57 Table 30 FSI Connections at the phyCORE-Connector ................

  • Page 8: Som Features

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 2 SOM Features The phyCORE-AM64xx offers the following features: Insert-ready, small (50 mm x 37 mm) System on Module (SOM) subassembly in low EMI design, achieved through • advanced SMD technology • Populated with the Texas Instruments AM64xx microprocessor (17.2 x 17.2 mm, 0.8 mm pitch BGA) Single supply voltage of 5V with on-board power management IC •...

  • Page 9: Conventions, Abbreviations And Acronyms

    12.4 Product Change Management for more information. The BSP delivered with the phyCORE-AM64xx includes drivers and/or software for controlling all components such as interfaces, memory, etc. Therefore, programming close to the hardware (at the register level) is not necessary in most cases.
  • Page 10 Printed circuit board Peripheral Component Interconnect PCIe PCI express Product Change Management Product Change Notification PHYTEC Display Interface; defined to connect PHYTEC display adapter boards, or custom adapters PHYTEC Expansion Board PMIC Power management IC Power-on reset Programmable Realtime Unit...

  • Page 11: Types Of Signals

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 3.3 Types of Signals Different types of signals are brought out at the phyCORE-Connector. Table 2 below lists the abbreviations used to specify the type of a signal. Table 2 Signal Types Used in this Manual...

  • Page 12: Introduction

    The phyCORE-AM64xx is a small (50mm x 37mm) insert-ready System on Module populated with the Texas Instrument’s AM64xx microprocessor. Its universal design enables its insertion in a wide range of embedded applications. Most of the microprocessor signals and ports extend from the microprocessor to the high-density pitch (0.5 mm) connectors aligning...

  • Page 13: Block Diagram

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 4.1 Block Diagram Figure 2. phyCORE-AM64xx Block Diagram © PHYTEC America L.L.C. 2022...

  • Page 14: Physical Dimensions

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 4.2 Physical Dimensions Figure 3. phyCORE-AM64xx Dimensions Top View © PHYTEC America L.L.C. 2022...
  • Page 15 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 4. phyCORE-AM64xx Dimensions Bottom View Figure 5. phyCORE-AM64xx Dimensions End View © PHYTEC America L.L.C. 2022...

  • Page 16: Connector Alignment For Mating To Carrier Boards

    4.3 Connector Alignment for Mating to Carrier Boards The phyCORE-AM64xx has two mounting holes in the lower left and upper right corner sized for M2.5 screws/components. It is recommended to use the following mounting hardware to secure the SOM to a mating carrier board: •...
  • Page 17 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 7. Carrier Board Alignment Hole Placement © PHYTEC America L.L.C. 2022...

  • Page 18: Component Placement Diagram

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 4.4 Component Placement Diagram Figure 8. phyCORE-AM64xx Component Placement (processor side) A searchable pdf of the phyCORE-AM64xx component placement (processor side) can be found here: TBD. © PHYTEC America L.L.C. 2022...
  • Page 19 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 9. phyCORE-AM64xx Component Placement (connector side) A searchable pdf of the phyCORE-AM64xx component placement (connector side) can be found here: TBD. © PHYTEC America L.L.C. 2022...

  • Page 20: Technical And Electrical Specifications

    Connect all ground pins to ground. • Implement a power sequencing circuit to avoid driving external power to the I/O pins of the PHYCORE-AM64xx SOM before the module is fully powered up. More details on this can be found in section 5.4 Power...

  • Page 21: Solder Jumpers

    Table 5 provides a functional summary of the solder jumpers which can be changed to adapt the phyCORE-AM64xx SOM to specific design needs. It shows their default positions, possible alternative positions, type, and functions. The jumpers are a 0402 package size with a 1/16W or higher power rating.
  • Page 22 L-860e.A1 Some of the phyCORE-AM64xx power domains can be configured for 1.8V or 3.3V operation via the solder jumpers in the table above. This allows for configuring the voltage levels of the associated I/O signals under these domains to meet application requirements.
  • Page 23 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 11. Jumper Locations (Connector side) © PHYTEC America L.L.C. 2022...

  • Page 24: Pin Descriptions

    SOM's pin multiplexing options. Signal names and descriptions in the following tables 7-10, however, are regarding the specification of the phyCORE-AM64xx SOM schematic and may not line up with the functionality defined in the BSP. For information about pin multiplexing contact PHYTEC Support.

  • Page 25: Pinout Table

    Refer to section Power Sequencing for more information about preventing damage from powering up too early. 4.9 Pinout Table Table 7 phyCORE-AM64xx Connector X1, Column A Pinout X1, Column A SOM Signal Name Type Level...
  • Page 26 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 X1, Column A SOM Signal Name Type Level Processor Ball Description SD Card Detect X_MMC1_SDCD 3.3V (10K pullup) SD Write Protect X_MMC1_SDWP 3.3V (10K pullup) X_USB0_ID 3.3V USB 2.0 Dual-Role Device Role Select X_USB0_DRVVBUS 3.3V...
  • Page 27 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Table 8 phyCORE-AM64xx Connector X1, Column B Pinout X1, Column B Signal Name Type Level Processor Ball Description VDD_3V3_OUT PWR_O 3.3V VCC 3.3V Output (2A) VDD_3V3_OUT PWR_O 3.3V VCC 3.3V Output (2A) VDDSHV_SD_IO PWR_IO 3.3V...
  • Page 28 The voltage level for this signal is configurable for 1.8V or 3.3V via J5. The default voltage level is listed here, but always check the actual jumper setting for the applicable SOM configuration. Refer to section 4.7 Solder Jumpers for details More information about this signal can be found in section 5 Power Table 9 phyCORE-AM64xx Connector X1, Column C Pinout X1, Column C Signal Type Level Processor Ball...
  • Page 29 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 X1, Column C Signal Type Level Processor Ball Description GPMC Data 10 Input/Output X_GPMC0_AD10/BOOTMODE_10 3.3V (100K pullup/pulldown network) Ground GPMC Data 11 Input/Output X_GPMC0_AD11/BOOTMODE_11 3.3V (100K pullup/pulldown network) GPMC Data 12 Input/Output X_GPMC0_AD12/BOOTMODE_12 3.3V (100K pullup/pulldown network)
  • Page 30 SOM configuration. Refer to section 4.7 Solder Jumpers for details This signal should not be driven during reset. More information can be found in section System Boot Configuration Table 10 phyCORE-AM64xx Connector X1, Column D Pinout X2, Column D Signal Type Level...
  • Page 31 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 X2, Column D Signal Type Level Processor Ball Description X_SPI1_CLK 3.3V SPI Clock X_SPI1_D1 3.3V SPI Data 1 Ground X_SPI1_CS0 3.3V SPI Chip Select 0 Emulation Control 1 X_EMU1 3.3V (5.76K pullup) Emulation Control 0 X_EMU0 3.3V...

  • Page 32: Thermal Management

    AM64xx processor generates considerable heat. The phyCORE-AM64xx has a temperature rating of -40C to 85C. PHYTEC has found that a fan and a heatsink help prevent overheating at the higher end of the phyCORE-AM64xx’s temperature operating range (during our temperature testing a BDN09-6CB/A01 heatsink was attached to the SOM).

  • Page 33: Layout Guidelines

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 13. Fan design reference circuit 4.11 Layout Guidelines 4.11.1 High-Speed Differential Signal Routing Guidelines Spacing • Implement proper trace width and spacing to yield the recommended differential impedance value. • Spacing between the differential pairs and other traces should be at least twice the distance between the inter- pair spacing.

  • Page 34: General Signal Routing Guidelines

    Separate clocks and other high-speed signals as much as possible from nearby traces to reduce crosstalk. A general rule is to use a clearance of at least 3 times the trace width. 5 Power The following sub-sections discuss the power configuration of the phyCORE-AM64xx in detail. Table 12 summarizes the relationships between the voltage rails and the devices on the phyCORE-AM64xx SOM.

  • Page 35: Primary System Power (Vin)

    VIN supplied to the SOM. For proper operation, the phyCORE-AM64xx SOM must be supplied with a voltage source of 5V (±5 %) with a minimum 2A capacity at the VIN pins on the phyCORE-Connector (if you do not plan to use VDD_3V3_OUT in your custom CB design only 1A of capacity is required).
  • Page 36 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 14. Primary Power VIN(VCC_5V0_MAIN) reference circuit The primary power reference circuit is simplistic and only provides the functionality of converting an external power input (VCC_IN) into a 5V power source for the SOM (VCC_5V0_MAIN). The reference circuits below showcase additional functionality that can be added to the primary power circuit.

  • Page 37: Backup Power (Vbat)

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 A current sense amplifier that amplifies the voltage difference, making it easier to measure • Figure 16. SOM current reader reference circuit 5.2 Backup Power (VBAT) To keep the Real-Time Clock (RTC) module running, a secondary voltage source of 3V can be supplied to the phyCORE- AM64xx SOM at the VBAT pin (pin B4 of phyCORE-Connector X1).

  • Page 38: Power Sequencing

    5.4 Power Sequencing It is mandatory to avoid driving the I/O pins of the phyCORE-AM64xx SOM when the SOM is not fully powered up. Prematurely driving the pins may cause current to flow through the I/O pins before the processor is properly powered, potentially resulting in damage or unknown behavior after power-up or reset.

  • Page 39: Safe Shutdown And Sudden Power Loss

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 17. Carrier board power reference circuit 5.5 Safe Shutdown and Sudden Power Loss Like a PC, a sudden power loss can result in a corrupted filesystem that renders your system unable to boot. When possible, initiating an OS controlled shutdown procedure is advised.

  • Page 40: System Memory

    6.1.1 DDR4 RAM The RAM on the phyCORE-AM64xx is comprised of one DDR4 SDRAM chip for a 16-bit wide interface providing up to 2GB of SDRAM which can run at up to 1600MT/s. These chips are connected to the dedicated DDR subsystem of the AM64xx processor.

  • Page 41: External Memory Bus

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 6.2 External Memory Bus 6.2.1 GPMC The General-Purpose Memory Control (GPMC) module can be used as a data path to an external memory device. The GPMC can support: An asynchronous or synchronous 8-bit memory or device (non-burst device) •...
  • Page 42 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description X_PRG0_RGMII2_TX_CTL GPMC0_A10 3.3V GPMC Address 10 Output X_CPSW_RGMII1_TD0 X_PRG0_RGMII2_TXC GPMC0_A11 3.3V GPMC Address 11 Output X_PRG1_PRU1_GPO8 X_PRG0_MDIO0_MDIO GPMC0_A12 3.3V GPMC Address 12 Output X_CPSW_RGMII1_TD1 X_PRG0_MDIO0_MDC GPMC0_A13 3.3V...

  • Page 43: Sd/Mmc/Sdio

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description X_GPMC0_AD13/BOOTMODE_13 GPMC0_AD13 3.3V GPMC Data 13 Input/Output (100K pullup/pulldown network) X_GPMC0_AD14/BOOTMODE_14 GPMC0_AD14 3.3V GPMC Data 14 Input/Output (100K pullup/pulldown network) X_GPMC0_AD15/BOOTMODE_15 GPMC0_AD15 3.3V GPMC Data 15 Input/Output...
  • Page 44 SD card power should be connected to a 3.3V power supply regardless of the MMC1 IO voltage level. • SD card power needs to be toggled with on board power reset. • Table 16 phyCORE-AM64xx MMC1 Layout Characteristics Signal Name SOM Trace Length (µm) Length Matching (µm) Single Ended Impedance (Ω)

  • Page 45: System Boot Configuration

    During the power-on reset cycle, the operational system boot mode of the phyCORE-AM64xx SOM is determined by the configuration of the BOOTMODE [15:0] signals. The BOOTMODE signals must be held at the desired configuration until X_PORz_OUT goes high to be properly latched into the system.
  • Page 46 VDD_3V3_OUT (found on pins B1/B2 at the phyCORE-Connector) or 10kΩ pull-down resistors to override the SOM settings. For startup/verification testing, PHYTEC recommends designing the boot configuration circuit to include a DIP switch. This will make it easy to swap between various boot modes (an example circuit is shown below). This DIP switch can then be de-populated for production.

  • Page 47: Serial Interfaces

    The following sub-sections detail each of the serial interfaces supported on the phyCORE-AM64xx. 7.1 CAN The phyCORE-AM64xx SOM provides two Controller Area Network (MCAN) ports. Both interfaces support CAN and CAN FD (flexible data-rate) specifications, conforming with CAN protocol version 2.0 part A, B and ISO 11898-1:2015.

  • Page 48: Can Reference Circuit

    A CAN FD Transceiver to convert the MCAN0 signals into differential CAN bus signal levels • 7.2 Ethernet The phyCORE-AM64xx SOM brings out five external 10/100/1000 Mbps Ethernet ports (the AM64xx processor has six internal ethernet ports, but two share the same pins and can’t be used simultaneously, CPSW_RGMII2 and PRG1_RGMII2): •...

  • Page 49: Ethernet Pinout

    PHY if necessary. Refer to the DP83867IRRGZ datasheet for further details on these configuration and strapping options (DP83867IRRGZ Datasheet). NOTE: Adjusting strapping options and PHY registers is not necessary when using PHYTEC provided BSPs. Table 19 Ethernet PHY Default Strapping Configuration Strapping Option Default Setting Strapping Signals...
  • Page 50 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description X_PRG1_PRU1_GPO5 X_CPSW_RGMII1_RD1 RGMII1_RD1 3.3V CPSW RGMII1 Receive Data 1 X_PRG1_PRU1_GPO8 RGMII1_RD2 X_CPSW_RGMII1_RD2 3.3V CPSW RGMII1 Receive Data 2 RGMII1_RD3 X_CPSW_RGMII1_RD3 3.3V CPSW RGMII1 Receive Data 3...
  • Page 51 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description PRG1_RGMII1_RD2 X_ PRG1_RGMII1_RD2 3.3V PRG1 RGMII1 Receive Data 2 PRG1_RGMII1_RD3 X_ PRG1_RGMII1_RD3 3.3V PRG1 RGMII1 Receive Data 3 PRG1_RGMII1_TX_CTL X_ PRG1_RGMII1_TX_CTL 3.3V PRG1 RGMII1 Transmit Control...
  • Page 52 Do not use this signal if the on-board ethernet PHY is populated The phyCORE-AM64xx SOM also brings out two Industrial Ethernet Peripheral (IEP) modules that are not required for the PRG ethernet ports to function, but provide the following additional utility: Manage and generate industrial Ethernet functions •...

  • Page 53: Ethernet Design In Guide

    7.2.2 Ethernet Design In Guide 7.2.2.1 CPSW_ETH0 Ethernet Design In Considerations • Connecting the phyCORE-AM64xx SOM to an existing 10/100/1000Base-T network involves adding an RJ45 and appropriate magnetic devices in the design. See the reference circuit in section 7.2.2.3 Industrial Ethernet Peripheral for an example.
  • Page 54 RGMII v2.0 Timing Requirements (shown in the table below) specify that the clock and data will be generated simultaneously by the transmitting source, which requires a skew be introduced between clock and data. Table 23 phyCORE-AM64xx RGMII Timing Requirements Parameter...
  • Page 55 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Table 24 phyCORE-AM64xx PRG0_RMGII1 Trace Length Characteristics Signal Name SOM Trace Length (µm) Match Group Recommended Length Match PRG0_RGMII1_TXC 17196 AVERAGE_LENGTH(TXCTL, TXD0, TXD1, TXD2, TXD3) + 1.8ns 2540 µm PRG0_RGMII1_TXCTL 17659 PRG0_RGMII1_TXD0 17513 PRG0_RGMII1 Transmit...
  • Page 56 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Table 26 phyCORE-AM64xx PRG1_RMGII1 Trace Length Characteristics Signal Name SOM Trace Length (µm) Match Group Recommended Length Match PRG1_RGMII1_TXC 50733 AVERAGE_LENGTH(TXCTL, TXD0, TXD1, TXD2, TXD3) + 1.8ns 2540 µm PRG1_RGMII1_TXCTL 50810 PRG1_RGMII1_TXD0 50644 PRG1_RGMII1 Transmit...
  • Page 57 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Table 28 phyCORE-AM64xx RMGII1 Trace Length Characteristics Signal Name SOM Trace Length (µm) Match Group Recommended Length Match RGMII1_TXC 84161 AVERAGE_LENGTH(TXCTL, TXD0, TXD1, TXD2, TXD3) + 1.8ns 2540 µm RGMII1_TXCTL 84132 RGMII1_TXD0 84129 RGMII1 Transmit...

  • Page 58: Ethernet Reference Circuits

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 7.2.3 Ethernet Reference Circuits Example reference circuits for connecting the CPSW_RGMII1 differential signals from the on-board PHY to an RJ45 connector and PRG0_RGMII1 signals to an Ethernet PHY are shown below. Figure 22. RJ45 Reference Schematic The circuit consists of: •...
  • Page 59 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 © PHYTEC America L.L.C. 2022...
  • Page 60 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 © PHYTEC America L.L.C. 2022...

  • Page 61: Fsi

    Ethernet PHYs you plan to populate, this may or may not be necessary). 7.3 FSI The phyCORE-AM64xx SOM provides two Fast Serial Interface Transmitter (FSI_TX) cores and six Fast Serial Interface Receiver (FSI_RX) cores. The FSI cores can be used to communicate with an FSI-enabled device.

  • Page 62: Fsi Pinout

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 7.3.1 FSI Pinout Table 30 FSI Connections at the phyCORE-Connector Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description X_GPMC0_AD8/BOOTMODE_8 FSI_RX0_CLK 3.3V FSI Clock (100K pullup/pulldown network) X_GPMC0_AD9/BOOTMODE_9 FSI_RX0_D0 3.3V FSI Data (100K pullup/pulldown network)

  • Page 63: I 2 C

    4.7 Solder Jumpers for details 7.5 PCIe The PCI Express (PCIe) interface of the phyCORE-AM64xx SOM provides PCIe Gen. 2.0 (1-lane) functionality. Furthermore, the interface is backwards compatible to the Gen1 specification. CAUTION: PCIe shares its SERDES signals with USB 3.1 and only one can be used at a time (both systems can be populated on a custom CB as long as the SERDES signals are run through a multiplexer).

  • Page 64: Pcie Pinout

    X_SERDES0_REFCLK0_N. The external clock must be a high-quality, low-jitter differential 100MHz clock source compliant to the PCIe REFCLK AC specifications. We recommend using the PI6C557-03 clock generator, which is implemented on the PHYTEC carrier board. A PCIe reference circuit is shown in section 7.5.3 PCIe Reference Circuits.
  • Page 65 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Figure 24. PCIe Reference Schematics © PHYTEC America L.L.C. 2022...

  • Page 66: Spi

    A PCIe clock generator to generate the PCIe clock signals • 7.6 SPI The Serial Peripheral Interface (SPI) is a transmit/receive, master/slave synchronous serial bus. The phyCORE-AM64xx SOM provides access to seven SPI ports at the phyCORE-Connector. 7.6.1 SPI Pinout...

  • Page 67: Uart

    UART0 is the default console and as such PHYTEC recommends bringing out UART0 for console access. More information on using it as a debug console is provided in section 10.3...
  • Page 68 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description X_MMC1_CLK X__GPMC0_AD8/BOOTMODE_8 UART2_CTSN 3.3V UART2 Clear to Send (100K pullup/pulldown network) X_PRG0_RGMII1_RD0 X_MMC1_CMD X_GPMC0_AD2/BOOTMODE_2 UART2_RTSN 3.3V UART2 Request to Send (100K pullup/pulldown network) X_PRG0_RGMII1_RD2 X_MMC1_DAT3...
  • Page 69 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor Signal X1 Pin #(s) SOM Signal(s) Type Level Description X_PRG0_PRU0_GPO8 X_GPMC0_AD6/BOOTMODE_6 (100K pullup/pulldown network) X_MCAN0_TX UART4_RXD 3.3V UART4 Receive Data X_MMC1_CLK X_PRG0_RGMII2_TD0 X_PRG0_RGMII1_TD0 X_PRG0_PRU0_GPO7 X_MCAN0_RX X_MMC1_CMD UART4_TXD 3.3V UART4 Transmit Data X_GPMC0_AD7/BOOTMODE_7 (100K pullup/pulldown network)

  • Page 70: Usb

    This signal should not be driven during reset. More information can be found in section 6.3 System Boot Configuration 7.8 USB The phyCORE-AM64xx SOM provides one USB3.1-Gen1 Dual-Role Device (DRD) Subsystem (USB0) that provides the following functionality: • Can be used as a USB 2.0 port that supports USB 2.0 on-the-go functionality Can be used as a USB 3.1 port and is compliant with USB 3.1 Gen1 and xHCI 1.1 specification...

  • Page 71: Usb Design In Considerations

    X_USB0_DP/X_USB0_DM trace lengths should be matched and should be no more than 12 inches in total length (SOM + Carrier Board), though 4 inches is considered typical. The table below shows the length of the USB2.0 traces on the SOM and required constraints. Table 38 phyCORE-AM64xx USB0 Layout Characteristics Signal Name Length (µm)

  • Page 72: Usb Reference Circuits

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Table 39 phyCORE-AM64xx SERDES0 Layout Characteristics Signal Name Length (µm) Length Single Ended Differential Matching Impedance (Ω) Impedance (Ω) Max Total Max CB (µm) Trace Trace X_SERDES0_TX0_N 4692 101600 96908 X_SERDES0_TX0_P 4680 101600 96920 X_SERDES0_RX0_N...

  • Page 73: Control Interfaces

    Two TVS diode arrays and two common mode filters (CMF) for ESD and EMI considerations A two port USB 3.1 connector • 8 Control Interfaces The following sub-sections detail each of the control interfaces supported on the phyCORE-AM64xx. 8.1 Enhanced Capture The phyCORE-AM64xx SOM brings out 3x Enhanced Capture (ECAP) modules. 8.1.1 ECAP Pinout...

  • Page 74: Enhanced Pulse-Width Modulation

    Do not use this signal if the on-board ethernet PHY is populated 8.2 Enhanced Pulse-Width Modulation The phyCORE-AM64xx SOM supports up to nine Enhanced Pulse-Width Modulation (PWM) modules. Each PWM provides the following functionality: • A dedicated 16-bit time-base counter with period and frequency control.

  • Page 75: Epwm Pinout

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 8.2.1 EPWM Pinout Table 41 EPWM Connections at the phyCORE-Connector Processor X1 Pin #(s) SOM Signal(s) Type Level Description Signal EHRPWM_SOCA X_MCAN1_TX 3.3V EHRPWM Start of Conversion A EHRPWM_SOCB X_MCAN1_RX 3.3V EHRPWM Start of Conversion B...

  • Page 76: Enhanced Quadrature Encoder Pulse

    This signal should not be driven during reset. More information can be found in section 6.3 System Boot Configuration 8.3 Enhanced Quadrature Encoder Pulse The phyCORE-AM64xx SOM brings out 3x Enhanced Quadrature Encoder Pulse (EQEP) modules. 8.3.1 EQEP Pinout Table 42 EQEP Connections at the phyCORE-Connector...

  • Page 77: Peripheral Interfaces

    The following sub-sections detail each of the peripheral interfaces supported on the phyCORE-AM64xx. 9.1 ADC The phyCORE-AM64xx SOM brings out 8x ADC inputs from the 12-bit, 8 channel ADC module on the processor. The reference voltage is connected directly to 1.8V on the module.

  • Page 78: Cpts

    4.7 Solder Jumpers for details 9.2 CPTS The phyCORE-AM64xx SOM brings out the Common Platform Time Sync (CPTS) module that is used to facilitate host control of time sync operations. 9.2.1 CPTS Pinout Table 44 CPTS Connections at the phyCORE-Connector...

  • Page 79: Gpio

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 The voltage level for this signal is configurable for 1.8V or 3.3V. The default voltage level is listed here, but always check the actual jumper setting for the applicable SOM configuration. Refer to section 4.7 Solder Jumpers for details 9.3 GPIO...

  • Page 80: Gpio Pinout

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 9.3.1 GPIO Pinout Table 46 GPIO0 Accessibility at phyCORE-Connector Processor X1 Pin #(s) SOM Signal(s) Type Level Internal SOM Usage Signal 100K pullup/pulldown network GPIO0_15 X_GPMC0_AD0/BOOTMODE_0 3.3V Do not drive during reset 100K pullup/pulldown network...
  • Page 81 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor X1 Pin #(s) SOM Signal(s) Type Level Internal SOM Usage Signal GPIO0_47 X_PRG1_RGMII1_RD2 3.3V None GPIO0_48 X_PRG1_RGMII1_RD3 3.3V None GPIO0_49 X_PRG1_RGMII1_RX_CTL 3.3V None GPIO0_50 X_PRG1_PRU0_GPO5 3.3V None GPIO0_51 X_PRG1_RGMII1_RXC 3.3V None GPIO0_52 X_PRG1_PRU0_GPO7 3.3V...
  • Page 82 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Table 47 GPIO1 Accessibility at phyCORE-Connector Processor X1 Pin #(s) SOM Signal(s) Type Level Internal SOM Usage Signal GPIO1_0 X_PRG0_RGMII1_RD0 3.3V None GPIO1_1 X_PRG0_RGMII1_RD1 3.3V None GPIO1_2 X_PRG0_RGMII1_RD2 3.3V None GPIO1_3 X_PRG0_RGMII1_RD3 3.3V None GPIO1_4 X_PRG0_RGMII1_RX_CTL 3.3V...
  • Page 83 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor X1 Pin #(s) SOM Signal(s) Type Level Internal SOM Usage Signal GPIO1_45 X_SPI0_D0 3.3V None GPIO1_46 X_SPI0_D1 3.3V None GPIO1_47 X_SPI1_CS0 3.3V None GPIO1_48 X_SPI1_CS1 3.3V None GPIO1_49 X_SPI1_CLK 3.3V None GPIO1_50 X_SPI1_D0 3.3V...
  • Page 84 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 Processor X1 Pin #(s) SOM Signal(s) Type Level Internal SOM Usage Signal MCU_GPIO0_4 X_MCU_SPI0_D1 3.3V None MCU_GPIO0_5 X_MCU_SPI1_CS0 3.3V None MCU_GPIO0_7 X_MCU_SPI1_CLK 3.3V None MCU_GPIO0_8 X_MCU_SPI1_D0 3.3V None MCU_GPIO0_9 X_MCU_SPI1_D1 3.3V None MCU_GPIO0_10 X_MCU_SPI0_D0 3.3V...
  • Page 85 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 The voltage level for this signal is configurable for 1.8V or 3.3V. The default voltage level is listed here, but always check the actual jumper setting for the applicable SOM configuration. Refer to section 4.7 Solder Jumpers...

  • Page 86: Timer

    SOM configuration. Refer to section 4.7 Solder Jumpers for details 9.4 TIMER The phyCORE-AM64xx SOM brings out 16x Timer modules. The modules have a 32-bit data bus width and provide interrupts generated on overflow, compare, and capture. 9.4.1 Timer Pinout Table 53 Timer Signals...

  • Page 87: Debug Interfaces

    The following sub-sections detail each of the debug interfaces supported on the phyCORE-AM64xx. 10.1 JTAG The phyCORE-AM64xx SOM is equipped with a JTAG interface for downloading program code into the internal RAM or for debugging programs currently executing. The JTAG interface is accessible via the phyCORE-Connector and provides seven standard IEEE1149.6 JTAG signals.

  • Page 88: Jtag Pinout

    Connectors and Pinout. Figure 28. JTAG Reference Schematic 10.2 TRACE (TRC) The phyCORE-AM64xx SOM is equipped with a TRACE (TRC) module that can be used to record operation of the ROM code and debug unexpected occurrences. © PHYTEC America L.L.C. 2022...

  • Page 89: Trc Pinout

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 10.2.1 TRC Pinout Table 55 TRC Connections at the phyCORE-Connector rocessor X1 Pin #( SOM Signal( Type Level Description Signal X_GPMC0_AD0/BOOTMODE_0 TRC_CLK 3.3V Trace Clock (100K pullup/pulldown network) X_GPMC0_AD1/BOOTMODE_1 TRC_CTL 3.3V Trace Control (100K pullup/pulldown network)

  • Page 90: Uart0

    L-860e.A1 10.3 UART0 The phyCORE-AM64xx SOM can also be communicated with using UART0 for downloading program code into the internal RAM or for debugging programs currently executing. UART0 is the default console and as such PHYTEC recommends bringing out UART0 for console access. The UART0 interface is accessible via the phyCORE-Connector.
  • Page 91 PCM-072/phyCORE-AM64xx System on Module L-860e.A1 The circuit consists of: Four buffers to isolate the UART signals from the bridge until reset is finished • A dual UART to USB bridge to convert the UART signals into USB signals • A TVS diode array for ESD protection •...

  • Page 92: System Interfaces

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 11 System Interfaces The following sub-sections detail the signals brought out to the phyCORE connectors from the MAIN and MCU interfaces of the AM64xx processor. 11.1 MAIN Pinout Table 57 MAIN Connections at the phyCORE-Connector...

  • Page 93: Integrating And Handling The Phycore-Am64Xx

    Minimum Requirements for Operation can be used as a starting point for integrating the phyCORE-AM64xx SOM into target circuitry. Additional information is available to facilitate the integration of the phyCORE-AM64xx SOM into customer applications, such as: phyCORE-AM64xx SOM and Carrier Board Schematic...

  • Page 94: Product Change Management

    Instead, PHYTEC manages this at the SOM-level. PHYTEC ensures continued availability of pin- and function-compatible SOMs and SBCs, further minimizing maintenance costs and risks. This pro- active product lifecycle management (PLM) policy has enabled deployment of the same PHYTEC SOM in designs for over twenty years.

  • Page 95: Additional Information

    PHYTEC System on Modules (SOM) and Single Board Computers (SBC) are designed as subcomponents for integration in electrical devices. Combined with PHYTEC Carrier Boards, PHYTEC SOMs can be used as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.
  • Page 96 - are reserved. No reproduction may occur without the express written consent from PHYTEC. The information in this document has been carefully checked and is as reliable as possible. However, PHYTEC assumes no responsibility for any inaccuracies. PHYTEC neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product.

  • Page 97: Revision History

    PCM-072/phyCORE-AM64xx System on Module L-860e.A1 14 Revision History Table 59 Document Revision History Version Date Changes in this Manual Number 2022/06/02 L-860e.A0 Preliminary Release Fixed a typo in Table 17, changing BOOTMODE[6:3] to BOOTMODE[9:3] and added a clarification to 5.4 Power 2022/10/26 L-860e.A1...

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