Related Manuals for Phytec phyCORE-i.MX7
Summary of Contents for Phytec phyCORE-i.MX7
- Page 1 ® phyCORE -i.MX 7 Hardware Manual Document No.: L-821e_4 SOM Prod. No.: PCM-061 SOM PCB. No.: 1458.3 Edition: May 2018 A product of a PHYTEC Technology Holding company...
- Page 2 Additionally, PHYTEC America L.L.C. offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC America L.L.C. further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.
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Page 3: Table Of Contents
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Table of Contents Table of Contents ................................3 List of Figures ..................................5 List of Tables ..................................6 Conventions, Abbreviations and Acronyms ........................7 Preface ....................................9 Introduction ................................12 Block Diagram ..............................14 Component Placement Diagram ........................15 Pin Description ................................ - Page 4 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Technical Specifications ............................40 Hints for Integrating and Handling the phyCORE-i.MX7 ..................42 12.1 Integrating the phyCORE-i.MX7 ........................42 12.2 Handling the phyCORE-i.MX7 ........................... 42 Revision History..............................43 © PHYTEC America L.L.C. 2018...
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Page 5: List Of Figures
List of Figures Figure 1. phyCORE-i.MX7 Block Diagram ..........................14 Figure 2. phyCORE-i.MX7 Component Placement (top view) ....................15 Figure 3. phyCORE-i.MX7 Component Placement (bottom view) ..................16 Figure 4. Pinout of the phyCORE-Connector (top view, with cross section insert) ............. 18 Figure 5. -
Page 6: List Of Tables
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 List of Tables Table 1. Abbreviations and Acronyms used in this Manual ....................8 Table 2. Types of Signals ................................ 8 Table 3. phyCORE-Connector (X1, X2) Pin-Out Description ....................19 Table 4. Jumper Descriptions and Settings ........................... 26 Table 5. -
Page 7: Conventions, Abbreviations And Acronyms
L-821e_4 Conventions, Abbreviations and Acronyms This hardware manual describes the PCM-061 System on Module, also referred to as phyCORE-i.MX7. The manual specifies the phyCORE-i.MX7's design and function. Precise specifications for the NXP i.MX7 microcontrollers can be found in NXP's i.MX7 Data Sheet and Technical Reference Manual. -
Page 8: Table 1. Abbreviations And Acronyms Used In This Manual
Power-on reset Real-time clock Surface mount technology System on Module - Used in reference to the PCM-061 / phyCORE-i.MX7 System on Module VBAT SOM standby voltage input Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify each type of signal. -
Page 9: Preface
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Preface This phyCORE-i.MX7 Hardware Manual describes the System on Module's design and functions. Precise specifications for the NXP i.MX7 processor can be found in the processor datasheet and/or technical reference manual (TRM). Ordering Information The part numbering of the phyCORE-i.MX7 has the following structure This structure shows the ordering options available as of the printing of this manual. - Page 10 The phyCORE-i.MX7 is one of a series of PHYTEC System on Modules that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports a variety of 8-/16- and 32-bit controllers in two ways: 1.
- Page 11 In addition to our HW and SW offerings, the buyer will receive a free obsolescence maintenance service for the HW provided when purchasing a PHYTEC SOM. Our Product Change Management Team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts which are being used in our products.
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Page 12: Introduction
The phyCORE-i.MX7 is a subminiature (41 mm x 50 mm) insert-ready System on Module populated with the NXP i.MX7 microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch (0.5 mm) connectors aligning two sides of the board, allowing... - Page 13 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 • 6x UART • 2x eCSPI • 3x SDIO/SD/MMC • 2x CAN • PCI Express 2.0 (1 Lane) • MIPI CSI (2 Lane) • MIPI DSI (2 Lane) • 4x ADC • 3x Tamper •...
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Page 14: Block Diagram
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Block Diagram Figure 1. phyCORE-i.MX7 Block Diagram © PHYTEC America L.L.C. 2018... -
Page 15: Component Placement Diagram
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Component Placement Diagram Figure 2. phyCORE-i.MX7 Component Placement (top view) Detailed component placement diagrams with all reference designators are available through our website © PHYTEC America L.L.C. 2018... -
Page 16: Figure 3. Phycore-I.mx7 Component Placement (Bottom View)
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Figure 3. phyCORE-i.MX7 Component Placement (bottom view) © PHYTEC America L.L.C. 2018... -
Page 17: Pin Description
Carrier Board/user target circuitry. The lower right-hand corner of the numbered matrix (pin A1) is thus covered with the corner of the phyCORE-i.MX7 marked with a triangle. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module. -
Page 18: Figure 4. Pinout Of The Phycore-Connector (Top View, With Cross Section Insert)
Signal names and descriptions in Table 3, however, are in regard to the specification of the phyCORE-i.MX7 and the functions defined therein. Please refer to the i.MX7 datasheet, or the schematic to learn about alternative functions. In order to utilize a specific pin's alternative function the corresponding registers must be configured within the appropriate driver of the BSP. -
Page 19: Table 3. Phycore-Connector (X1, X2) Pin-Out Description
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Table 3. phyCORE-Connector (X1, X2) Pin-Out Description X1, Column A Pin # Signal Type Level Description X_I2C1_SCL 3.3V I²C bus 1 clock X_I2C1_SDA 3.3V I²C bus 1 data X_I2C2_SCL 3.3V I²C bus 2 clock X_I2C2_SDA 3.3V... - Page 20 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 X1, Column A Pin # Signal Type Level Description X_SD1_CD_B 3.3V SD/MMC1 Card Detect X_SD1_WP 3.3V SD/MMC1 Write Protect X_SD1_CLK 3.3V SD/MMC1 Clock X_SD1_CMD 3.3V SD/MMC1 Command Ground X_SD1_DATA0 3.3V SD/MMC1 Data 0 X_SD1_DATA1 3.3V...
- Page 21 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 X1, Column B Pin # Signal Type Level Description X_PCIE_REFCLK_N DIFF100 PCIe Differential Negative Reference Clock Ground X_NAND_WP_B 3.3V NAND Wait Polarity X_SD2_CD_B 1.8V/3.3V SD/MMC2 Card Detect X_SD2_WP 1.8V/3.3V SD/MMC2 Write Protect X_SD2_RESET_B 1.8V/3.3V SD/MMC2 Reset...
- Page 22 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 X2, Column A Pin # Signal Type Level Description Ground X_LCD1_DATA21_BOOT21 3.3V LCD1 Display Data 21 / BOOT 21 Signal X_LCD1_DATA14_BOOT14 3.3V LCD1 Display Data 14 / BOOT 14 Signal X_LCD1_ENABLE 3.3V LCD1 Display Enable X_LCD1_DATA12_BOOT12 3.3V...
- Page 23 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 X2, Column A Pin # Signal Type Level Description Ground X_RGMII2_TX0 3.3V RGMII2 Transmit Data 0 X_RGMII2_TX1 3.3V RGMII2 Transmit Data 1 X_RGMII2_TX2 3.3V RGMII2 Transmit Data 2 X_RGMII2_TX3 3.3V RGMII2 Transmit Data 3 Ground X_MDIO_D 3.3V...
- Page 24 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 X2, Column B Pin # Signal Type Level Description X_MIPI_CSI_D1_N DIFF100 CSI Differential Data 1 Negative X_MIPI_CSI_D1_P DIFF100 CSI Differential Data 1 Positive Ground X_USB_H_DATA 3.3V USB HSIC Data Signal X_USB_H_STROBE 3.3V USB HSIC Strobe Signal...
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Page 25: Jumpers
Table 4 below represent the default configuration for each jumper. The table also describes the function of each jumper as well as each alternative position. Note that each solder jumper on the phyCORE-i.MX7 should be populated with a 0-ohm 0402 resistor. -
Page 26: Table 4. Jumper Descriptions And Settings
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Table 4. Jumper Descriptions and Settings Jumper Setting Description J1 - J12 Open Route RGMII1 signals only to the Ethernet PHY. Closed Route RGMII1 signals out to the phyCORE connector. SPI1 and UART7 operate at 1.8V. -
Page 27: Power
The following sections of this chapter describe the power design of the phyCORE-i.MX7 in further detail. Primary System Power (VCC_SOM) The phyCORE-i.MX7 operates from a voltage supply with a nominal value of +3.3V. The PMIC and On-board switching regulators generate the voltage supplies required by the i.MX7 processor and on-board components from the 3.3V supplied to the SOM. -
Page 28: Power Management Ic (U2)
Power Management IC (U2) The phyCORE-i.MX7 provides an on-board Power Management IC (PMIC), NXP PF3000, at position U2 to generate the voltages required by the processor and on-board components. -
Page 29: Table 5. External Supply Voltages
PMIC, which then generates other voltage rails on the SOM. A load switch IC at U13 is used to generate the 3.3V rails used on the phyCORE-i.MX7 (VLDO3_3V3, NVCC_3V3, and 3V3MEM_IN) from VCC_SOM. This load switch is enabled by the PMIC to ensure proper power sequencing for all on-board supplies. - Page 30 PCM-061/phyCORE-i.MX7 System on Module L-821e_4 sequencing power before the release of POR. It is recommended to use this power sequencing for configuring the boot signals on a carrier board (as these are strapped at the release of POR) and supplying memory devices (i.e. SD card).
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Page 31: Real-Time Clock (Rtc)
Real-Time Clock (RTC) There are two options for an RTC on the phyCORE-i.MX7: the on-chip RTC or an external on-board RTC. If cost is the primary concern, then the on-chip RTC should be considered to minimize external components. However, if power is the primary concern, then consider using the external RTC to reduce power consumption. -
Page 32: System Configuration And Booting
Serial Downloader Internal Boot Reserved for NXP use Boot Device Selection Table 9 describes the external boot devices that are supported by the phyCORE-i.MX7. By default, the boot device is set to SD. Table 9. Boot Device Selection BOOT_CFG[15:12] Boot Device... -
Page 33: Boot Device Configuration
L-821e_4 Boot Device Configuration Table 10 shows the default boot configuration selected by the phyCORE-i.MX7 default boot strapping. For detailed information regarding all supported boot device configurations, please refer to the NXP i.MX7 Technical Reference Manual. Table 10. SD/MMC Boot Configuration Description... -
Page 34: System Memory
NOTE: The phyCORE-i.MX7 does not support the use of eMMC and NAND flash storage at the same time. Only one of the storage devices can be populated on the SOM at any given time. Additional NAND or eMMC devices need to be implemented on the Carrier Board. -
Page 35: Qspi Nor Flash Memory (U9)
L-821e_4 QSPI NOR Flash Memory (U9) The phyCORE-i.MX7 can be populated with a SPI Flash memory device via the QSPI_A bus as an ordering option. This would be suitable for applications which require a small code footprint or small RTOS. -
Page 36: Sd/Mmc Card Interfaces
L-821e_4 SD/MMC Card Interfaces The phyCORE-i.MX7 provides three SD/MMC interfaces: SD/MMC1-3. SD/MMC1 and SD/MMC2 are provided at the phyCORE connector directly from the processor. These two ports allow support for external SD/MMC devices, such as an SD card or a WiFi/Blueooth module, and are provided with 22 Ohm source termination resistors on the SOM. The SD/MMC3 interface is used to interface with an on-board flash device, either eMMC at U5 or NAND at U6 depending on the SOM configuration (see Section 7.2). -
Page 37: Serial Interfaces
The phyCORE-i.MX7 provides two USB 2.0 OTG interfaces with integrated USB PHYs. Typically, an external USB connector is all that is needed for USB functionality. However, USB power switch circuits can be implemented on a baseboard to add additional VBUS enable and over-current detection functionality. -
Page 38: I 2 C
PCI Express The phyCORE-i.MX7 provides a single lane PCI Express Gen 2.0 interface with an integrated PHY supporting a data rate up to 5Gbps. The PCIe reference clock into the processor is provided by an external 100MHz oscillator circuit with HCSL termination. -
Page 39: Debug Interface
L-821e_4 Debug Interface The phyCORE-i.MX7 is equipped with a JTAG interface for downloading program code into the internal RAM or for debugging programs currently executing. The JTAG interface is accessible via the phyCORE-Connectors. Please reference the NXP documentation for further information regarding the JTAG interface. -
Page 40: Technical Specifications
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Technical Specifications The physical dimensions of the phyCORE-i.MX7 are represented in Figure 7. The module’s profile is approximately 5.4 mm thick from the tallest component on the top to the tallest component on the bottom (excluding the phyCORE connectors). -
Page 41: Table 12. Technical Specifications
The mass is calculated by averaging the measurements of 4x PCM-061.A4 units using a digital scale Temperature range will depend on the processor ordered with the PHYTEC SOM; the minimum temperature will be limited to 0C if using the MCIMX7D7DVK10SC, which is rated for 0C to +95C The VBAT rail should never exceed the VCC_SOM supply ©... -
Page 42: Hints For Integrating And Handling The Phycore-I.mx7
12.1 Integrating the phyCORE-i.MX7 Successful integration of the phyCORE-i.MX7 SOM into target circuitry greatly depends on adherence to the layout design rules for the GND connections of the phyCORE module. As a general design rule, we recommend connecting all GND pins neighboring signals which are being used in application circuitry. -
Page 43: Revision History
PCM-061/phyCORE-i.MX7 System on Module L-821e_4 Revision History Table 14. Revision History Date Version Number Changes in this Manual 2016/06/03 L-821e_0 Preliminary Release 2017/01/13 L-821e_1 Revised explanation of X_3V3MEM_IN and X_3V3MEM_EN. Added 3V3MEM_EN to Power Diagram (Figure 6). Updated pin description for the X_nWDOG_RST soft reset signal.