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Phytec phyCORE-P8xC51Mx2 Hardware Manual

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phyCORE-P8xC51Mx2
Hardware Manual
Edition April 2005
A product of a PHYTEC Technology Holding company

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Summary of Contents for Phytec phyCORE-P8xC51Mx2

  • Page 1 Hardware Manual Edition April 2005 A product of a PHYTEC Technology Holding company...
  • Page 2 PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages which might result.

  • Page 3: Table Of Contents

    Contents Preface ......................1 Introduction ..................3 1.1 Blockdiagram................6 1.2 View of the phyCORE-P8xC51Mx2 ..........6 Pin Description..................7 Jumpers ....................13 3.1 J1 Internal or External Program Memory ........16 3.2 J2, J3 Pin 1 and Pin 23 on U1............16 3.3 J4 PLD Control ................17 3.4 J5, J6 RAM Selection ..............17...
  • Page 4 The phyCORE-P8xC51Mx2 on the phyCORE Development Board LD 5V ........... 43 14.1 Concept of the phyCORE Development Board LD 5V ..... 43 14.2 Development Board LD 5V Connectors and Jumpers ....45 14.2.1 Connectors..............45 14.2.2 Jumpers on the phyCORE Development Board LD 5V......
  • Page 5 Index of Figures Figure 1: Block Diagram................6 Figure 2: View of the phyCORE-P8xC51Mx2 ..........6 Figure 3: Pinout of the phyCORE-P8xC51Mx2 (Top View) ......7 Figure 4: Numbered Matrix Overview of the phyCORE-Connector (Viewed from Above)..............9 Figure 5: Numbering of the Jumper Pads...........13 Figure 6: Location of the Jumpers (Top View)..........13...
  • Page 6 Table 16: Control Register 1 of the Address Decoder........ 25 Table 17: Control Register 2 of the Address Decoder........ 28 Table 18: EEPROM Memory Options and Addressing......33 Table 19: Improper Jumper Settings for the Development Board....48 © PHYTEC Messtechnik GmbH 2005 L-602e_3...
  • Page 7 Plug P2B ..................61 Table 34: JP17 Configuration of the Programmable LED D3....62 Table 35: Pin Assignment Data/Address Bus for the phyCORE-P8xC51Mx2 / Development Board / Expansion Board.................65 Table 36: Pin Assignment Control Signals for the phyCORE-P8xC51Mx2 / Development Board / Expansion Board.................66...
  • Page 8 Table 39: Unused Pins on the phyCORE-P8xC51Mx2 / Development Board / Expansion Board ........68 Table 40: JP19 Jumper Configuration for Silicon Serial Number Chip..69 © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 9: Preface

    Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments. Note: PHYTEC products lacking protective enclosures are subject to dam- age by Electro Static Discharge (ESD) and, hence, may only be unpacked, handled or operated in environments in which sufficient precautionary measures have been taken in respect to ESD dangers.
  • Page 10 The phyCORE-P8xC51Mx2 is one of a series of PHYTEC Single Board Computers (SBCs) that can be populated with different controllers and, hence, offers various functions and configurations.

  • Page 11: Introduction

    Introduction 1 Introduction The phyCORE-P8xC51Mx2 belongs to PHYTEC’s phyCORE Single Board Computer (SBC) module family. The phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all core elements of a...
  • Page 12 The phyCORE-P8xC51Mx2 is a subminiature (55 x 51 mm) insert-ready Single Board Computer populated with Philips P8xC51Mx2 microcontroller family featuring extended memory addressing. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to standard-width (2.54 mm / 0.1 in.) pin...
  • Page 13 Introduction The phyCORE-P8xC51Mx2 offers the following features: • subminiature Single Board Computer (55 x 51 mm) achieved through advanced SMD technology • populated with the Philips P8xC51Mx2 microcontroller (PLCC-44 packaging) featuring extended memory addressing • instruction cycle time of 500 ns at 12 MHz clock speed (standard) •...

  • Page 14: Blockdiagram

    S u p e r v i s o r 0.5/1KB This feature is under development and is not available yet. Figure 1: Block Diagram 1.2 View of the phyCORE-P8xC51Mx2 Figure 2: View of the phyCORE-P8xC51Mx2 © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 15: Pin Description

    As Figure 3 indicates, all controller signals extend to standard-width (2.54 mm / 0.10 in.) pin rows lining two sides the board (referred to as phyCORE-connector). This allows the phyCORE-P8xC51Mx2 to be plugged into any target application like a "big chip".
  • Page 16 Lettering of the pin connector rows progresses alphabetically from left to right (refer to Figure 4). The numbered matrix can be aligned with the phyCORE-P8xC51Mx2 (viewed from above; phyCORE-connector header pins pointing down) or with the socket of the phyCORE Development Board LD 5V / target circuitry.

  • Page 17: Figure 4: Numbered Matrix Overview Of The Phycore-Connector

    Pin Description The following figure (see Figure 4) illustrates the numbered matrix system. It shows a phyCORE-P8xC51Mx2 mounted on a phyCORE Development Board LD 5V. The shaded area of the phyCORE- connectors shown below indicates the remaining pins not used in...
  • Page 18 17B, 18B Address Latch Enable output µC Address line from address latch 1 (A1) A8A16, Address bus /upper address lines from µC A13A21 Multiplexed address/data line from µC Address line from address latch 2 (A17) © PHYTEC MMesstechnikGmbH 2005 L-602e_3...
  • Page 19 WDI input of the Reset controller Boot = 1 during Reset → starts the Boot BOOT sequence Port pins µC P1.0, P1.1, P1.3, 10D, P1.6 (SCL), P3.0 (RxD) Port pins µC 12D, P4.0 P4.1 C clock output © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 20: Table 1: Pinout Of The Phycore-Connector X1

    Differential B signal of the RS-485 transceiver or TxD1 output of the RS-232 transceiver TxD0 Transmit output of the RS-232 transceiver RxD0 Receive input of the RS-232 transceiver /INTRTC Interrupt output RTC Table 1: Pinout of the phyCORE-Connector X1 © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 21: Jumpers

    Jumpers 3 Jumpers For configuration purposes, the phyCORE-P8xC51Mx2 has 20 solder jumpers, some of which have been installed prior to delivery. Figure 5 illustrates the numbering of the jumper pads, while Figure 6 and Figure 7 indicate the location of the jumpers on the board. With the exception of Jumper J18 all solder jumpers (Jxx) are located on the top side of the phyCORE-P8xC51Mx2.

  • Page 22: Figure 7: Location Of The Jumpers (Bottom View)

    Figure 7: Location of the Jumpers (Bottom View) © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 23: Table 2: Jumper Settings Overview

    SDA used for remote boot function Table 2: Jumper Settings Overview The EEPROM at U12 is not supported in the current revision of the phyCORE-P8xC51Mx2 (1199.0). These jumpers are reserved for future versions of the module. © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 24: J1 Internal Or External Program Memory

    VCC and GND connection. Closing both Jumpers J2 and J3 connects the controller pins to the applicable potential on the module, hence improves the EMI characteristics of the phyCORE-P8xC51Mx2. On controllers with different pin functions these jumpers must remain open.

  • Page 25: J4 Pld Control

    3.4 J5, J6 RAM Selection Both standard RAM types or high-speed devices can populate the phyCORE-P8xC51Mx2 at U5 and U6. If high-speed RAMs are used, Jumpers J5 and J6 disable the delay of the /CS signal that controls the memory device. With Jumpers J5 and J6 closed no battery buffer for RAM is possible.

  • Page 26: J7 Sram Supply Voltage

    P3.0 and P3.1 - Serial Interface J8, J9 closed * P3.0 and P3.1 as RS-232 P3.0 and P3.1 as port pins open *= Default setting Table 8: J8, J9 Port P3.0 and P3.1 / 1 Serial Interface Configuration © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 27: J10, J11 P4.0 And P4.1 As 2 Nd Serial Interface

    Pins X1F13 and X1E14 as RS-232 Pins X1F13 and X1E14 as RS-485 2 + 3 2 + 3 Pins X1F13, X1E14 not connected open open *= Default setting Table 10: J12, J13 X1F13 and X1E14 Configuration © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 28: J14 Rs-485 Interface Control

    *= Default setting Table 12: J15, J18 EEPROM Configuration The EEPROM at U12 is not supported in the current revision of the phyCORE-P8xC51Mx2 (1199.0). These jumpers are reserved for future versions of the module. © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 29: J16, J17 Configuration Of P1.6 And P1.7 For I 2 C Bus

    *= Default setting Table 14: J19 RTC Interrupt Configuration The EEPROM at U12 is not supported in the current revision of the phyCORE-P8xC51Mx2 (1199.0). These jumpers are reserved for future versions of the module. © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 30: J20 Remote Download Source

    RS-232 / RS-485 – RxD1 2 + 3 *= Default setting Table 15: J20 Remote Download Source Configuration ___________________ The Remote Supervisor IC is under development. Hence Jumper J20 has no function at this time © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 31: Memory Models

    Memory Models 4 Memory Models The phyCORE-P8xC51Mx2 allows for flexible address decoding which can be configured by software to different memory models. A hardware reset activates a default memory configuration that is suitable for a variety of applications. However, this memory model can be changed or adjusted at the beginning of a particular application.

  • Page 32: Figure 8: Default Memory Model Following A Hardware Reset

    The following figure illustrates the default memory model: Figure 8: Default Memory Model following a Hardware Reset The following sections describe the address decoder’s registers for configuration of the memory model. © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 33: Control Register 1

    CODE memory space starting at address 0. When starting the runtime model this bit is erased. The FlashTools firmware is pre-installed in the external Flash device upon delivery of the module. © PHYTEC Messtechnik GmbH 2005 L-602e_3...
  • Page 34 RAM-SW: Two SRAM devices of 128 kByte capacity each can populate the phyCORE-P8xC51Mx2. Setting the RAM-SW bit allows mapping of the second RAM’s address space (/CSRAM2) into range 02:0000h - 03:FFFFh. If the bit is erased then the address...

  • Page 35: Figure 9: Von Neumann Memory Model

    Memory Models Figure 9: Von Neumann Memory Model © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 36: Control Register 2

    XDATA memory space within the appropriate address range. The fourth block is reserved for internal access to the decoder’s internal register (write-only access). This block is not available for use of connecting external devices. N/A: Not Accessible © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 37: Figure 10: Configuration Of The I/O Area

    00:FC00H - 00:FC01H (IO-SW = 0). The rest of the /CS-REG block remains unused and is reserved for future expansion. _________________ Firmware portion of the utility program for on-board Flash programming and is pre-installed in the Flash at time of delivery. © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 38: Serial Interfaces

    Serial Interfaces 5.1 RS-232 Interface An RS-232 transceiver is located on the phyCORE-P8xC51Mx2 at U9. This device adjusts the signal levels of the P3.0/RxD0, P3.1/TxD0, P4.0/RxD1 and P4.1/TxD1 lines. The RS-232 interface enables connection of the module to a COM port on a host-PC. In this instance, the RxD0 line (X1F15) of the transceiver is connected to the TxD line of the COM port;...

  • Page 39: Flash Memory (U7)

    Flash, as non-volatile memory on the phyCORE-P8xC51Mx2, provides an easily reprogrammable means of code storage to the user. The phyCORE-P8xC51Mx2 can be populated at U7 by a single Flash device of type 29F200 with 256 kByte, a 29F400 with 512 kByte, a 29F800 with 1 Mbyte or device type 29F160 with 2 MB.
  • Page 40 Flash (such as into von Neumann RAM). This usually equals the interruption of a "normal" program execution cycle. As of the printing of this manual, Flash devices generally have a life expectancy of at least 100,000 erase/program cycles. © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 41: Serial Eeprom (U12)

    These jumpers are reserved for future versions of the module. ____________________ The EEPROM at U12 is not supported in the current revision of the phyCORE-P8xC51Mx2 (1199.0). These jumpers are reserved for future versions of the module. © PHYTEC Messtechnik GmbH 2005...

  • Page 42: Real-Time Clock Rtc-8563/64 (U13)

    • automatic word address incrementing • programmable alarm, timer and interrupt functions If the phyCORE-P8xC51Mx2 is equipped with a battery, the Real-Time Clock runs independently of the module’s power supply. Programming of the Real-Time Clock is done via the I C bus at address 1010001(0)/0xA2, connected to port P1.6 (SCL) and port...

  • Page 43: Reset Controller (U8)

    PFI. If VBAT = 3.3 V, a voltage of 1.65 V is available at PFI. If the voltage at PFI drops below 1.25 V, the signal /PFO is released. The signals WDI and /PFO are available at the phyCORE-connector pins X1D5 and X1F5. © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 44: Remote Supervisory Chip (U10)

    Space U10 is intended to be populated by an RSC1308 Remote Supervisory Chip. This IC can initiate a boot sequence via a serial interface, such as RS-232 or RS-485. The RSC can start PHYTEC FlashTools without requiring a manual reset of the phyCORE module via a Boot jumper or button.

  • Page 45: Battery Buffer

    The VBAT input (pin X1D4) is provided for connecting the external battery. The negative polarity pin on the battery must connect to GND on the phyCORE-P8xC51Mx2. As of the printing of this manual, a lithium battery is recommended as it offers relatively high capacity at low discharge.
  • Page 46 © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 47: Technical Specifications

    Technical Specifications 12 Technical Specifications The physical dimensions of the phyCORE-P8xC51Mx2 are represented in Figure 11. The module’s profile is approximately 11 mm thick, with a maximum component height of 3.5 mm on the back-side of the PCB and approximately 6 mm on the front-side. The PCB itself is approximately 1.5 mm thick.
  • Page 48 138 ns These specifications describe the standard configuration of the phyCORE-P8xC51Mx2 as of the printing of this manual. Please note that the module storage temperature is only 0°C to +70°C if a battery buffer is used for the RAM devices.

  • Page 49: Hints For Handling The Module

    Carefully heat neighboring connections in pairs. After a few alternations, components can be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the bonds. © PHYTEC Messtechnik GmbH 2005 L-602e_3...
  • Page 50 © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 51: The Phycore-P8Xc51Mx2 On The Phycore Development Board Ld 5V

    The phyCORE-P8xC51Mx2 on the Development Board LD 5V The phyCORE-P8xC51Mx2 on the phyCORE Development Board LD 5V PHYTEC Development Boards are fully equipped with all mechanical and electrical components necessary for the speedy and secure start- up and subsequent communication to and programming of applicable PHYTEC Single Board Computer (SBC) modules.

  • Page 52: Figure 12: Modular Development And Expansion Board Concept With The Phycore-P8Xc51Mx2

    • As the physical layout of the expansion bus is standardized across all applicable PHYTEC Development Boards, PHYTEC is able to offer various expansion boards (5) that attach to the Development Board at the expansion bus connectors. These modular expansion...

  • Page 53: Development Board Ld 5V Connectors And Jumpers

    The phyCORE-P8xC51Mx2 on the Development Board LD 5V 14.2 Development Board LD 5V Connectors and Jumpers 14.2.1 Connectors As shown in Figure 13, the following connectors are available on the phyCORE Development Board LD 5V: low-voltage socket for power supply connectivity...

  • Page 54: Jumpers On The Phycore Development Board Ld 5V

    14.2.2 Jumpers on the phyCORE Development Board LD 5V Peripheral components of the phyCORE Development Board LD 5V can be connected to the signals of the phyCORE-P8xC51Mx2 by setting the applicable jumpers. The Development Board’s peripheral components are configured for use with the phyCORE-P8xC51Mx2 by means of insertable jumpers.

  • Page 55: Figure 15: Location Of The Jumpers (View Of The Component Side)

    The phyCORE-P8xC51Mx2 on the Development Board LD 5V Figure 15: Location of the Jumpers (View of the Component Side) Figure 16 shows the factory default jumper settings for operation of the phyCORE Development Board LD 5V with the standard phyCORE-P8xC51Mx2 (standard = P8xC51Mx2 controller, use of the first and second RS-232 interface, LED D3, the Boot button on the Development Board).

  • Page 56: Unsupported Features And Improper Jumper Settings

    The phyCORE Development Board LD 5V supports two main supply voltages for the start-up of various phyCORE modules. When using the phyCORE-P8xC51Mx2, only one main supply voltage is required, VCC1 with 5V. The connector pins for a second supply voltage on the phyCORE-P8xC51Mx2 are not defined.

  • Page 57: Functional Components On The Phycore Development Board Ld 5V

    (3.3 V version of the module) Table 20: JP9 Configuration of the Main Supply Voltage VCCI If the phyCORE-P8xC51Mx2 is purchased in a Rapid Development Kit, an appropriate 5V power adapter is included. © PHYTEC Messtechnik GmbH 2005 L-602e_3...

  • Page 58: Figure 17: Connecting The Supply Voltage At X1

    Setting Description 1 + 2 3,3 V as main supply voltage for the phyCORE-P8xC51Mx2 (if 5 V version of the module is used) 2 + 3 5 V as main supply voltage for the phyCORE-P8xC51Mx2 (if 3.3 V version of the...

  • Page 59: Starting Flashtools

    PC allows for on-board Flash programming with application programs via an RS-232 interface. In order to start FlashTools on the phyCORE-P8xC51Mx2, the Boot pin (X1D6) of the phyCORE module must be connected to a high- level signal at the time the Reset signal changes from its active to the inactive state.
  • Page 60 2. The Boot input of the phyCORE-P8xC51Mx2 can also be perma- nently connected to VCC. This spares pushing the Boot button during a hardware reset or power-on. Jumper Setting Description JP28 2 + 4 Boot input connected permanently with VCC.

  • Page 61: First Serial Interface At Socket P1A

    The phyCORE-P8xC51Mx2 on the Development Board LD 5V 14.3.3 First Serial Interface at Socket P1A Socket P1A is the lower socket of the double DB-9 connector at P1. P1A is connected via jumpers to the first serial interface of the phyCORE-P8xC51Mx2.

  • Page 62: Power Supply To External Devices Via Socket P1A

    P1A. This power supply option especially supports connectivity to analog and digital modems. Such modem devices enable global communication of the phyCORE-P8xC51Mx2 over the Internet or a direct dial connection. On all PHYTEC Rapid Development Kits mounted with a phyCORE module featuring Philips...
  • Page 63 The phyCORE-P8xC51Mx2 on the Development Board LD 5V The components at U11 and U12 guarantee electronic protection against overvoltage and excessive current draw at pin 6 of P1A; in particular: • Load detection and controlled voltage supply switch-on: In order to ensure clear detection of the switch-on condition, the connected device should cause a current draw of at least 10 mA at pin 6.

  • Page 64: Socket P1B

    Jumper Setting Description closed Pin 2 of P1B connected with RS-232 interface signal TxD1 of the phyCORE-P8xC51Mx2 open Pin 2 of the DB-9 socket P1B not connected open Pin 9 of the DB-9 socket P1B not connected open Pin 7 of the DB-9 socket P1B not connected...
  • Page 65 The phyCORE-P8xC51Mx2 on the Development Board LD 5V Caution: When using the phyCORE-P8xC51Mx2 mounted on a phyCORE Development Board LD 5V the following jumper settings are not functional and could damage the module: Jumper Setting Description closed Pin 7 of the DB-9 socket P1B is connected to SCL (I²C) of the phyCORE-P8xC51Mx2...

  • Page 66: Plug P2A

    CAN interface this plug can be used to connect the CAN signals from the CAN bus to the module. The phyCORE-P8xC51Mx2 does not support a CAN interface. Plug P2A remains unused.
  • Page 67 The phyCORE-P8xC51Mx2 on the Development Board LD 5V Caution: When using the phyCORE-P8xC51Mx2 mounted on a phyCORE Development Board LD 5V the following jumper settings are not functional and could damage the module: Jumper Setting Description JP31 1 + 2...

  • Page 68: Rs-485 Interface At Plug P2B

    RS-485 interface signals phyCORE-P8xC51Mx2 via jumpers. The RS-485 interface is an alternative function of the serial interface signals on the P8xC51Mx2 controller. The default configuration of the phyCORE-P8xC51Mx2 activates the RS-232 interface. In order to enable the RS-485 signals, different jumper settings on the phyCORE-P8xC51Mx2 are required (refer to sections 3.7, 3.8 and 3.9 for details).
  • Page 69 The phyCORE-P8xC51Mx2 on the Development Board LD 5V Caution: When using the DB-9 plug P2B as RS-485 interface the following jumper settings are not functional and could damage the module: Jumper Setting Description JP33 2 + 3 Pin 2 of DB-9 plug P2B connected with CAN-L1 signal...

  • Page 70: Programmable Led D3

    LED at D3 for user implementations. This LED can be connected to a port pin at GPIO0 (JP17 = 1+2) or the data bus via a latch at U14 (JP17 = 2+3). When using the phyCORE-P8xC51Mx2, the factory default configuration enables control of LED D3 using port pin P1.0 (GPIO0).

  • Page 71: Pin Assignment Summary Of The Phycore, The Expansion Bus And The Patch Field

    14.1, signals from phyCORE-P8xC51Mx2 extend in a strict 1:1 assignment to the expansion bus connector X2 on the Development Board. These signals, in turn, are routed in a similar manner to the patch field on an optional expansion board that mounts to the Development Board at X2.

  • Page 72: Figure 23: Pin Assignment Scheme Of The Expansion Bus

    Figure 23: Pin Assignment Scheme of the Expansion Bus A B C D E F Figure 24: Pin Assignment Scheme of the Patch Field © PHYTEC MMesstechnikGmbH 2005 L-602e_3...
  • Page 73 The phyCORE-P8xC51Mx2 on the Development Board LD 5V The pin assignment on the phyCORE-P8xC51Mx2, in conjunction with the expansion bus (X2) on the Development Board and the patch field on an expansion board, is as follows: Signal phyCORE-P8xC51Mx2 Expansion Bus Patch Field P0.0/ AD0...
  • Page 74 ClkOut P3.2 / INT0 P3.3/ /INT1 P3.4/ T0 P3.5/ T1 /CS1 /CS2 /CS3 Table 36: Pin Assignment Control Signals for the phyCORE-P8xC51Mx2 / Development Board / Expansion Board Signal phyCORE-P8xC51Mx2 Expansion Bus Patch Field /RESET /RESIN /WDI BOOT P1.0 / T2 P1.1 / T2EX...
  • Page 75 The phyCORE-P8xC51Mx2 on the Development Board LD 5V Signal phyCORE-P8xC51Mx2 Expansion Bus Patch Field 1D, 1E 1C, 2C, 1D, 2D 1A, 1C 4D, 5D 1D, 2C VBAT 2B, 3B, 5B, 7B, 8B, 2A, 7A, 12A, 3C, 4C, 7C, 8C, 10B, 12B, 13B,...

  • Page 76: Battery Connector Bat1

    The mounting space BAT1 (see PCB stencil) is provided for connection of a battery that buffers volatile memory devices (SRAM) and the RTC on the phyCORE-P8xC51Mx2. The Reset controller on the phyCORE-P8xC51Mx2 is responsible for switching from a normal power supply to a back-up battery. This optional battery required for this function (refer to section 11) is available through PHYTEC (order code BL-003).

  • Page 77: Ds2401 Silicon Serial Number

    Development Board LD 5V can be connected to a port pin at GPIO1 (JP19 1+2) or the data bus via latch U14 and driver U15 (JP19 = 2+3). When using the phyCORE-P8xC51Mx2, the factory default configuration enables access to the Silicon Serial Number using port pin P1.1 (GPIO1).

  • Page 78: Pin Header Connector X4

    1 and provides the phyCORE Development Board LD 5V GND potential at pin 2. The maximum current draw depends on the power adapter used. We recommend the use of modems with less than 250 mA current draw. © PHYTEC MMesstechnikGmbH 2005 L-602e_3...

  • Page 79: Index

    J3 ..........16 EEPROM Configuration ...21 J4 ..........17 EMC ..........1 J5 ..........17 Expansion Bus......72 J6 ..........17 J7 ..........18 J8 ..........18 Features ........5 J9 ..........18 First Serial Interface....61 JP17 ...........71 Flash Memory......36 JP19 ...........79 Jumper Configuration....53 © PHYTEC Messtechnik GmbH 2005 L-602e_3...
  • Page 80 Devices via Socket P1A ..62 U12..........38 PRG-EN ........27 U13..........39 U7..........36 U8..........41 RAM-SW ........28 U9..........33 Real-Time Clock ....... 39 Remote Download ....23 Remote Supervisory Chip ..42 VBAT........43 Reset Button......53 VN-EN ........28 © PHYTEC MMesstechnikGmbH 2005 L-602e_3...
  • Page 81 How would you improve this manual? Did you find any mistakes in this manual? page Submitted by: Customer number: Name: Company: Address: Return to: PHYTEC Technologie Holding AG Postfach 100403 D-55135 Mainz, Germany Fax : +49 (6131) 9221-33 © PHYTEC Messtechnik GmbH 2005 L-602e_3...
  • Page 82 Published by © PHYTEC Messtechnik GmbH 2005 Ordering No. L-602e_3 Printed in Germany...

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