Infineon PSoC 4000T Manuals

Manuals and User Guides for Infineon PSoC 4000T. We have 1 Infineon PSoC 4000T manual available for free PDF download: Reference Manual

Infineon PSoC 4000T Reference Manual (210 pages)

MCU architecture

Brand: Infineon | Category: Microcontrollers | Size: 3 MB

About this Document
1
Scope and Purpose
1
Intended Audience
1
Table of Contents
2
Section A: Overview
8
Introduction
9
Top Level Architecture
9
Features
10
CPU System
11
Processor
11
Interrupt Controller
11
Memory
11
System-Wide Resources
11
Clocking System
11
Power System
12
Gpio
12
Watchdog Timers
12
Timer/Counter/Pwm Block
12
Serial Communication Blocks
12
Special Function Peripherals
13
Capsense
13
Program and Debug
13
Device Feature Summary
13
Getting Started
14
Development Ecosystem
14
Psoc™ 4 MCU Resources
14
Modustoolbox™ Software
15
Document Construction
16
Major Sections
16
Documentation Conventions
16
Register Conventions
16
Numeric Naming
16
Units of Measure
17
Acronyms
18
Section B: CPU System
22
Top Level Architecture
22
Cortex®-M0+ CPU
23
Features
23
Block Diagram
23
How It Works
24
Address Map
24
Registers
24
Operating Modes
26
Instruction Set
27
Address Alignment
29
Memory Endianness
29
Systick Timer
29
Debug
29
Interrupts
30
Features
30
How It Works
30
Interrupts and Exceptions - Operation
31
Interrupt/Exception Handling
31
Level and Pulse Interrupts
32
Exception Vector Table
33
Exception Sources
34
Reset Exception
34
Non-Maskable Interrupt (NMI) Exception
34
Hardfault Exception
34
Supervisor Call (Svcall) Exception
35
Pendsv Exception
35
Systick Exception
35
Interrupt Sources
36
Exception Priority
36
Enabling and Disabling Interrupts
37
Exception States
38
Pending Exceptions
38
Stack Usage for Exceptions
39
Interrupts and Low-Power Modes
39
Exceptions - Initialization and Configuration
40
Registers
40
Associated Documents
40
Device Security
41
Features
41
How It Works
42
Device Security
42
Flash Security
42
Section C: System Resources Subsystem (SRSS)
43
Top Level Architecture
43
O System
44
Features
44
GPIO Interface Overview
44
I/O Cell Architecture
45
Digital Input Buffer
46
Digital Output Driver
46
Drive Mode
47
Slew Rate Control
48
High-Speed I/O Matrix
49
Behavior in Low-Power Modes
50
Interrupt
50
Peripheral Connections
52
Firmware Controlled GPIO
52
Capsense
52
Serial Communication Block (SCB)
53
Timer, Counter, and Pulse Width Modulator (TCPWM) Block
53
Registers
53
Clocking System
54
Block Diagram
54
Clock Sources
55
Internal Main Oscillator (IMO)
55
Startup Behavior
56
Internal Low-Speed Oscillator (ILO)
57
External Clock (EXTCLK)
57
Clock Distribution
57
High-Frequency Clock (HFCLK) Input Selection
57
Low-Frequency (LFCLK) Input Selection
57
System Clock (SYSCLK) Prescaler Configuration
57
Peripheral Clock Divider Configuration
58
Low-Power Mode Operation
60
Register List
60
Power Supply and Monitoring
61
Block Diagram
61
Power Supply Scenarios
62
Single 2 V to 5.5 V Regulated Supply
62
Direct 1.71 V to 1.89 V Supply
63
How It Works
63
Regulator Summary
63
Voltage Monitoring
64
Power-On Reset (POR)
64
Register List
64
Power Modes
65
Active Mode
66
Sleep Mode
66
Deep Sleep Mode
67
Power Mode Summary
67
Low-Power Mode Entry and Exit
68
Register List
68
Chip Operational Modes
69
Boot
69
User
69
Privileged
69
Debug
69
Watchdog Timer (WDT)
70
Features
70
Block Diagram
70
How It Works
70
Enabling and Disabling WDT
71
WDT Interrupts and Low-Power Modes
71
WDT Reset Mode
72
Register List
72
Trigger Multiplexer Block
73
Features
73
Architecture
73
Trigger Multiplexer Group
74
Software Triggers
75
Register List
75
Reset System
76
Reset Sources
76
Power-On Reset
76
Brownout Reset
76
Watchdog Reset
76
Software Initiated Reset
76
External Reset
77
Protection Fault Reset
77
Identifying Reset Sources
77
Register List
77
Section D: Digital System
78
Top Level Architecture
78
Serial Communications Block (SCB)
79
Features
79
Architecture
79
Buffer Modes
79
FIFO Mode
79
Clocking Modes
80
Serial Peripheral Interface (SPI)
81
Features
81
General Description
82
SPI Modes of Operation
83
SPI Buffer Modes
88
FIFO Mode
88
Clocking and Oversampling
91
Clock Modes
91
Enabling and Initializing SPI
95
I/O Pad Connection
96
SPI Master
96
Drive Mode
96
SPI Slave
97
SPI Registers
98
Register Name
98
Operation
98
Uart
99
Features
99
General Description
100
UART Modes of Operation
100
Standard Protocol
100
Clocking and Oversampling
111
Enabling and Initializing the UART
112
I/O Pad Connection
112
Smartcard Mode
113
LIN Mode
113
Irda Mode
114
UART Registers
114
Inter Integrated Circuit (I2C)
115
Features
115
General Description
115
External Electrical Connections
116
Terms and Definitions
117
Clock Stretching
117
Bus Arbitration
118
I2C Modes of Operation
118
Read Transfer
119
I2C Buffer Modes
120
Clocking and Oversampling
123
Enabling and Initializing the I2C
127
I/O Pad Connections
128
I2C Registers
129
SCB Interrupts
130
SPI Interrupts
132
UART Interrupts
135
I2C Interrupts
138
Timer, Counter, and PWM (TCPWM)
140
Features
140
Architecture
140
Enabling and Disabling Counters in a TCPWM Block
141
Clocking
141
Trigger Inputs
142
Trigger Outputs
145
Interrupts
145
Interrupt Registers
145
PWM Outputs
146
Power Modes
146
Operation Modes
147
Counting Modes
147
Timer Mode
148
Capture Mode
154
Quadrature Decoder Mode
157
Pulse Width Modulation Mode
162
Supported Features
163
Trigger Output
164
Pulse Width Modulation with Dead Time Mode
173
Pulse Width Modulation Pseudo-Random Mode (PWM_PR)
175
TCPWM Registers
179
Section E: Analog System
180
Capsense
181
Section F: Program and Debug
182
Program and Debug Interface
183
Features
183
Functional Description
183
Serial Wire Debug (SWD) Interface
184
SWD Timing Details
185
ACK Details
186
Turnaround (Trn) Period Details
186
Cortex®-M0+ Debug and Access Port (DAP)
186
Debug Port (DP) Registers
187
Access Port (AP) Registers
187
Programming the Psoc™ 4 Device
188
SWD Port Acquisition
188
SWD Programming Mode Entry
189
SWD Programming Routines Executions
189
Psoc™ 4 SWD Debug Interface
189
Debug Control and Configuration Registers
189
Breakpoint Unit (BPU)
190
Data Watchpoint (DWT)
190
Debugging the Psoc™ 4 Device
190
Registers
191
Nonvolatile Memory Programming
192
Features
192
Functional Description
192
System Call Implementation
193
Blocking and Non-Blocking System Calls
193
Performing a System Call
194
System Calls
195
Silicon ID
196
Configure Clock
196
Load Flash Bytes
197
Write Row
198
Program Row
199
Erase All
200
Checksum
201
Write Protection
202
Non-Blocking Write Row
203
Non-Blocking Program Row
204
Resume Non-Blocking
205
System Call Status
206
Non-Blocking System Call Pseudo Code
207
Revision History
209

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