Functional Description - Analog Devices AD9833 Manual

Numerically Controlled Oscillator Plus Phase Modulator
This consists of two frequency select registers, a phase accumu-
lator, two phase offset registers, and a phase offset adder. The
main component of the NCO is a 28-bit phase accumulator.
Continuous time signals have a phase range of 0 to 2. Outside
this range of numbers, the sinusoid functions repeat themselves
in a periodic manner. The digital implementation is no different.
The accumulator simply scales the range of phase numbers into
a multibit digital word. The phase accumulator in the AD9833 is
implemented with 28 bits. Therefore, in the AD9833, 2 = 2
Likewise, the Phase term is scaled into this range of numbers
0 < Phase < 2 – 1. With these substitutions, the previous
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equation becomes
f =  Phase ¥ f
where 0 < Phase < 2 – 1.
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The input to the phase accumulator can be selected either from
the FREQ0 register or FREQ1 register, and is controlled by
the FSELECT bit. NCOs inherently generate continuous phase
signals, thus avoiding any output discontinuity when switching
between frequencies.
Following the NCO, a phase offset can be added to perform phase
modulation using the 12-bit phase registers. The contents of
one of these phase registers is added to the most significant bits
of the NCO. The AD9833 has two phase registers; their resolu-
tion is 2/4096.
SIN ROM
To make the output from the NCO useful, it must be converted
from phase information into a sinusoidal value. Since phase infor-
mation maps directly into amplitude, the SIN ROM uses the digital
phase information as an address to a look-up table and converts
the phase information into amplitude. Although the NCO contains
a 28-bit phase accumulator, the output of the NCO is truncated
to 12 bits. Using the full resolution of the phase accumulator is
impractical and unnecessary, as this would require a look-up
table of 2 entries. It is necessary only to have sufficient phase
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resolution such that the errors due to truncation are smaller than
the resolution of the 10-bit DAC. This requires that the SIN ROM
have two bits of phase resolution more than the 10-bit DAC.
The SIN ROM is enabled using the MODE bit (D1) in the
control register. This is explained further in Table XI.
Digital-to-Analog Converter
The AD9833 includes a high impedance current source 10-bit
DAC. The DAC receives the digital words from the SIN ROM
and converts them into the corresponding analog voltages.
The DAC is configured for single-ended operation. An external
load resistor is not required since the device has a 200 W resis-
tor on board. The DAC generates an output voltage of typically
0.6 V p-p.
REV. A
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MCLK
Regulator
VDD provides the power supply required for the analog section
and the digital section of the AD9833. This supply can have a
value of 2.3 V to 5.5 V.
The internal digital section of the AD9833 is operated at 2.5 V.
An on-board regulator steps down the voltage applied at VDD
to 2.5 V. When the applied voltage at the VDD pin of the AD9833
is equal to or less than 2.7 V, the CAP/2.5 V and VDD pins
should be tied together, thus bypassing the on-board regulator.
.

FUNCTIONAL DESCRIPTION

Serial Interface
The AD9833 has a standard 3-wire serial interface that is com-
patible with SPI , QSPI
®
standards.
Data is loaded into the device as a 16-bit word under the control
of a serial clock input, SCLK. The timing diagram for this opera-
tion is given in Figure 3.
The FSYNC input is a level triggered input that acts as a frame
synchronization and chip enable. Data can be transferred into
the device only when FSYNC is low. To start the serial data
transfer, FSYNC should be taken low, observing the minimum
FSYNC to SCLK falling edge setup time, t . After FSYNC goes
low, serial data will be shifted into the device's input shift register
on the falling edges of SCLK for 16 clock pulses. FSYNC may
be taken high after the 16th falling edge of SCLK, observing
the minimum SCLK falling edge to FSYNC rising edge time, t .
Alternatively, FSYNC can be kept low for a multiple of 16 SCLK
pulses and then brought high at the end of the data transfer. In
this way, a continuous stream of 16-bit words can be loaded while
FSYNC is held low, FSYNC only going high after the 16th SCLK
falling edge of the last word loaded.
The SCLK can be continuous, or alternatively the SCLK can
idle high or low between write operations but must be high
when FSYNC goes low (t ).
Powering Up the AD9833
The flow chart in Figure 7 shows the operating routine for the
AD9833. When the AD9833 is powered up, the part should be
reset. This will reset appropriate internal registers to zero to pro-
vide an analog output of midscale. To avoid spurious DAC outputs
while the AD9833 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
RESET does not reset the phase, frequency, or control registers.
These registers will contain invalid data, and therefore should be
set to a known value by the user. The RESET bit should then
be set to 0 to begin generating an output. The data will appear
on the DAC output eight MCLK cycles after RESET is set to 0.
Latency
Associated with each asynchronous write operation in the AD9833
is a latency. If a selected frequency/phase register is loaded with
a new word, there is a delay of seven to eight MCLK cycles before
the analog output will change. (There is an uncertainty of one
MCLK cycle, as it depends on the position of the MCLK rising
edge when the data is loaded into the destination register.)
–9–
AD9833
, MICROWIRE , and DSP interface
™ ™
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