Pin Configuration - Analog Devices AD9833 Manual

Pin Number
Power Supply
2
3
4
9
Analog Signal and Reference
1
10
Digital Interface and Control
5
6
7
8
REV. A

PIN CONFIGURATION

COMP
1
VDD
2
CAP/2.5V
3
(Not to Scale)
DGND
4
MCLK
5
PIN FUNCTION DESCRIPTIONS
Mnemonic Function
VDD Positive Power Supply for the Analog and the Digital Interface Sections. The
on-board 2.5 V regulator is also supplied from VDD. VDD can have a value
from 2.3 V to 5.5 V. A 0.1 mF and a 10 mF decoupling capacitor should be
connected between VDD and AGND.
CAP/2.5 V The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated
from VDD using an on-board regulator (when VDD exceeds 2.7 V). The
regulator requires a decoupling capacitor of typically 100 nF, which is connected
from CAP/2.5 V to DGND. If VDD is equal to or less than 2.7 V, CAP/2.5 V
should be tied directly to VDD.
DGND Digital Ground.
AGND Analog Ground.
COMP A DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
VOUT Voltage Output. The analog and digital output from the AD9833 is available at
this pin. An external load resistor is not required because the device has a
200 W resistor on board.
MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction
of the frequency of MCLK. The output frequency accuracy and phase noise
are determined by this clock.
SDATA Serial Data Input. The 16-bit serial data-word is applied to this input.
SCLK Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge.
FSYNC Active Low Control Input. This is the frame synchronization signal for the input
data. When FSYNC is taken low, the internal logic is informed that a new word is
being loaded into the device.
VOUT
10
AGND
AD9833 9
FSYNC
8
TOP VIEW
SCLK
7
SDATA
6
–5–
AD9833