Analog Devices AD9833 Manual page 15

WRITE A FULL 28-BIT WORD
TO A FREQUENCY REGISTER?
(CONTROL REGISTER WRITE)
WRITE TWO CONSECUTIVE
(SEE TABLE V FOR EXAMPLE)
WRITE ANOTHER FULL
YES
FREQUENCY REGISTER?
INTERFACING TO MICROPROCESSORS
The AD9833 has a standard serial interface that allows the part to
interface directly with several microprocessors. The device uses
an external serial clock to write the data/control information
into the device. The serial clock can have a frequency of 40 MHz
maximum. The serial clock can be continuous, or it can idle high
or low between write operations. When data/control information
is being written to the AD9833, FSYNC is taken low and is held
low while the 16 bits of data are being written into the AD9833.
The FSYNC signal frames the 16 bits of information being loaded
into the AD9833.
AD9833 to ADSP-21xx Interface
Figure 10 shows the serial interface between the AD9833 and
the ADSP-21xx. The ADSP-21xx should be set up to operate in
the SPORT transmit alternate framing mode (TFSW = 1). The
ADSP-21xx is programmed through the SPORT control register
and should be configured as follows:
• Internal clock operation (ISCLK = 1)
• Active low framing (INVTFS = 1)
• 16-bit word length (SLEN = 15)
• Internal frame sync signal (ITFS = 1)
• Generate a frame sync for each write (TFSR = 1)
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. The data is clocked out on
each rising edge of the serial clock and clocked into the AD9833
on the SCLK falling edge.
REV. A
DATA WRITE
NO
TO A FREQUENCY REGISTER?
YES
B28 (D13) = 1
16-BIT WORDS
28-BIT WORD TO A
NO
Figure 9. Data Writes
WRITE 14 MSBs OR LSBs
NO
YES
(CONTROL REGISTER WRITE)
B28 (D13) = 0
HLB (D12) = 0/1
WRITE A 16-BIT WORD
(SEE TABLES VI AND VII
FOR EXAMPLES)
WRITE 14MSBs OR LSBs
TO A
FREQUENCY REGISTER?
YES
NO
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 10. ADSP-2101/ADSP-2103 to AD9833 Interface
AD9833 to 68HC11/68L11 Interface
Figure 11 shows the serial interface between the AD9833 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting bit MSTR in the SPCR to 1.
This provides a serial clock on SCK while the MOSI output drives
the serial data line SDATA. Since the microcontroller does not
have a dedicated frame sync pin, the FSYNC signal is derived from
a port line (PC7). The setup conditions for correct operation of
the interface are as follows:
• SCK idles high between write operations (CPOL = 0)
• Data is valid on the SCK falling edge (CPHA = 1)
When data is being transmitted to the AD9833, the FSYNC line is
taken low (PC7). Serial data from the 68HC11/68L11 is transmit-
ted in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. In order to load
data into the AD9833, PC7 is held low after the first 8 bits are
transferred, and a second serial write operation is performed to
the AD9833. Only after the second 8 bits have been transferred
should FSYNC be taken high again.
–15–
AD9833
WRITE TO PHASE
REGISTER?
YES
(16-BIT WRITE)
D15, D14 = 11
D13 = 0/1 (CHOOSE THE
PHASE REGISTER)
D12 = X
D11 ... D0 = PHASE DATA
WRITE TO ANOTHER
PHASE REGISTER?
YES
NO
AD9833*
FSYNC
TFS
SDATA
DT
SCLK SCLK