Analog Devices AD9833 Manual

Low power 20 mw 2.3v to 5.5v programmable waveform generator

Hide thumbs

Table Of Contents

Quick Links

Download this manual

FEATURES

Digitally Programmable Frequency and Phase

20 mW Power Consumption at 3 V

0 MHz to 12.5 MHz Output Frequency Range

28-Bit Resolution (0.1 Hz @ 25 MHz Ref Clock)

Sinusoidal/Triangular/Square Wave Outputs

2.3 V to 5.5 V Power Supply

No External Components Required

3-Wire SPI Interface

Extended Temperature Range: –40C to +105C

Power-Down Option

10-Lead MSOP Package

APPLICATIONS

Frequency Stimulus/Waveform Generation

Liquid and Gas Flow Measurement

Sensory Applications—Proximity, Motion, and Defect

Detection

Line Loss/Attenuation

Test and Medical Equipment

Sweep/Clock Generators

TDR

AGND

MCLK

FREQ0 REG

FREQ1 REG

SERIAL INTERFACE

CONTROL LOGIC

FSYNC

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use,norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

FUNCTIONAL BLOCK DIAGRAM

DGND

VDD

CAP/2.5V

REGULATOR

AVDD/

DVDD

2.5V

PHASE

MUX

ACCUMULATOR

(28-BIT)

PHASE0 REG

MUX

PHASE1 REG

CONTROL REGISTER

AND

SCLK

SDATA

Low Power 20 mW 2.3 V to 5.5 V

Programmable Waveform Generator

GENERAL DESCRIPTION

The AD9833 is a low power programmable waveform generator

capable of producing sine, triangular, and square wave outputs.

Waveform generation is required in various types of sensing,

actuation, and time domain reflectometry applications. The output

frequency and phase are software programmable, allowing easy

tuning. No external components are needed. The frequency regis-

ters are 28 bits; with a 25 MHz clock rate, resolution of 0.1 Hz

can be achieved. Similarly, with a 1 MHz clock rate, the AD9833

can be tuned to 0.004 Hz resolution.

The AD9833 is written to via a 3-wire serial interface. This serial

interface operates at clock rates up to 40 MHz and is compatible

with DSP and microcontroller standards. The device operates

with a power supply from 2.3 V to 5.5 V.

The AD9833 has a power-down function (SLEEP). This allows

sections of the device that are not being used to be powered down,

thus minimizing the current consumption of the part, e.g., the DAC

can be powered down when a clock output is being generated.

The AD9833 is available in a 10-lead MSOP package.

ON-BOARD

REFERENCE

SIN



ROM

DIVIDE

MUX

BY 2

AD9833

FULL-SCALE

CONTROL

MUX

10-BIT DAC

MSB

200

COMP

VOUT

Table of Contents

Need help?

Do you have a question about the AD9833 and is the answer not in the manual?

Questions and answers

Summary of Contents for Analog Devices AD9833

Page 1 No External Components Required ters are 28 bits; with a 25 MHz clock rate, resolution of 0.1 Hz 3-Wire SPI Interface can be achieved. Similarly, with a 1 MHz clock rate, the AD9833 ® Extended Temperature Range: –40C to +105C can be tuned to 0.004 Hz resolution.
Page 2 AD9833–SPECIFICATIONS (VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, T = T to T , R = 6.8 k for VOUT, unless otherwise noted.) Parameter Unit Test Conditions/Comments SIGNAL DAC SPECIFICATIONS Resolution Bits Update Rate MSPS 0.65...
Page 3: Timing Characteristics
AD9833 TIMING CHARACTERISTICS (VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.) Parameter Limit at T to T Unit Test Conditions/Comments ns min MCLK Period ns min MCLK High Duration ns min MCLK Low Duration...
Page 4: Absolute Maximum Ratings
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9833 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges.
Page 5: Pin Configuration
Serial Data Input. The 16-bit serial data-word is applied to this input. SCLK Serial Clock Input. Data is clocked into the AD9833 on each falling SCLK edge. FSYNC Active Low Control Input. This is the frame synchronization signal for the input data.
Page 6 AD9833–Typical Performance Characteristics –60 T = 25C AVDD = 3V T = 25C T = 25C –65 –70 –75 SFDR dB MCLK/7 SFDR dB MCLK/50 –80 –85 –90 100k (Hz) MCLK (MHz) MCLK FREQUENCY (MHz) TPC 1. Typical Current Consumption TPC 2.
Page 7 AD9833 –10 –10 –10 –20 –20 –20 –30 –30 –30 –40 –40 –40 –50 –50 –50 –60 –60 –60 –70 –70 –70 –80 –80 –80 –90 –90 –90 –100 –100 –100 100k RWB 100 VWB 30 ST 100 SEC RWB 1K...
Page 8: Theory Of Operation
Total Harmonic Distortion 1/ f the reference period Total harmonic distortion (THD) is the ratio of the rms sum of MCLK harmonics to the rms value of the fundamental. For the AD9833, = DPhase ¥ / 2p MCLK THD is defined as The AD9833 builds the output based on this simple equation.
Page 9: Functional Description
An on-board regulator steps down the voltage applied at VDD in a periodic manner. The digital implementation is no different. to 2.5 V. When the applied voltage at the VDD pin of the AD9833 The accumulator simply scales the range of phase numbers into is equal to or less than 2.7 V, the CAP/2.5 V and VDD pins...
Page 10: Control Bits
14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The control bit D12 (HLB) informs the AD9833 whether the bits to be altered are the 14 MSBs or 14 LSBs.
Page 11 Function SLEEP12 SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9833 is used to output the MSB of the DAC data. SLEEP12 = 0 implies that the DAC is active. This function is explained further in Table X.
Page 12: Reset Bit
RESET does not reset contain the 14 LSBs, while the second write will contain the 14 MSBs. the phase, frequency, or control registers. When the AD9833 is For this mode of operation, the control bit B28 (D13) should powered up, the part should be reset.
Page 13: Grounding And Layout
GROUNDING AND LAYOUT The SIN ROM can be bypassed so that the truncated digital output The printed circuit board that houses the AD9833 should be from the NCO is sent to the DAC. In this case, the output is no designed so that the analog and digital sections are separated longer sinusoidal.
Page 14 FROM SIN TO RAMP? CHANGE OUTPUT TO CONTROL REGISTER A DIGITAL SIGNAL? WRITE (SEE TABLE XI) Figure 7. Flow Chart for AD9833 Initialization and Operation INITIALIZATION APPLY RESET (CONTROL REGISTER WRITE) RESET = 1 WRITE TO FREQUENCY AND PHASE REGISTERS FREQ0 REG = F ...
Page 15 Data is transmitted MSB first. In order to load each rising edge of the serial clock and clocked into the AD9833 data into the AD9833, PC7 is held low after the first 8 bits are on the SCLK falling edge.
Page 16 8-bit bytes, thus only eight falling SCLK edges tion board. occur in each cycle. To load the remaining 8 bits to the AD9833, The DDS evaluation kit includes a populated, tested AD9833 P3.3 is held low after the first 8 bits have been transmitted, and a printed circuit board.
Page 17 AD9833 SCLK SDATA 10F FSYNC DVDD 0.1F DVDD 0.1F 0.1F DVDD 10F 0.1F 0.1F 10F 0.1F SCLK SCLK SDATA SDATA 0.01F COMP FSYNC FSYNC AD9833 MCLK VOUT MCLK VOUT DVDD 50 DVDD DGND AGND 0.1F DGND Figure 14. Evaluation Board Layout...
Page 18: Outline Dimensions
AD9833 OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC 4.90 BSC 3.00 BSC PIN 1 0.50 BSC 0.95 0.85 1.10 MAX 0.23 0.75 0.08 0.80 8 0.15 0.27 SEATING 0.40 0 PLANE 0.17 COPLANARITY 0.10...

Analog Devices AD9833 Manual

Quick Links

Need help?

Questions and answers

Related Manuals for Analog Devices AD9833

Summary of Contents for Analog Devices AD9833