Analog Devices AD9833 Manual page 16

AD9833
68HC11/68L11*
PC7
MOSI
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. 68HC11/68L11 to AD9833 Interface
AD9833 to 80C51/80L51 Interface
Figure 12 shows the serial interface between the AD9833 and the
80C51/80L51 microcontroller. The microcontroller is operated
in mode 0 so that TxD of the 80C51/80L51 drives SCLK of the
AD9833, while RxD drives the serial data line SDATA. The
FSYNC signal is again derived from a bit programmable pin on
the port (P3.3 being used in the diagram). When data is to be trans- requirements, the user requires only a power supply, an IBM
mitted to the AD9833, P3.3 is taken low. The 80C51/80L51
transmits data in 8-bit bytes, thus only eight falling SCLK edges
occur in each cycle. To load the remaining 8 bits to the AD9833,
P3.3 is held low after the first 8 bits have been transmitted, and a
second write operation is initiated to transmit the second byte of
data. P3.3 is taken high following the completion of the second
write operation. SCLK should idle high between the two write
operations. The 80C51/80L51 outputs the serial data in a format
that has the LSB first. The AD9833 accepts the MSB first
(the 4 MSBs being the control information, the next 4 bits being
the address, while the 8 LSBs contain the data when writing to a
destination register). Therefore, the transmit routine of the
80C51/80L51 must take this into account and rearrange the bits
so that the MSB is output first.
80C51/80L51*
P3.3
RxD
TxD
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. 80C51/80L51 to AD9833 Interface
AD9833 to DSP56002 Interface
Figure 13 shows the interface between the AD9833 and the
DSP56002. The DSP56002 is configured for normal mode
asynchronous operation with a gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated internally
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0),
and the frame sync signal will frame the 16 bits (FSL = 0).
The frame sync signal is available on pin SC2, but it needs to be
inverted before being applied to the AD9833. The interface to
the DSP56000/DSP56001 is similar to that of the DSP56002.
AD9833*
FSYNC
SDATA
SCLK
AD9833*
FSYNC
SDATA
SCLK
–16–
DSP56002*
SC2
STD
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. DSP56002 to AD9833 Interface
AD9833 EVALUATION BOARD
The AD9833 Evaluation Board allows designers to evaluate the
high performance AD9833 DDS modulator with a minimum
of effort.
To prove that this device will meet the user's waveform synthesis
compatible PC, and a spectrum analyzer along with the evalua-
tion board.
The DDS evaluation kit includes a populated, tested AD9833
printed circuit board. The evaluation board interfaces to the
parallel port of an IBM compatible PC. Software is available
with the evaluation board that allows the user to easily program
the AD9833. A schematic of the evaluation board is shown in
Figure 14. The software will run on any IBM compatible PC
that has Microsoft Windows
®
or Windows 2000 NT installed.
Using the AD9833 Evaluation Board
The AD9833 evaluation kit is a test system designed to simplify
the evaluation of the AD9833. An application note is also avail-
able with the evaluation board and gives full information on
operating the evaluation board.
Prototyping Area
An area is available on the evaluation board for the user to add
additional circuits to the evaluation test set. Users may want to
build custom analog filters for the output or add buffers and
operational amplifiers to be used in the final application.
XO vs. External Clock
The AD9833 can operate with master clocks up to 25 MHz.
A 25 MHz oscillator is included on the evaluation board. How-
ever, this oscillator can be removed and, if required, an external
CMOS clock connected to the part.
Power Supply
Power to the AD9833 evaluation board must be provided exter-
nally through pin connections. The power leads should be twisted
to reduce ground loops.
AD9833*
FSYNC
SDATA
SCLK
, Windows 98, Windows ME,
95
®
REV. A
®